Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

Abstract: An apparatus includes: a first memory mat; a second memory mat adjacent to the first memory mat; a peripheral circuit between the first memory mat and the second memory mat, the peripheral circuit defining a first boundary to the first memory mat and a second boundary to the second memory mat and including a plurality of wiring patterns in a wiring layer; and at least one dummy pattern in the wiring layer arranged on or along the first boundary.

Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

Abstract: Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced.

Abstract: Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.

Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal.

Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: A data writing and reading method is applied to a data storage system. The storage system includes a processor, a charged particle beam excitation modulation component, and a recording medium. The method is performed by the processor. The data writing method includes obtaining to-be-written data; controlling, based on the to-be-written data, the charged particle beam excitation modulation component to generate a charged particle beam array with a target modulation feature; and controlling the charged particle beams in the charged particle beam array to act on the recording medium to generate, in a target area of the recording medium, a target recording feature corresponding to the to-be-written data.

Abstract: An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.

Abstract: An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

Abstract: A switch device includes a driver circuit, a switch circuit and a level transition circuit. The driver circuit includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first terminal coupled to a first reference terminal, and a second terminal coupled to a second reference terminal. The switch circuit includes a control terminal for receiving the output signal. The level transition circuit includes a first terminal for receiving the output signal, a second terminal coupled to a third reference terminal, and a third terminal for receiving the input signal. In a transition interval, the input signal is transitioned from a first input signal level to a second input signal level, the level transition circuit transitions the output signal from a first output signal level to a third output signal level between the first output signal level and a second output signal level.

Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

Abstract: Systems, methods and apparatus are provided for decoupling capacitors for an array of vertically stacked memory cells. Embodiments provide that the decoupling capacitors are electrically coupled to a power bus.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory cells, a bit line selection circuit, including a first main select transistor, and a plurality of first sub-select transistors connected in parallel with each other, and the plurality of first sub-select transistors configured to be the first memory cell through the first bit line to transfer the read current from the first bit line to the first memory cell; and a sense amplifier configured to compare a reference current having a predetermined current value with a memory current drawn by the first memory cell, and output an output signal based on an input voltage, the sense amplifier including an active load, connected to the first main select transistor, comprising a PMOS diode or a NMOS diode configured to lower the input voltage at a sense node.

Abstract: A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is in the testing mode of operation the circuit, receiving test data obtained from read address signals to represent a test state for the bit cells of the memory.

Abstract: An automatic addressing process for devices on a serial bus is disclosed. In one aspect, a controller is communicatively coupled to multiple power supply units (PSUs) over a serial bus. At installation (and may be at start up or reset), the controller sends a signal through the serial bus to a first PSU, which adopts a first address based on a voltage level of the signal and increases the voltage level before passing the signal to a second PSU. The second PSU adopts an address based on the increased voltage level, increments the voltage level of the signal and passes the signal down the bus. Adopted addresses are written to memory and stored in such a manner that power loss will not erase the address. This stepped voltage signal allows multiple identical PSUs to be addressed without reliance on manually-changed dip switches, separate address negotiation software, or the like.

Abstract: In examples, an apparatus includes a first transistor, voltage source, resistor, second transistor, third transistor, and capacitor. The first transistor has a first gate, first source, and first drain, in which the first source is coupled to a first voltage terminal. The resistor is coupled between the first gate and the voltage source. The voltage source is coupled between the resistor and the first voltage terminal. The second transistor has a second gate, a second source, and a second drain, in which the second gate is coupled to the first drain, and the second source is coupled to the first voltage terminal. The third transistor has a third gate, a third source, and a third drain, in which the third drain is coupled to the second drain, and the third source is coupled to a ground terminal. The capacitor is coupled between the first drain and the third gate.

Abstract: Apparatuses, methods, and systems for matrix formation for performing computational operations in memory are included. An embodiment includes a memory having a plurality of levels, wherein each of the plurality of levels includes a plurality of memory cells, voltage circuitry configured to apply sub-threshold voltages to the memory cells of each respective level, a plurality of sense lines, sense circuitry coupled to the plurality of sense lines, wherein the sense circuitry coupled to each respective sense line is configured to sense a state for each of the number of memory cells coupled to that respective sense line responsive to the voltage circuitry applying the sub-threshold voltages to the memory cells of each respective level, and processing circuitry configured to utilize the states for each of the memory cells to form a matrix and perform computational operations on data stored in the memory using the matrix.

Abstract: A memory device is provided. The memory device comprises a memory cell array connected to a first bit line and a complementary bit line, a first bit line sense amplifier configured to sense, amplify and the first bit line signal output a first bit line signal and the complimentary bit signal output on a complementary bit line signal output on the first bit line and the complementary bit line, a charge transfer transistor connected to the first bit line sense amplifier and configured to be gated by a charge transfer signal of a first node, an offset transistor configured to connect the first node and a second node based on an offset removal signal and a pre-charging transistor connected between the second node and a pre-charging voltage line and the pre-charging transistor being configured to pre-charge the first bit line or the complementary bit line based on an equalizing signal.

Abstract: Embodiments relate to a sense amplifier circuit and a data read method. The sense amplifier circuit includes: a first P-type transistor connected to a first signal terminal; a second P-type transistor connected to a second signal terminal; a first N-type transistor connected to a third signal terminal; a second N-type transistor connected to a fourth signal terminal; a first offset cancellation subcircuit configured to connect a first read bit line to a second complementary read bit line in response to a first offset cancellation signal; a second offset cancellation subcircuit configured to connect a first complementary read bit line to a second read bit line in response to a second offset cancellation signal; a first write-back subcircuit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal; and a second write-back subcircuit.

Abstract: An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.

Abstract: A storage array includes a read bit line, a ground, a read bit line switch of the read bit line, and a plurality of storage circuits. Each storage circuit includes a storage unit configured to store data and a read circuit configured to read data from the storage unit. A data input end of the read circuit is connected to a data output end of the storage unit, to read data from the storage circuit, and a data output end of the read circuit is connected to the read bit line, to output the read data to the read bit line. There is at least one PMOS transistor in an electric leakage path from a power supply to the read bit line in the read circuit, to suppress a leakage current in the read circuit.

Abstract: An internal power generation circuit comprises: a first internal power generation circuit, configured to generate a first power signal based on an external power signal, and including an NMOS transistor, voltage of the first power signal being lower than voltage of the external power signal by threshold voltage of one NMOS transistor, wherein the circuit further includes: a booster unit performing boosting on the first power signal, voltage of a boosted signal being higher than the voltage of the first power signal by at least the threshold voltage of one NMOS transistor; a self-starting feedback circuit configured to generate an output voltage signal based on the boosted signal and the external power signal, wherein before the output voltage signal reaches a target voltage, the output voltage signal follows the external power signal, and after the output voltage signal reaches the target voltage, the output voltage signal holds the target voltage.

Abstract: The invention provides a sense amplifier circuit, a method for operating same, and a fabrication method for same. The sense amplifier circuit includes: an amplifier electrically connected to a memory cell of a semiconductor memory; and a pre-amplifier located between the amplifier and the memory cell, where the pre-amplifier is configured to pre-amplify an electrical signal transmitted from the memory cell to the amplifier. In this way, the pre-amplifier is provided between the amplifier and the memory cell, such that the electrical signal stored in the semiconductor memory can be output after two stages of amplification by the pre-amplifier and the amplifier, thereby avoiding the problem that the electrical signal output from the memory cell cannot be accurately received and output in a case of a small sense margin of a signal of the sense amplifier.

Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.

Abstract: A storage device includes: a controller that exchanges data with a host through an interface; memory devices that store the data; a power supply circuit that outputs internal voltages, required for the controller and the memory devices, using an external voltage received through the interface; a distribution circuit that provides an operating voltage to the memory devices; and a discharge circuit including a first comparator that compares a first internal voltage, among the internal voltages, with a reference voltage and a second comparator that compares a second internal voltage, different from the first internal voltage, with the reference voltage, and including an operating circuit that computes an output of the first comparator and an output of the second comparator to output a discharge control signal determining whether the operating voltage has been discharged.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Abstract: Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.

Abstract: A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

Abstract: A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.

Abstract: Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.

Abstract: The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.

Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.

Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: An apparatus includes a subword driver configured to drive a subword line, wherein the subword driver includes a transistor coupled to the subword line, a word driver control circuit configured to provide a first control signal and a second control signal, and a word driver configured to receive the first and second control signals, and based on the first control signal provide a driving signal including a plurality of reset pulses to the transistor of the subword driver to activate the transistor a corresponding plurality of times to discharge the subword line, and further provide the driving signal including a transition following the plurality of reset pulses to activate the transistor to further discharge the subword line.

Abstract: A monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify a current amount between a terminal to which a power voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal of which a frequency is adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size greater than the first size, and wherein the oscillator includes a plurality of transistors having a third size greater than the first size.

Abstract: An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: The present disclosure relates to a method and apparatus for determining a signal margin (SM) of a memory cell, a storage medium and an electronic device, and relates to the technical field of integrated circuits. The method for determining an SM of a memory cell includes: when the memory cell performs write and read operations, determining a sense signal threshold of the memory cell under an influence of a noise; and determining, based on the sense signal threshold, an actual SM of the memory cell during data reading.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Devices and techniques are disclosed herein to provide a number of different bias signals to each of multiple signal lines of an array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period, to determine settling times of each of the multiple signal lines to the target voltage for the number of different bias signals, to determine a functional compensation profile for an array of memory cells comprising a relationship between the different bias signals and the determined settling times of the multiple signal lines.

Abstract: According to at least one aspect, a controller having a mode of operation including one of an on mode and an off mode is provided including a voltage supply node, a mode of operation signal node, a powered component, a switching device coupled in series between the voltage supply node and the powered component, a power supply detector coupled to the switching circuit, the voltage supply node, and the mode of operation signal node, the power supply detector being configured to receive a mode of operation signal indicative of the mode of operation of the controller from the mode of operation signal node, determine that the controller is in the off mode based on the mode of operation signal, and control the switching device to prevent a current from passing from the voltage supply node to the powered component responsive to determining that the controller is in the off mode.

Abstract: A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.