Read/write Circuit Patents (Class 365/189.011)
  • Patent number: 10416927
    Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Patent number: 10403384
    Abstract: A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 3, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10381054
    Abstract: The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dhani Reddy Sreenivasula Reddy, Vinay Bhat Soori
  • Patent number: 10332594
    Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Miyashita, Jun Deguchi
  • Patent number: 10318168
    Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Glen E. Hush
  • Patent number: 10318365
    Abstract: Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 11, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sheng Li, Norman P. Jouppi, Doe Hyun Yoon
  • Patent number: 10310858
    Abstract: Apparatus and a corresponding method for controlling a transition between use of first processing circuitry and second processing circuitry to execute program instructions are provided. Transition monitoring storage selects an entry for a load program instruction executed during the transition in dependence on a memory address from which a value is to be loaded and stores a program order timestamp for the load program instruction, unless a valid previously stored program order timestamp in the entry precedes the program order timestamp. Thus the oldest timestamp of an load instruction executed in the transition is held. At either the start or end (or both) of the transition the content of the transition monitoring storage is cleared.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: June 4, 2019
    Assignee: The Regents of the University of Michigan
    Inventors: Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Scott Mahlke, Jiecao Yu
  • Patent number: 10297329
    Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 21, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Yingda Dong, Masaaki Higashitani
  • Patent number: 10269408
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 23, 2019
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10242730
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 26, 2019
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10199080
    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah
  • Patent number: 10198376
    Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 5, 2019
    Assignee: Marvell World Trade Ltd.
    Inventor: Jerry Hongming Zheng
  • Patent number: 10163926
    Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 25, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10146359
    Abstract: A system is disclosed. The system can comprise dynamic drive circuitry configured to drive a plurality of electrodes on a touch screen. The system can also comprise a switching circuit configured to selectively couple the dynamic drive circuitry to one or more of the plurality of electrodes. The system can also comprise a display circuitry configured to selectively update a plurality of display pixels on the touch screen. The dynamic drive circuitry can be configured to set its output based on which of the plurality of electrodes are selectively coupled to the first drive circuitry and which of the display pixels are updated by the display circuitry.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 4, 2018
    Assignee: Apple Inc.
    Inventors: Howard Tang, Christoph H. Krah, Paolo Sacchetto, Chaohao Wang
  • Patent number: 10134751
    Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Akutsu, Ryota Katsumata
  • Patent number: 10115470
    Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabio Enrico Carlo Disegni, Giuseppe Castagna, Maurizio Francesco Perroni
  • Patent number: 10109637
    Abstract: The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow trench isolation (STI) positioned between the first and second regions of the substrate; a first transistor with a channel region is positioned on the first region of the substrate, and spacer positioned on the first region of the substrate and the STI; and a gate metal positioned on the spacer. The gate metal includes a gate contact region positioned over the first source/drain region of the substrate, and surrounding the channel region. Across-couple region extends laterally from the gate contact region to the source/drain region of a second transistor formed on the second region of the substrate.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Randy W. Mann, Bipul C. Paul
  • Patent number: 10102901
    Abstract: A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of the first operational voltage, the second operational voltage, the third operation voltage, the fourth operation voltage, or a combination thereof, by a bias voltage difference.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh Shah
  • Patent number: 10079063
    Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10032491
    Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: July 24, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Patrick A. La Fratta
  • Patent number: 10032502
    Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 24, 2018
    Assignee: Uniquify IP Company, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10020072
    Abstract: Systems and methods are provided to detect a developed bad word-line of a flash memory. Embodiments provide an improved Background media scan (BGMS) process that can predict at the end of a block read if a word-line will potentially become bad with the use of the flash memory. Accordingly, data from the potentially bad block can be recovered and the block can be retired. The embodiments can minimize the need for the expensive chip-kill method.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 10, 2018
    Assignee: SK Hynix Inc.
    Inventors: Haibo Li, Sangsik Kim, Juhyeon Han
  • Patent number: 9940983
    Abstract: A channel controlling device includes: a multiplexing circuit coupled to multiple channels for selecting a particular channel from the channels to output a channel data according to a selection signal, wherein the channels correspond to multiple predetermined digital numbers; a sorting circuit arranged to sort the predetermined digital numbers to form multiple sorted digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selection signal according to the plurality of sorted digital numbers.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 10, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Chen-Yu Weng, Wen-Kai Liu
  • Patent number: 9922693
    Abstract: The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence. Current flow and blockage scores are obtained and stored for the current refresh sequence. The current flow and blockage scores are used to update (by averaging, for example) the existing flow and blockage scores for the current refresh sequence. The next refresh sequence is then chosen from amongst a plurality of refresh sequences in a way that favors a high flow score and a low blockage score.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: March 20, 2018
    Assignee: Altera Corporation
    Inventors: Kay Keat Khoo, Weng Li Leow
  • Patent number: 9905300
    Abstract: A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 27, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Makoto Kitagawa, Takafumi Kunihiro, Wataru Otsuka, Tomohito Tsushima
  • Patent number: 9892772
    Abstract: This technology relates to a semiconductor system. The semiconductor system may include a first semiconductor device capable of outputting a clock signal, a data strobe signal, and data; and a second semiconductor device capable of generating a division enable signal and a data input clock signal in response to the clock signal when performing a write operation, generating an internal strobe signal by dividing the data strobe signal in response to the division enable signal, and aligning the data in response to the internal strobe signal, wherein the first semiconductor device receives the division enable signal from the second semiconductor device and trains the data strobe signal so that the data strobe signal is output in a predetermined section.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 13, 2018
    Assignee: SK Hynix Inc.
    Inventor: Keun-Soo Song
  • Patent number: 9852029
    Abstract: A method, system and a computer program product for managing a computing system crash. Memory of the computing system is separated into at least two classifications, referred to herein as a dumpable area and a non-dumpable area. Upon detection of an operating system crash in the computing system, an operating system module prevents a dumping operation of the memory, including preventing access to the dumpable memory area, and divides the non-dumpable area into a new dumpable area and a new non-dumpable area. At such time as the operating system is rebooted, the dumping operation is initiated and completed in the dumpable area, and resumed operations use the non-dumpable area.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventor: Prateek Goel
  • Patent number: 9852028
    Abstract: A system and a computer program product for managing a computing system crash. Memory of the computing system is separated into at least two classifications, referred to herein as a dumpable area and a non-dumpable area. Upon detection of an operating system crash in the computing system, an operating system module prevents a dumping operation of the memory, including preventing access to the dumpable memory area, and divides the non-dumpable area into a new dumpable area and a new non-dumpable area. At such time as the operating system is rebooted, the dumping operation is initiated and completed in the dumpable area, and resumed operations use the non-dumpable area.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventor: Prateek Goel
  • Patent number: 9846554
    Abstract: A storage system and method for generating block allocation groups based on deterministic data patterns are provided. A storage system is provided comprising a memory comprising a plurality of blocks and a controller. The controller is configured to infer characteristics of the memory from data patterns of data stored in the plurality of blocks; and group the plurality of blocks based on the inferred characteristics of the memory.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: December 19, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Joanna Lai, Nian Niles Yang
  • Patent number: 9786025
    Abstract: Signal processing including decoding and format conversion is executed on compressed image data at a high speed by simple control. A decoder decodes compressed image data in units of blocks and writes the decoded data in the blocks into a decoded data memory. A progress notification unit generates a progress signal indicating a state of progress that data is being decoded or written into the decoded data memory by the decoder and outputs the signal to a format conversion unit per picture. The format conversion unit reads out the decoded data from the decoded data memory and format-converts the data, and writes the format-converted data into a format-converted data memory. In reading out data from the decoded data memory, the format conversion unit acquires information indicating an address of decoded data readable from the decoded data memory from the progress signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki Kaya, Katsushige Matsubara
  • Patent number: 9773542
    Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: September 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Timothy Mowry Hollis, Michael Joseph Brunolli
  • Patent number: 9740255
    Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: August 22, 2017
    Assignee: Tohoku University
    Inventors: Takashi Ohsawa, Tetsuo Endoh
  • Patent number: 9705505
    Abstract: There is provided a reconfigurable semiconductor device including a plurality of logic units connected to each other using an address line or a data line, each logic unit including a plurality of address lines, a plurality of data lines, a clock signal line configured to receive a system clock signal, a delay element configured to delay the system clock signal, a memory cell unit configured to operate in synchronization with a clock signal, and an address decoder configured to decode an address signal to output the decoded signal to the memory cell unit. The logic unit configuring a combination logic circuit operates in synchronization with a delayed clock signal outputted from the delay element.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 11, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Masayuki Satou, Isao Shimizu
  • Patent number: 9691740
    Abstract: A semiconductor device includes: a plurality of semiconductor chips which are stacked; a plurality of circuit blocks respectively included in the plurality of semiconductor chips; a first power supply domain that supplies power and stops the supply of the power to one of the plurality of circuit blocks independently of the other circuit blocks; and a second power supply domain that supplies power and stops the supply of the power to at least two of the plurality of circuit blocks in common and supplies the power and stops the supply of the power independently of the other circuit blocks.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Akihiro Chiyonobu, Hironori Kawaminami
  • Patent number: 9609245
    Abstract: A semiconductor apparatus, comprising a decoder arranged in a path between a first power supply line and a second power supply line and configured to receive a signal and decode the signal, a switch portion arranged, in series with the decoder, in the path between the first power supply line and the second power supply line, and a control unit configured to set the switch portion in a conductive state so as to cause the decoder to decode the signal after the signal has changed from one of high level and low level to the other.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 28, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichiro Iwata, Kazuki Ohshitanai, Hiroo Akabori, Takeshi Akiyama, Hiroyuki Morita
  • Patent number: 9595312
    Abstract: The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence. Current flow and blockage scores are obtained and stored for the current refresh sequence. The current flow and blockage scores are used to update (by averaging, for example) the existing flow and blockage scores for the current refresh sequence. The next refresh sequence is then chosen from amongst a plurality of refresh sequences in a way that favors a high flow score and a low blockage score.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 14, 2017
    Assignee: Altera Corporation
    Inventors: Kay Keat Khoo, Weng Li Leow
  • Patent number: 9576622
    Abstract: In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
  • Patent number: 9560446
    Abstract: A sound source locator efficiently employs a distributed physical or logical microphone array to determine a location of a source of a sound. In some instances, the sound source locator is deployed in an augmented reality environment. The sound source locator detects sound at a plurality of microphones, generates a signal corresponding to the sound, and causes attributes of signal as generated at the plurality of microphones to be stored in association with the corresponding microphone. The sound source locator uses these stored attributes to identify multiple groups of the plurality of microphones from which delays between the times the signal is generated can be used to compute the location of the source of the sound.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 31, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Samuel Henry Chang, Wai C. Chu
  • Patent number: 9552886
    Abstract: A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Minsu Kim, Kang-Bin Lee, Kitae Park
  • Patent number: 9473991
    Abstract: Combinational networks provide simultaneous connectivity via networks of different network type between user equipment. For communication sessions on different network types, belonging to the same user equipment, a correlation check is enabled by introduction of an identifier denoted as Combinational Call Indicator (CCI). This CCI identifier in combination with the known Calling Line Identity (CLI) identifier enables user equipment and other and network entities to perform a correlation check between ongoing, or to be established, CScalls and PS-sessions. A user equipment, setting up a related communication session, sets the CCI identifier and provides the CCI identifier during the communication session setup towards the receiving user equipment or network entity, which is enabled to check whether the last received communication session is correlated to the earlier established session due to the presence of the CCI identifier.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: October 18, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Rogier Noldus, Jos den Hartog, Rakesh Taori
  • Patent number: 9472269
    Abstract: Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Nathaniel R. Chadwick, John B. Deforge, Ezra D. B. Hall, Kirk D. Peterson
  • Patent number: 9449680
    Abstract: A write assist circuit capable of writing data to a memory cell with a bit line and a bit line bar is provided. The write assist circuit includes a clamping circuit, and first and second sense amplifiers. The clamping circuit is coupled to first and second nodes to prevent the voltage of the first and second nodes from being lower than a data-retention voltage. The first and second nodes are supplied with first and second voltage sources. The first and second sense amplifier are utilized to detect the voltage of the bit line or the bit line bar, amplify the voltage and pull down the voltage of one of the first or second node according to the data while the voltage of the other one of the first or second node is kept at a power supply voltage level.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: September 20, 2016
    Assignee: MEDIATEK INC.
    Inventor: Shih-Huang Huang
  • Patent number: 9443605
    Abstract: Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb. The techniques may include compensating for how program disturb depends on the location of the word line that is selected for programming. In one aspect, the voltage that is applied to the control gates drain side select transistors of unselected NAND strings is adjusted during programming based on temperature. Greater temperature compensation may be applied when the selected word line is closer to the drain side select transistors.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Jian Chen, Yingda Dong, Jiahui Yuan
  • Patent number: 9431080
    Abstract: A system includes a first plurality of memory macros and a first tracking circuit associated with a memory macro of the first plurality of memory macros. Each memory macro of the first plurality of memory macros includes a corresponding global control circuit configured to receive a first reset signal. The first tracking circuit is configured to generate the first reset signal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Annie-Li-Keow Lum
  • Patent number: 9411722
    Abstract: An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: August 9, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Kian-Chin Alex Yap
  • Patent number: 9350357
    Abstract: A reconfigurable semiconductor device includes a plurality of logic units connected to each other via address lines or data lines, each of the logic units including: a plurality of address lines; a plurality of data lines; a first address decoder that decodes addresses inputted from some of the address lines; a second address decoder that decodes addresses inputted from the other of the address lines; a first memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the first address decoder; and a second memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the second address decoder.
    Type: Grant
    Filed: October 27, 2013
    Date of Patent: May 24, 2016
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Masayuki Sato, Koshi Sato
  • Patent number: 9311967
    Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 12, 2016
    Assignee: Apple Inc.
    Inventors: Ajay Kumar Bhatia, Anshul Y. Mehta, Amrinder S. Barn, Greg M. Hess
  • Patent number: 9298201
    Abstract: The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic. The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vijay A. Mathiyalagan, Siva Rama K. Pullelli, Saravanan Sethuraman, Kenneth L. Wright
  • Patent number: 9286975
    Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Daniel J. Chu, Kiran Pangal, Nathan R. Franklin, Prashant S. Damle, Hu Chaohong
  • Patent number: 9171805
    Abstract: Provided is a substrate identification circuit that generates a numeric value, whose duplication is difficult and which is proper to a substrate, at low cost and a semiconductor device having such a substrate identification circuit. A substrate identification circuit 304 is produced by utilizing variations in characteristics among TFTs formed on a substrate having an insulating surface. The substrate identification circuit 304 includes a plurality of proper bit generating circuits, each of which is constructed from a plurality of TFTs and outputs a one-bit random number based on variations in characteristics among the plurality of TFTs. The substrate identification circuit generates a numeric value proper to the substrate using the one-bit random number. The substrate identification circuit may include a circuit that makes a judgment by comparing the numeric value proper to the substrate with an identification number inputted from the outside.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Shunpei Yamazaki