Read/write Circuit Patents (Class 365/189.011)
  • Patent number: 12033718
    Abstract: A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: July 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Kensuke Ota, Marina Yamaguchi, Masatoshi Yoshikawa
  • Patent number: 12021548
    Abstract: A method of encoding input data. The method includes receiving a plurality of data bits of a bit stream. The method further includes forming words using the plurality of data bits to create a plurality of data packets including a first data packet. The method further includes encoding the words of the first data packet into coded words, partitioning the coded words into a plurality of blocks of M words each and integrating the coded words in each block in an interleaved order to generate a coded data packet for transmission through a communication channel.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: June 25, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Aliazam Abbasfar
  • Patent number: 12009036
    Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: June 11, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Hongtao Liu, Dejia Huang, Wenzhe Wei, Ying Huang
  • Patent number: 12002505
    Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Riccardo Pazzocco, Angelo Visconti
  • Patent number: 11990204
    Abstract: A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer of a memory cell and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer. a refresh operation is performed to return the voltage of the channel semiconductor layer of a selected word line to a first data retention voltage thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which a voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with a switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: May 21, 2024
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Koji Sakui, Nozomu Harada
  • Patent number: 11983439
    Abstract: A program method of a memory device having planes includes receiving a program command, obtaining an address associated with the program command, determining a first plane of the planes according to the address, and resetting a page register of the first plane without resetting one or more page registers of one or more remaining planes of the planes.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: May 14, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES, INC.
    Inventors: Xiang Ming Zhi, Augustus Tsai
  • Patent number: 11961567
    Abstract: A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: April 16, 2024
    Assignee: PUFsecurity Corporation
    Inventors: Kai-Hsin Chuang, Chi-Yi Shao, Chun-Heng You
  • Patent number: 11948627
    Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 11935618
    Abstract: An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: March 19, 2024
    Assignee: QUICKLOGIC CORPORATION
    Inventors: Ket Chong Yap, Chihhung Liao, Shieh Huan Yen
  • Patent number: 11923020
    Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: March 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroyuki Ishii, Yuji Nagai, Makoto Miakashi, Tomoko Kajiyama, Hayato Konno
  • Patent number: 11908540
    Abstract: A semiconductor system includes a semiconductor apparatus and a control device. The semiconductor apparatus performs a preset operation in response to a command signal. The control device controls a temperature adjustment operation so that first temperature information and second temperature information correspond to each other.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: In Jong Jang
  • Patent number: 11895842
    Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Changyeon Yu, Pansuk Kwak
  • Patent number: 11894096
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area. The memory controller is configured to control read operations of the memory device. The memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11887693
    Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 30, 2024
    Inventor: Dmitri Yudanov
  • Patent number: 11868662
    Abstract: A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 9, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, Alexander Bazarsky, David Avraham
  • Patent number: 11862262
    Abstract: A memory system includes: nonvolatile memory devices and a memory controller confirming a programming time for each word line of each of the nonvolatile memory devices and calculating a target programming time on the basis of the programming time for each word line. Each of the nonvolatile memory devices receives the target programming time from the memory controller, and adjusts the programming time for each word line on the basis of the target programming time. When the adjustment of the programming time for each word line is completed, the memory controller confirms a variation width of a writing speed of the memory system for a predetermined time, and sets the target programming time as a final target programming time when the variation width of the writing speed is smaller than a reference value.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Youngbong Kim
  • Patent number: 11862252
    Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Minjian Wu
  • Patent number: 11854661
    Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 11837287
    Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
  • Patent number: 11823769
    Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.
    Type: Grant
    Filed: August 28, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11811401
    Abstract: A method for operating an integrated circuit chip including multiple tiles (202a-202d) includes determining a configuration for the tiles for execution of a computation. When the configuration for the tiles satisfies a first criterion, the integrated circuit is operated in a first mode, including concurrently receiving respective input data (208a, 208b) at each of the tiles (202a-202d).
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 7, 2023
    Assignee: Google LLC
    Inventor: Reiner Pope
  • Patent number: 11803328
    Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 31, 2023
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 11790988
    Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 17, 2023
    Inventors: Ji-Hoon Lim, Bilal Ahmad Janjua
  • Patent number: 11789893
    Abstract: A memory system comprises a memory and a physical layer circuit. The memory system comprises a memory, a data bus and a single-pin STB. The memory receives a parallel command though the data bus, and receives a serial command through the STB. The physical layer circuit is configured to transmit the parallel command to the data bus. The physical layer circuit is configured to convert STB input data from the controller into the serial command and transmit the serial command to the STB.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: October 17, 2023
    Assignee: ETRON TECHNOLOGY, INC.
    Inventor: Chun Shiah
  • Patent number: 11776597
    Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: October 3, 2023
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani, Kai Lun Hsiung, Venkata Ramana Malladi, Rahul Ranjan, Naveen Kumar Korada
  • Patent number: 11763882
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 11727995
    Abstract: A semiconductor memory device includes: first conductive layers; second conductive layers; a first semiconductor layer disposed between the first conductive layers and the second conductive layers; a charge storage layer that includes a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second part disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor memory device is configured such that a read operation and a first operation performed before the read operation are performable. In the first operation: a first voltage is supplied to the first wiring; and a second voltage smaller than the first voltage is supplied to an n-th second conductive layer counted from the one side in the first direction.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventor: Shingo Nakazawa
  • Patent number: 11715530
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Patent number: 11651804
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Chiting Cheng, Pankaj Aggarwal, Yen-Huei Chen, Cheng Hung Lee, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Jhon Jhy Liaw
  • Patent number: 11631467
    Abstract: Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: April 18, 2023
    Assignee: Macronix International Co., Ltd.
    Inventors: Yung-Chun Lee, Yu-Ming Huang, Han-Wen Hu
  • Patent number: 11586389
    Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Patent number: 11581037
    Abstract: Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: February 14, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaonan Chen, Zhongze Wang, Yandong Gao, Mustafa Badaroglu
  • Patent number: 11556251
    Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ali Mohammadzadeh, Jung Sheng Hoei, Dheeraj Srinivasan, Terry M. Grunzke
  • Patent number: 11557334
    Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. Each non-volatile memory cell is configured to store a plurality of bits of a plurality of logical pages including at least a first bit of a first logical page, a second bit of a second logical page and a third bit of a third logical page. The control circuits are configured to select a subset of the plurality of logical pages for reading, perform pre-read steps, and read a first and at least a second selected logical page of the subset without performing pre-read steps between reading the first and second selected logical pages.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: January 17, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Subin CP, Gopu S, Sainath Viswasarai
  • Patent number: 11538516
    Abstract: A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Hiroshi Akamatsu
  • Patent number: 11532352
    Abstract: This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the virtual ground, a second transistor coupled to at least the first data storage line and the first transistor, a third transistor coupled to at least the second data storage line and the read word line, and a fourth transistor coupled at least the first data storage line and the read word line.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 20, 2022
    Assignee: SYNOPSYS, INC.
    Inventors: M. Sultan M. Siddiqui, Sudhir Kumar Sharma, Sudhir Kumar, Ravindra Kumar Shrivastava
  • Patent number: 11527272
    Abstract: A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: December 13, 2022
    Assignee: XX Memory Technology Corp.
    Inventors: Li Che Chen, Cheng Jye Liu, Heng Cheng Yeh
  • Patent number: 11521677
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a compensated kick time in response to determining the target word line voltage is not greater than a predetermined voltage design limit. The control circuit applies the kicking voltage to the selected ones of word lines for the compensated kick time thereby enabling a word line voltage to reach one of a plurality of reference voltages quickly without exceeding the predetermined voltage design limit.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng
  • Patent number: 11521675
    Abstract: A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 6, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kou Tei, Anirudh Amarnath, Ohwon Kwon
  • Patent number: 11514985
    Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sundaravadivel Rajarajan, Srivatsan Venkatesan, Iniyan Soundappa Elango, Robert Douglas Cassel
  • Patent number: 11500613
    Abstract: A memory unit with a multiply-accumulate assist scheme for a plurality of multi-bit convolutional neural network based computing-in-memory applications is controlled by a reference voltage, a word line and a multi-bit input voltage. The memory unit includes a non-volatile memory cell, a voltage divider and a voltage keeper. The non-volatile memory cell is controlled by the word line and stores a weight. The voltage divider includes a data line and generates a charge current on the data line according to the reference voltage, and a voltage level of the data line is generated by the non-volatile memory cell and the charge current. The voltage keeper generates an output current on an output node according to the multi-bit input voltage and the voltage level of the data line, and the output current is corresponding to the multi-bit input voltage multiplied by the weight.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 15, 2022
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Han-Wen Hu, Kuang-Tang Chang
  • Patent number: 11487548
    Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 1, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Vijay Chinchole, Nisha Padattil Kuliyampattil, Sonam Agarwal, Akash Agarwal, Pavithra Devaraj, Yan Li
  • Patent number: 11468929
    Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: October 11, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
  • Patent number: 11386938
    Abstract: A memory device includes: memory cells; an operation mode determiner for determining any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device; a pad control signal generator for generating a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode; a pad controller for receiving the signal through the determined pad according to the pad control signal; an internal command generator for generating an internal operation command corresponding to the data movement command according to the determined operation mode; and an operation controller for performing one of a read operation of reading first target data from the memory cells and a program operation of storing second target data in the memory cells, based on the internal operation command.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung Hyun Chung
  • Patent number: 11385753
    Abstract: A switching unit of a touch panel device switches between a first connection state in which, among a plurality of drive wiring lines, a first drive wiring line and a second drive wiring line adjacent to each other are connected, and a second connection state in which, among the plurality of drive wiring lines, the first drive wiring lines adjacent to each other are connected to each other and the second drive wiring lines adjacent to each other are connected to each other.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: July 12, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuhiro Sugita, Kazutoshi Kida, Hiroshi Fukushima
  • Patent number: 11372550
    Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Glen E. Hush
  • Patent number: 11367500
    Abstract: Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Katherine H. Chiang
  • Patent number: 11361833
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Patent number: 11348633
    Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kazutaka Miyano
  • Patent number: 11295818
    Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Jin Shin, Ji Su Kim, Dae Seok Byeon, Ji Sang Lee, Jun Jin Kong, Eun Chu Oh