Read/write Circuit Patents (Class 365/189.011)
  • Patent number: 11114171
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
  • Patent number: 11107547
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a chip selection signal, a command/address signal and a clock signal. The first semiconductor device outputs first external data and a strobe signal during a write operation in a test mode and receives second external data to adjust an output moment of the strobe signal during a read operation in the test mode. The second semiconductor device is synchronized with the strobe signal to latch input data generated from the first external data during the write operation according to the chip selection signal and the command/address signal. The second semiconductor device generates output data from the input data and outputs the output data as the second external data during the read operation according to the chip selection signal and the command/address signal.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Kwang Soon Kim
  • Patent number: 11081474
    Abstract: Systems and methods for dynamically assigning memory array die to CMOS die of a plurality of stacked die during memory operations are described. The plurality of stacked die may be vertically stacked and connected together via one or more vertical through-silicon via (TSV) connections. The memory array die may only comprise memory cell structures (e.g., vertical NAND strings) without column decoders, row decoders, charge pumps, sense amplifiers, control circuitry, page registers, or state machines. The CMOS die may contain support circuitry necessary for performing the memory operations, such as read and write memory operations. The one or more vertical TSV connections may allow each memory array die of the plurality of stacked die to communicate with or be electrically connected to one or more CMOS die of the plurality of stacked die.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Tung Thanh Hoang, Martin Lueker-Boden, Anand Kulkarni
  • Patent number: 11069415
    Abstract: The non-volatile memory device includes a memory cell array including a plurality of memory cells and a voltage generator configured to supply a voltage to the memory cell array. The voltage generator includes a charge pump circuit, a switching circuit, and a stage controller. The charge pump circuit includes a plurality of pump units and is configured to output a pump voltage and a pump current in accordance with a number of pump units that have received an input voltage among the plurality of pump units. The switching circuit is configured to output the pump voltage. The stage controller is configured to receive an input signal corresponding to the pump current and perform a stage control operation of generating a stage control signal for controlling the number of pump units to be driven.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-heon Baek, Dae-seok Byeon, Ki-chang Jang, Young-sun Min
  • Patent number: 11031067
    Abstract: A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Mi-Hyun Hwang
  • Patent number: 11017825
    Abstract: A memory circuit includes: memory cells each including a storage transistor having a first configuration; and a tracking circuit including: a tracking bit line having first and second intermediary nodes; a tracking word line; a first finger circuit (coupled between the first intermediary node and a reference voltage node) including: a first set of first tracking cells, each including a first shadow transistor having the first configuration; and a second finger circuit (coupled between the second intermediary node and the reference voltage node) including: a second set of second tracking cells, each including a second shadow transistor having the first configuration; gate terminals of the first and second shadow transistors being coupled with the tracking word line; and a switch configured to selectively couple the first intermediary node with the second intermediary node and thereby selectively couple the first and second finger circuits in parallel.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Jacklyn Chang
  • Patent number: 10937468
    Abstract: Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dale H. Hiscock, Michael Kaminski, Joshua E. Alzheimer, John H. Gentry
  • Patent number: 10923178
    Abstract: The present disclosure generally relates to enhanced write performance by taking into consideration user write performance preferences as well as enhanced post write read (EPWR) scheduling. The user provides the write performance preferences to the data storage device. When a write operation happens, the data storage device checks the write performance preference for the current LBA as well as the write performance preference for the previous LBA. The data storage device will also check whether the current word line is scheduled for EPWR. Based upon the write performance preferences for the LBAs and the EPWR scheduling, the data can be written out of order to meet the user's write performance preferences. If the data is written out of order, the flash translation layer (FLT) is informed of the switch.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Refael Ben-Rubi
  • Patent number: 10916314
    Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Jin Shin, Ji Su Kim, Dae Seok Byeon, Ji Sang Lee, Jun Jin Kong, Eun Chu Oh
  • Patent number: 10896004
    Abstract: High-efficiency control technology for non-volatile memory. A controller allocates spare blocks of a non-volatile memory to provide an active block and writes data issued by a host to the active block. The controller further uses the active block as the destination for data transferred from a first source block when there are fewer spare blocks than the threshold amount. When a second source block meets the transfer requirements, the controller uses the active block as the destination for data transferred from the second source block.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 19, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Ting-Han Lin, Che-Wei Hsu
  • Patent number: 10878100
    Abstract: A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Connor, Bruce Querbach
  • Patent number: 10872656
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: writing a first data and a second data to a first physical erasing unit; copying the first data from the first physical erasing unit to a second physical erasing unit; and copying the second data from the first physical erasing unit to a third physical erasing unit, wherein the memory sub-module to which the second physical erasing unit belongs is different from the memory sub-module to which the third physical erasing unit belongs.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10867662
    Abstract: Systems, apparatuses and methods related to subarray addressing for electronic memory and/or storage are described. Concurrent access to different rows within different subarrays may be enabled via independent subarray addressing such that each of the subarrays may serve as a “virtual bank.” Accessing the different rows as such may provide improved throughput of data values accessed from the respective rows being sent to a destination location. For instance, one such apparatus includes a plurality of subarrays within a bank of a memory device. Circuitry within the bank is coupled to the plurality of subarrays. The circuitry may be configured to activate a row at a particular ordinal position in a first subarray during a time period and a row at a different ordinal position in a second subarray of the plurality of subarrays during the same time period.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 10867661
    Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Christopher J. Kawamura
  • Patent number: 10846008
    Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Daniel Doyle
  • Patent number: 10795582
    Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Glen E. Hush
  • Patent number: 10783070
    Abstract: A memory system comprises a first memory including physical blocks, a second memory storing a first correspondence table in which a logical cluster address corresponding to an address assigned to data received from a host is correlated with a logical group number corresponding to a block group and a logical cluster number corresponding to a location within the block group, and a second correspondence table in which first physical block numbers corresponding to first physical blocks are correlated with a first logical group number and second physical block numbers corresponding to second physical blocks are correlated with a second logical group number, and a controller circuit that updates the first correspondence table when new data is written to the first physical blocks, and the second correspondence table, without changing the first corresponding table, when data is moved from the first to the second physical blocks.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroki Matsudaira
  • Patent number: 10763367
    Abstract: A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Purdue Research Foundation
    Inventors: Tillmann C. Kubis, Prasad Sarangapani
  • Patent number: 10748916
    Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Akutsu, Ryota Katsumata
  • Patent number: 10734048
    Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yadhu Vamshi Vancha, James Hart, Jeffrey Koon Yee Lee, Tz-Yi Liu, Ali Al-Shamma, Yingchang Chen
  • Patent number: 10734061
    Abstract: In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 4, 2020
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10658057
    Abstract: A semiconductor memory device of one embodiment includes a p-type first semiconductor region, n word lines from the first to nth word lines stacked on the first semiconductor region in a first direction, an n-type second semiconductor region, a semiconductor layer between the first semiconductor region and the second semiconductor region, extending in the first direction, and intersecting with the n word lines, and a control circuit which, when verifying whether or not a kth memory cell provided in a region where a kth (4<k<n) word line and the semiconductor layer intersect with each other has reached a desired threshold voltage, executes a first verify operation of applying a first voltage between the first semiconductor region and the second semiconductor region and a second verify operation of applying a second voltage different from the first voltage, between the first semiconductor region and the second semiconductor region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Takashi Maeda
  • Patent number: 10644001
    Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 5, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10628085
    Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Patent number: 10622065
    Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniele Balluchi, Paolo Amato, Graziano Mirichigni, Danilo Caraccio, Marco Sforzin, Marco Dallabora
  • Patent number: 10613781
    Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ashot Melik-Martirosian
  • Patent number: 10600454
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-su Jang, Man-jae Yang, Jeong-don Ihm, Go-eun Jung, Byung-hoon Jeong, Young-don Choi
  • Patent number: 10599599
    Abstract: A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Kawai, Yohichi Miwa
  • Patent number: 10586585
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 10, 2020
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10571944
    Abstract: A voltage generator which generates an internal voltage based on a varying voltage derived from the internal voltage includes a feedback control circuit configured to variably transmit the varying voltage responsive to a control signal to generate a feedback voltage. A voltage generation circuit is configured to generate the internal voltage based on the feedback voltage.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-sang Park
  • Patent number: 10553611
    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
  • Patent number: 10529433
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Patent number: 10522211
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array an array of memory cells via a sense line. The sensing circuitry is configured to sense, as a voltage associated with a second operand of a logical function, a voltage on the sense line corresponding to a first logical data value resulting in part from reading a first memory cell of the array of memory cells associated with a first operand of the logical function.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10510827
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Patent number: 10416927
    Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Patent number: 10403384
    Abstract: A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 3, 2019
    Inventor: Darryl G. Walker
  • Patent number: 10381054
    Abstract: The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dhani Reddy Sreenivasula Reddy, Vinay Bhat Soori
  • Patent number: 10332594
    Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory, a read circuit array, a multiply-accumulate operator array, a first bus, an operation controller circuit, and a second bus. The read circuit array reads the data from the nonvolatile memory. The multiply-accumulate operator array receives the data read from the read circuit array. The first bus is connected between the read circuit array and the multiply-accumulate operator array and having a first bit width. The operation controller circuit is electrically connected to the multiply-accumulate operator array. The second bus is connected to the operation controller circuit and having a second bit width smaller than the first bit width.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Miyashita, Jun Deguchi
  • Patent number: 10318365
    Abstract: Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 11, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sheng Li, Norman P. Jouppi, Doe Hyun Yoon
  • Patent number: 10318168
    Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Glen E. Hush
  • Patent number: 10310858
    Abstract: Apparatus and a corresponding method for controlling a transition between use of first processing circuitry and second processing circuitry to execute program instructions are provided. Transition monitoring storage selects an entry for a load program instruction executed during the transition in dependence on a memory address from which a value is to be loaded and stores a program order timestamp for the load program instruction, unless a valid previously stored program order timestamp in the entry precedes the program order timestamp. Thus the oldest timestamp of an load instruction executed in the transition is held. At either the start or end (or both) of the transition the content of the transition monitoring storage is cleared.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: June 4, 2019
    Assignee: The Regents of the University of Michigan
    Inventors: Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Scott Mahlke, Jiecao Yu
  • Patent number: 10297329
    Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 21, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Yingda Dong, Masaaki Higashitani
  • Patent number: 10269408
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 23, 2019
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10242730
    Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 26, 2019
    Assignee: UNIQUIFY IP COMPANY, LLC
    Inventors: Mahesh Gopalan, David Wu, Venkat Iyer
  • Patent number: 10199080
    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah
  • Patent number: 10198376
    Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 5, 2019
    Assignee: Marvell World Trade Ltd.
    Inventor: Jerry Hongming Zheng
  • Patent number: 10163926
    Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 25, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10146359
    Abstract: A system is disclosed. The system can comprise dynamic drive circuitry configured to drive a plurality of electrodes on a touch screen. The system can also comprise a switching circuit configured to selectively couple the dynamic drive circuitry to one or more of the plurality of electrodes. The system can also comprise a display circuitry configured to selectively update a plurality of display pixels on the touch screen. The dynamic drive circuitry can be configured to set its output based on which of the plurality of electrodes are selectively coupled to the first drive circuitry and which of the display pixels are updated by the display circuitry.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 4, 2018
    Assignee: Apple Inc.
    Inventors: Howard Tang, Christoph H. Krah, Paolo Sacchetto, Chaohao Wang
  • Patent number: 10134751
    Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Akutsu, Ryota Katsumata
  • Patent number: 10115470
    Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabio Enrico Carlo Disegni, Giuseppe Castagna, Maurizio Francesco Perroni