Abstract: A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a level shifting circuit configured to generate an output voltage in a second voltage domain corresponding to an input signal in a first voltage domain. The level shifting circuit includes a thick-oxide transistor and a thin-oxide transistor. The semiconductor device includes a bias generating circuit operatively coupled to the level shifting circuit and configured to generate a bias voltage substantially higher than a voltage of the input signal, and provide the bias voltage to a gate of the thick-oxide transistor, causing the level shifting circuit to generate the output voltage.

Abstract: A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Abstract: A method for programming a memory device having a plurality of planes is provided. Program commands and addresses are received. Each of the addresses associated with one of the program commands. A first plane of the plurality of planes are determined according to a first address of the addresses. A page register of the first plane is reset. A second plane of the plurality of planes is determined according to a second address of the addresses. A page register of the second plane is reset.

Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.

Abstract: A computer-implemented method, according to one embodiment, includes: causing a multi-bit input to be split into two or more chunks, where each of the two or more chunks include at least one individual bit. Each of the two or more chunks are also converted into a respective pulse width modulated signal, and a partial result is generated in digital form for each of the respective pulse width modulated signals. Each of the partial results are scaled by a respective significance factor corresponding to each of the two or more chunks, and the scaled partial results are also accumulated.

Abstract: A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

Abstract: Upon determining that a first read operation on one memory cell of a plurality of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to first unselected word lines, and a first pass voltage is applied to second unselected word lines. The first unselected word lines include one or more word lines adjacent to a selected word line, and the second unselected word lines include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the first unselected word lines in the first read operation. The second pass voltage is higher than the first pass voltage.

Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

Abstract: Aspects of the disclosure provide a semiconductor device. For example, the semiconductor device can include a first deserializer, a second deserializer, and a write data converter coupled to the first deserializer and the second deserializer. The first deserializer can be configured to convert serial data to parallel data based on a set of write clock signals, thus the parallel data has a first timing alignment with regard to the set of write clock signals. The second deserializer can be configured to generate a mask pattern based on the set of write clock signals, thus the mask pattern has a second timing alignment with regard to the set of write clock signals. The write data converter can be configured to generate valid data based on the parallel data and the mask pattern.

Abstract: Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

Abstract: The implementation of the present disclosure provides a memory, an operation method thereof and a memory system. For example, the memory can include a first memory plane, a second memory plane, and a plane data bus connected to each of the first memory plane and the second memory plane. The plane data bus can be configured to receive input data. The first memory plane can be configured to store first data of the input data. The second memory plane can be configured to store second data of the input data. The second data can be configured to indicate whether the first data has been performed with an inversion operation prior to transmission.

Abstract: A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.

Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

Abstract: A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer.

Abstract: A method to compare between a first number and a second number includes the steps of storing the first number in a first row of an associative memory array, storing a two's complement representation of the second number in a second row of the associative memory array wherein bit i of the second number is stored in a same column of the associative memory array as bit i of the first number, concurrently performing a carry save operation on a plurality of columns of the associative memory array to create a sum and a carry, predicting a value of a carry out bit without adding the sum and the carry, and indicating that the first number is smaller than the second number if the value of the carry out bit is 1.

Abstract: An example apparatus includes a PIM capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.

Abstract: Provided is a step of forming, on a P-layer substrate 20, an N+ layer 21A to be connected to a source line SL, Si pillars 25a to 25d, N+ layers 23A to 23D to be connected to bit lines BL1 and BL2, HfO2 layers 30a and 32 surrounding lower and upper portions of the Si pillars 25a to 25d, a TiN layer 31a to be connected to a plate line PL, and TiN layers 33a and 33b to be connected to word lines WL1 and WL2. P layers 27a to 27d are formed so as to surround the Si pillars 25a to 25d and so as to be deposited on them to form a plurality of dynamic flash memory cells arranged in rows and columns.

Abstract: A field-effect transistor (FET) includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first and second regions. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.

Abstract: Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

Abstract: A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.

Abstract: A semiconductor integrated circuit includes a plurality of sense amplifier units including a first group of sense amplifier units and a second group of sense amplifier units, a first data bus, a second data bus, a transfer circuit between the first data bus and the second data bus, and a data latch connected to the second data bus and to the first data bus through the transfer circuit and the second data bus. Each sense amplifier unit is connected to one of the bit lines. The first data bus is connected to each of the sense amplifier units in the first group. The second data bus is connected to each of the sense amplifier units in the second group. The transfer circuit controls the transfer of data between the first data bus and the second data bus in both directions.

Abstract: A memory device includes pages containing memory cells arranged in an array on a substrate. In each memory cell, a voltage applied to a first gate conductor layer, second gate conductor layer, third gate conductor layer, first impurity layer, and second impurity layer is controlled to form a hole group by impact ionization inside a channel semiconductor layer, and a page write operation of holding the hole group and a page erase operation of removing the hole group are performed. The first impurity layer is connected to a source line, the second impurity layer to a bit line, the first gate conductor layer to a first plate line, the second gate conductor layer to a second plate line, and the third gate conductor layer to a word line. A page erase operation is performed without inputting a positive or negative bias pulse to the bit line and the source line.

Abstract: The present invention provides a semiconductor device comprising a storage chip and a temperature detection module for detecting a temperature of the storage chip. When the temperature detected by the temperature detection module reaches a set threshold, the storage chip is activated. The present invention utilizes the temperature detection module to detect the temperature of the storage chip so as to provide a reference for the activation and operation of the storage chip, avoiding the activation and operation of the storage chip under low temperatures, shortening write time, and improving the stability of the storage chip write; the temperature detection module has a simple circuit structure and is easy for implementation, with a small occupied area, exerting no influence on the active area of the storage chip.

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Abstract: An N+ layer 11a and N+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO2 layer 17b and that extends between the Si pillars 12c and 12d are formed.

Abstract: A memory device includes N memory planes (N is an integer greater than 1), M asynchronous multi-plane independent (AMPI) read units (M is an integer smaller than or equal to N), a first microcontroller unit (MCU), and a multiplexing circuit coupled to the N memory planes, the first MCU, and the M AMPI read units. Each AMPI read unit is configured to provide an AMPI read control signal for a respective memory plane to control an AMPI read operation on the respective memory plane. The first MCU is configured to provide a non-AMPI read control signal for each memory plane to control a non-AMPI read operation on each memory plane. The multiplexing circuit is configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of M AMPI read control signals to the respective memory plane from the corresponding AMPI read unit.

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.

Abstract: A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.

Abstract: A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

Abstract: A method of encoding input data. The method includes receiving a plurality of data bits of a bit stream. The method further includes forming words using the plurality of data bits to create a plurality of data packets including a first data packet. The method further includes encoding the words of the first data packet into coded words, partitioning the coded words into a plurality of blocks of M words each and integrating the coded words in each block in an interleaved order to generate a coded data packet for transmission through a communication channel.

Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell.

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

Abstract: A page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer of a memory cell and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer. a refresh operation is performed to return the voltage of the channel semiconductor layer of a selected word line to a first data retention voltage thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer of the memory cell in which a voltage of the channel semiconductor layer is set to the first data retention voltage using the page write operation. The refresh operation is performed, with a switch circuit kept in a nonconducting state, concurrently with a page read operation of reading page data of a first memory cell group belonging to a first page.

Abstract: A program method of a memory device having planes includes receiving a program command, obtaining an address associated with the program command, determining a first plane of the planes according to the address, and resetting a page register of the first plane without resetting one or more page registers of one or more remaining planes of the planes.

Abstract: A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

Abstract: A semiconductor system includes a semiconductor apparatus and a control device. The semiconductor apparatus performs a preset operation in response to a command signal. The control device controls a temperature adjustment operation so that first temperature information and second temperature information correspond to each other.

Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent to the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area. The memory controller is configured to control read operations of the memory device. The memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.

Abstract: A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: A memory system includes: nonvolatile memory devices and a memory controller confirming a programming time for each word line of each of the nonvolatile memory devices and calculating a target programming time on the basis of the programming time for each word line. Each of the nonvolatile memory devices receives the target programming time from the memory controller, and adjusts the programming time for each word line on the basis of the target programming time. When the adjustment of the programming time for each word line is completed, the memory controller confirms a variation width of a writing speed of the memory system for a predetermined time, and sets the target programming time as a final target programming time when the variation width of the writing speed is smaller than a reference value.