Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: A method for creating a physical unclonable function (PUF) bit for use with transistor circuitry includes performing a tilt test on a PUF cell of a transistor circuitry, comprising tilting the PUF cell at least once, and comparing a mismatch of a response of the PUF cell to a tilt threshold. A magnitude of the mismatch is determined. A mismatch magnitude below the tilt threshold is considered a first logic value” and a mismatch magnitude above the tilt threshold is considered a second logic value. The mismatch magnitude of the PUF cell is random. The absolute value of the mismatch magnitude is used as an entropy source to produce at least one PUF bit called a mirror PUF bit.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: Inductor device comprising a rectangular prismatic electro-insulating support (10) with three pairs of parallel outer faces (11) defining orthogonal axis (X, Y, Z), and defining eight corners; a rectangular prismatic magnetic core (20) supported by said electro-insulating support (10); and three conductor wire windings (DX, DY, DZ) wound around the three axis (X, Y, Z) surrounding the magnetic core (20); wherein the magnetic core (20) is a hollow magnetic core (20) composed by three pairs of sheets (21), each pair of sheets (21) being composed by two parallel sheets (21) facing each other perpendicular to one of said axis (X, Y, Z), and wherein each sheet (21) is made of a magnetic material, said sheet (21) being in contact and attached to the electro-insulating support (10) and being in contact with the surrounding orthogonal sheets (21).

Abstract: The present invention provides methods for inducing regression of tumors in human subjects, the methods utilize a modified mesogenic strain of Newcastle disease virus (NDV) with modified F protein cleavage site, which is non-pathogenic to poultry (lentogenic), but exhibits oncolytic properties. The disclosed methods provide safe, effective and reliable means to induce regression of a tumor in an individual in need thereof. These methods overcome the drawbacks of using pathogenic strains of viruses for human therapy.

Abstract: A self-contained radio-frequency device featuring multiple overlapping coupled coil inductors in a planar configuration with overlaps selected for desired coupling between different pairs of coils, wherein the electromagnetic energy of the coils arises substantially only from the coils themselves and affects only the coils themselves. Overlapping configurations provide a compact space-saving form-factor for such a device a variety of applications, including filters, baluns, transformers, matching networks, amplifier stages, distributed amplifiers, and frequency multipliers. Space-saving is achieved by overlapping the coils while controlling the mutual inductance. The planar arrangements are applicable to a variety of technologies, such as integrated circuits (IC, ASIC, RFIC), ceramic multilayer technologies such as low temperature co-fired ceramics (LTCC), and to printed circuit boards (PCB).

Abstract: A coil electronic component includes a body including metal powder particles having shape anisotropy and a coil unit disposed in the body and having an axis perpendicular with respect to a thickness direction of the body. The metal powder particles having shape anisotropy are arranged such that a plane-shaped surface thereof is parallel to a direction of flow of magnetic flux.

Abstract: Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, a method for providing electro-magnetic interference shielding for a radio-frequency module can include applying a metal-based covering over a portion of a lead-frame package, the package having a plurality of pins with at least one pin exposed from overmold compound and in contact with the metal-based covering. The method can also include mounting the lead-frame package on a substrate. The method can further include connecting the metal-based covering to a ground plane of the substrate.

Abstract: According to the present invention, a semiconductor device includes a first metal plate, a second metal plate provided above the first metal plate, a third metal plate provided above the second metal plate, a first semiconductor chip provided between the first metal plate and the second metal plate, a second semiconductor chip provided between the second metal plate and the third metal plate and a cooling member, wherein the first metal plate has a first cooling portion that is in contact with the cooling member, the second metal plate has a second cooling portion that is in contact with the cooling member, and the third metal plate has a third cooling portion that is in contact with the cooling member.

Abstract: An integrated electronic assembly including a first electronic component defining a receptacle and at least a second electronic component wherein at least a portion of the second electronic component is disposed in the receptacle of the first electronic component, and a method for conserving space in a circuit or on a printed circuit board by integrating a plurality of electronic components so that the plurality of electronic components collectively take up a smaller amount of space on a substrate than the plurality of electronic components would if the plurality of electronic components were not integrated.

Abstract: The present invention discloses an electronic package structure. The body has a top surface with a cavity thereon, the first conductive element is disposed in the cavity, and the second conductive element is disposed in the body. The first external electrode electrically connected to the first conductive element and the second external electrode electrically connected to the second conductive element are both disposed on the top surface of the body or a first surface formed by the top surface of the encapsulation compound and the exposed portions of the top surface of the body which are not covered by the encapsulation compound.

Abstract: A power-supply module includes at least one power-supply component, an inductor and a package. The inductor is disposed over the at least one power-supply components, and the at least a power-supply component and the inductor are disposed within the package. Besides, the power-supply module further comprises a printed circuit board, and the at least one power-supply component and the inductor are mounted to the printed circuit board. Moreover, the inductor comprises a plurality of leads that support the inductor over the at least one power-supply component.

Abstract: A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.

Abstract: A normally opaque waveguide interacting with a drop-filter cavity can be switched to a transparent state when the drop filter is also coupled to a dipole. This dipole induced transparency may be obtained even when the vacuum Rabi frequency of the dipole is much less than the cavity decay rate. The condition for transparency is a large Purcell factor. Dipole induced transparency can be used in quantum repeaters for long distance quantum communication.

Abstract: A magnetic signal transmission line includes a one-dimensional array of a plurality of single-magnetization domains each formed in a ferromagnetic body. The anisotropic energy of the single-magnetization domains is zero to 120% of the interactive energy acting between dipoles in adjacent single-magnetization domains. The single-magnetization domains are formed by sputtering iron onto a silicon substrate by using a mask.

Abstract: Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.

Abstract: A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

Abstract: A DRAM control circuit, having a second counter 12 which counts the number of times of generation of a refresh request signal generated by a first timer circuit 100, a set value register 13 which holds the maximum number of reservations for refreshing a DRAM 52, and a second comparator 14 which compares the count value of the counter 12 and a value held by the set value register 13, which cancels high-speed page mode and refreshes the DRAM 52 in a predetermined procedure only at a time when the second comparator 14 detects coincidence between the count value of the second counter 12 and a value held by the set value register 13. This configuration enables it to limit refreshing during high-speed page mode, while achieving a DRAM control circuit capable of operating in high-speed page mode more efficiently.

Abstract: A thin transparent epitaxial layer of a magnetizable material (e.g. gallium ferrite) is deposited on a substrate of a dielectric transparent material (e.g. gadolinium gallium garnet). A mask made from an oxidizable material (e.g. silicon) deposited on the epitaxial layer covers pixels defining rows and columns and exposes the other areas on the epitaxial layer. The epitaxial layer is then annealed at a suitable temperature (e.g. 500.degree. C.) for a suitable time (e.g. 10 minutes) to oxidize the silicon and reduce the Fe atoms in the pixel areas beneath the mask to Fe.sup.++ ions. This causes the pixel areas beneath the mask to be more easily magnetizable than the other areas in the epitaxial layer. The mask is then removed and a first insulating layer is deposited on the epitaxial layer. A first plurality of windings is then deposited on the first insulated layer in insulating relationship to one another.

Abstract: A non-volatile random access memory is described incorporating a plurality of memory cells, each memory cell having a Hall effect device including amorphous magnetic material and a switch for directing current through the flail effect device. An array of memory cells are interconnected by word lines, current lines, and bit lines. The invention overcomes the problem of a rugged non-volatile random access memory with long term reliability.

Abstract: A microprocessor has a register in which attributive data corresponding to a memory to be coupled to the microprocessor is written, and a control circuit which controls address signals to be supplied to the memory in accordance with the attributive data. The attributive data is composed of range data for discriminating ranges of address data supplied to an address bus, system data indicative of addressing systems of the memories corresponding to the respective address ranges, and bit number data indicative of numbers of address bits of the memories. Thus, in a case where the memory to be accessed is of an address multiplexing system as in a dynamic RAM, the address data of the address bus is divided into row address data and column address data, which are then supplied to the memory in time division.

Abstract: According to one embodiment of the present invention, a magnetic bubble memory module comprising a flexible printed circuits substrate (FPC3), on which a magnetic bubble memory chip (CHI) is mounted and electrically connected, with interconnecting patterns (9a) electrically connecting the chip (CHI) with external connecting leads, terminals or pins as well as bias coil winding (BIC2) for applying bias field to the chip (CHI), thereby reducing the number of components as well as fabricating steps because of the formation of the bias coil (BIC2) with the printed circuits substrate (FPC3).

Abstract: According to one embodiment of the present invention, a magnetic bubble memory module comprising a flexible printed circuits substrate (FPC3), on which a magnetic bubble memory chip (CHI) is mounted and electrically connected, with interconnecting patterns(9a) electrically connecting the chip (CHI) with external connecting leads, terminals or pins as well as bias coil winding (BIC2) for applying bias field to the chip (CHI), thereby reducing the number of components as well as fabricating steps because of the formation of the bias coil (BIC2) with the printed circuits substrate (FPC3).

Abstract: A package comprised of a plurality of truncated confocal, ellipsoidal layers of substantially equal length and having a common opening therethrough along a central axis for receiving a micromagnetic memory therein, typically a vertically stacked bubble memory.

Abstract: A magnetic bubble memory device comprising a chip assembly having a plurality of bubble memory chips superposed one above the other on a main printed wiring film. The lowermost chip is electrically connected to wiring patterns formed on the main printed wiring film. Each of the upper chip or chips is mounted on an auxiliary printed wiring film and electrically connected to the wiring patterns of the main printed wiring film through the auxiliary printed wiring film. The chip assembly is assembled with coils for generating a revolutional magnetic field disposed in a magnetic shield case in such a manner that the bubble memory chips are disposed inside of the coils and both ends of the main printed wiring film are disposed outside of the coils for outer connection.

Abstract: A sheet random access memory (SHRAM) is a truly random access, nonvolatile and transportable memory characterized by the cell density, size and power requirements of smaller dynamic memories but having the nonvolatile character of core memories or magnetic disks and tape and the rugged transportability of magnetic disk and tape. The SHRAM is characterized by a memory media comprising a two dimensional magnetic substrate and a fixed driving device for writing and reading into the substrate and a fixed sensing device for sensing the information at each cell location. In one embodiment the fixed sensing device is a sensing line in close proximity to a cell location. In a second embodiment, a fixed sensing device includes a Hall effect device which senses the magnetic configuration of the cell. In a third embodiment, the fixed sensing device includes an SCS thyristor in which the cathode gate is coupled to the magnetic configuration of the cell.

Abstract: A magnetic bubble memory device comprises a magnetic bubble memory chip, a unit for generating a bias field, a magnetic shield, and a unit for compensating the bias field, wherein the thermodependency of the bias field is compensated to approximate that of the operation characteristics of the memory chip over a wide temperature range, thereby providing a wide region in which operation is ensured.

Abstract: A magnetic bubble memory chip is disposed at a position surrounded by a rectangular annular core having two pairs of opposite sides wound by a pair of wires, respectively, and is covered by a case for confining revolving magnetic field, thereby providing a revolving magnetic field to said chip. A bubble memory includes a permament magnet used as a holding magnetic field source, lying at a predetermined angle to the chip. An inclination between the chip and the magnet is provided on the revolving-magnetic-field confining case to be inserted between the chip and the magnet by having the case changed in plate thickness.

Abstract: A magnetic bubble memory module containing a magnetic bubble memory device and its analog peripheral circuits mounted on a substrate, having outer input/output lead terminals, allowing the module to be mounted on a conventional printed circuit board instantaneously with other electronic elements. Lead terminals of the magnetic bubble memory device are protected by a protection means of an insulator such as plastic material, so that the magnetic bubble memory device is protected from the electrostatic discharge damage caused by the touching of a charged body such as human fingers. This results in high reliability and high production yield of the magnetic bubble memory apparatus.

Abstract: A magnetic bubble memory module having a rectangular core shaped like a picture frame providing windings on respective two pairs of opposite sides, at least one magnetic bubble memory chip disposed in an area surrounded by the core, a flexible substrate having a chip-loading section for loading the magnetic bubble memory chip thereon and having four corners for leading out lead wires connecting signal lines and driving lines of the chip. A revolving magnetic field-confining case accommodates the core, the chip and the flexible substrate and enables the lead wires of the flexible substrate at the corners of the chip-loading section to be drawn out therethrough.

Abstract: A bias magnet for a bubble memory device is comprised of a single material low permeability magnet contoured to enhance the magnetic field in the central area of the magnet and is adapted to be slightly larger than the bubble memory chip and in thermal contact therewith, the entire bubble memory chip and bias magnet structure to be surrounded by the rotating magnetic field drive coil structure.

Abstract: In a magnetic bubble memory unit comprising two pairs of windings confronting in parallel each other, a printed circuit board having a magnetic bubble memory chip thereon surrounded by the windings for providing the rotating magnetic field, and a conductive shield case for covering the magnetic bubble memory chip on the printed circuit board, slitlike openings are provided on the side face of the conductive shield case so as to present connection between the printed circuit board and an external device.

Abstract: A storage medium is disclosed which includes a plate having a plurality of taps arranged near the peripheral edges and on each surface thereof. Each tap is connected to a storage element. The taps are arranged near the peripheral edges of both sides of the plate in order to provide for an increased amount of storage of information in one plate. The plate may have interruptable lead lines between the taps and the storage elements to prevent erasure of information stored in the storage element. The plate is inserted into a holder fitting of a data processor for a cyclic-series read-out or recordation of digital information out of or into the storage elements on the plate. The storage elements located on each surface of the plate are used for storage of information. Labels may be used to identify the digital information stored on each surface of the plate.

Abstract: A magnetic bubble memory module comprises a shielding conductor case which encloses therein an annular rectangular parallelepiped core having windings and a magnetic bubble memory chip arranged in a space defined by the annular core. The central portion of the shielding conductor case is recessed so that it is brought near the bubble memory chip. The recess may be formed in one or each of the top and bottom surfaces of the shielding conductor case. A magnet plate is disposed in the recess of the shielding conductor case. The whole assembly is covered by a magnetic shielding case.

Abstract: A magnetic bubble memory device comprises a cassette and a body. The cassette has a bias magnetic field generator adapted to generate a bias magnetic field for sustaining magnetic bubbles within a bubble memory chip and is removed of coils adapted to generate a rotating magnetic field for propagation of the magnetic bubbles. The body has a rotating magnetic field generator. The cassette is mounted to or dismounted from the body. When the cassette is dismounted from the cassette, information stored in the chip is held by the bias magnetic field generator and when the cassette is mounted to the body, information is read from or written into the chip by the rotating magnetic field generator.

Abstract: The invention provides a method for producing a magnetic bias field in a magnetic bubble domain memory device. The method comprises coupling a magnetic bubble domain element with a permanent magnet. The permanent magnet is formed of a rare earth metal-containing alloy for use in the bubble domain memory device in respect of the reversible temperature coefficient of the magnet capable of being in compliance with the temperature coefficient of the bubble disappearance field of the memory device. The alloy characteristically contains nickel as an essential component so that the composition of the alloy is expressed by the formulaR(Co.sub.1-x-y Cu.sub.x Ni.sub.y).sub.z,in which R is a rare earth element, e.g. samarium or cerium, and s, y and z are each a positive number from 0.001 to 0.4, from 0.001 to 0.6 and from 4.0 to 9.0, respectively, with the proviso that x+y is smaller than 1.

Abstract: In a bubble memory package, a contoured, shaped magnet and filler plate combination is provided to shape the magnetic field in a uniform fashion to prevent the loss of magnetic flux density which normally tends to occur in the center of the magnet area of a planar, uniformly thick magnet.

Abstract: A nonmagnetic substrate is shown having a magnetic film that has been separated into a grid-like pattern of spaces to form quadrilateral magnetic elements. The spaces are filled with conductors arranged generally in X and Y directions. Each quadrilaterally shaped magnetic post element has a first and second region of low anisotropy material compared to the high anisotropy material of the magnetic film. The first regions of low anisotropy material are located in one corner of the quadrilaterally shaped post elements while the second regions are located in the corner opposite the first regions. Alternate columns of magnetic post elements have the first and second regions of low anisotropy material in opposite corners defined by a first diagonal, while the remaining columns have the low anisotropy material in corners defined by the second diagonal. This arrangement permits redundant switching of each magnetic post element.

Abstract: An improved conductive grid for a magneto-optic display is shown having individual magnetic and transparent post elements separated from one another by an orthogonal grid-like pattern. Conductors are deposited in each vertical separation and every other horizontal separation. A first region of low anisotropy material compared to the high anisotropy material of each post element is located in close proximity to the intersection of each vertical and horizontal conductor.

Abstract: An improved grid pattern is shown for increasing the density of magnetic post elements, within a magneto-optic display, for example, wherein the post elements are separated by a grid-like pattern of spaces which are filled with conductive elements arranged generally in the X and Y directions. Each quadrilaterally shaped post element is separated by a diagonal so that the first, third, fifth . . . etc. columns of post elements have diagonals running in one direction while the second, fourth, sixth . . . etc. columns have diagonals running in the opposite direction. A region of low anisotropy material is located in the corner of each triangularly shaped magnetic post element opposite the diagonal which forms the triangular element so as to be as close as possible to all extremes of the element.

Abstract: A bubble memory device comprises an insulating substrate holding a bubble memory chip secured thereto, X- and Y-direction driving coils wound on the insulating substrate for providing an in-plane rotating filed to the chip, a lead frame secured to edge portions of the insulating substrate, and magnet blocks disposed above and below the coils and including permanent magnets and field homogenizer plates for providing a bias field to the chip. The magnet blocks are molded together with the insulating substrate, coils and lead frame.

Abstract: The specification describes a magnetic bubble device which incorporates a Z coil for providing a test magnetic field in addition to the usually provided bias field. In order to reduce package size the Z coil comprises at least one printed coil 17 formed on a substrate 15. The substrate 15 may be a flexible substrate such as polyimide film which is provided as a flap on a chip connection substrate formed from the same film, the flap folding over to lie parallel with the chip connection substrate.The invention enables a Z coil to be provided within a package without unduly increasing package height and provides an additional advantage that the substrate which supports the Z coil may be used to protect the magnetic bubble device chip.

Abstract: Disclosed is an inter-connect board adapted to regularize the means of connecting chip elements, such as coils for a bubble memory, to various related I/O leads, without making this interconnection manually.

Abstract: A magnetic bubble memory device comprises a common package accommodating a lurality of pairs of memory chips. In each pair, the two chips have bubble propagation patterns in confronting relation which are mirror images of each other and additionally angularly offset by 180. Electrical connecting leads between the chips and the outside of the package are carried by insulating films located between the confronting chips. Coils located in the package create a bias magnetic field which is common to all chips. The coils for driving bubbles along the patterns are also common to all chips.

Abstract: In a field-accessed magnetic domain device package assembly, the magnetic domain device carrier or support, the circuit line or conductor carrier, and the magnetic bias field source are integrally and coactively provided by a common substrate member. The member is a planar permanent magnetic insulator ceramic and carries a bonded conductor or wiring pattern. The input/output (I/O) terminals of the domain device, also referred to in the art as a chip, are selectively bonded to the conductors of the pattern thereby providing mechanical support of the chip directly to the substrate in a superimposed relationship, input/output electrical connection to the chip, and mounting of the chip in close proximity to the bias field source, the flux of which passes through the superimposed mounted chips to a high permeability member at least part of which is disposed on the opposite side of the chip.

Abstract: In a non-volatile random access memory, a selected one of a plurality of magnetic cells arranged in an array on a major surface of a substrate is inductively switched between opposite remanent, i.e. permanent, states upon the simultaneous application of electrical pulses to a pair of conductors intersecting adjacent the selected cell, each of the electrical pulses having an amplitude less than, but the sum thereof being at least equal to, the amplitude required to inductively switch the remanent state of the selected cell.

Abstract: A credit card or security card data processing system employing portable ds including data processing means in each card adapted to be coupled to a data processing station having its own data processing means. In each card a part of the data processing means is formed by magnetic bubble elements at least one of which is a memory. The magnetic bubble elements are formed in a layer of magnetic material which has a propagation track thereon and which is positioned between a pair of magnet elements which establish a polarizing field perpendicular to the layer. The operating station includes orthogonal conductive coils arranged to set up a rotatable magnetic field which is applied to the magnetic layer causing the bubbles to be attracted by magnetic poles in the propagation track. A magnetoresistive member senses movement of the bubbles.

Abstract: A magnetic bubble memory module according to this invention is so constructed that heat developed by a rotating magnetic field-generating coil assembly is transmitted to linear ferrite plates of a bias magnetic field-generating device very efficiently.Accordingly, the temperature rise of a magnetic bubble chip can be suppressed conspicuously. As a result, the service temperature range of the magnetic bubble memory can be expanded.

Abstract: A portable credit or identity card or the like incorporates magnetic bubble elements. The bubble elements comprise a layer of magnetic material capable of containing magnetic bubbles and which is provided with a propagation track and a means for detecting the bubbles. Two flat permanent magnets arranged on either side of the magnetic layer generate a magnetic polarizing field perpendicular to the layer. The bubble element forms the memory which contains the identity code for the card.