Abstract: A garnet compound represented by a general formula (I): Ln3In2Ga3-XAlXO12 (I) (in the formula, Ln represents one or more metal elements selected from La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu; and X satisfies an expression 0?X<3).

Abstract: A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. An SCM smallest writable unit for writing data in the SCM is smaller than a secondary memory smallest writable unit for writing data in the secondary memory. An operation instruction is received from the processor to perform an operation on data stored in the secondary memory. The data is loaded from the secondary memory into the SCM for performance of the operation.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.

Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.

Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.

Abstract: A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

Abstract: A test mode control circuit detects designation of a test mode in accordance with a combination of external control signals and address signals, and activates an internal period setting circuit. Internal period setting circuit generates a clock signal having a prescribed period when activated, and applies it to a control circuit. In accordance with the test mode designating signal from test mode setting circuit and the clock signal from internal period setting circuit, control circuit causes an internal address generating circuit to generate an internal address signal successively in synchronization with the clock signal, so that a word line of a memory array is selected.

Abstract: The invention provides a structure that does not employ complicated and large-scale control circuits or control memory, minimizes the circuits for real time processing, and allows the use of refresh memory. The invention provides a test clock 8-1 comprising a data processing apparatus 1-1 provided for each electrode pin of the measured device 11, a memory 2-1 that carries out reading and writing of the test pattern data and the like, a first-in-first-out element 4-1 that executes queue processing of the data read out from the memory, a delay circuit 5-1 that delays the output signal of the first-in-first-out element, and a measured device driver 6-1 that inputs into the electrode pin the output signal of the delay circuit, and in which the data processing apparatus 1-1 of adjacent test blocks are connected into a loop via the input-output circuit 3-1.

Abstract: A non-physical movement component recording and reproducing device produces a pair of special waves with special waveforms that form a special stationary waveform. An electrically-conducting media contains three overlaid layers, a first layer contains the special stationary waveform, a middle layer allows signals to be recorded or be reproduced therein, and a third layer allows the signals to be connected. Two diodes are connected in reverse polarity to the third layer wherein one diode is used for recording and reproducing signals, while the other diode is used for erasing unused signals during the recording process. The bias voltage of the diodes is bigger than the peak value of the special waveform, but less than the maximum peak value of the special stationary waveform. The control unit changes at least one of the intermittence length and the phase of the special waves.

Abstract: A device for magnetic domains contains at least two, meander-shaped, current conductors for the purpose of driving parallel domains along these conductors by means of respective currents in them that alternate cyclically. At at least one end the current conductors are connected to a third current conductor. The latter is either also meander-shaped or it acts in the same way as a meander-shaped conductor with respect to the domains. Conversion is possible between parallel drive along the first and second conductors and serial drive along the third conductor owing to the fact that a loop of the latter also forms part of the other conductors.

Abstract: A magnetic device comprising at least one thin domain layer of a magnetizable material which has an easy axis of magnetization which is substantially normal to the surface of the layer and in which magnetic domains are propagated under the influence of a bipolar current, for example an alternating current, by a pattern of electrically conductive material with which the layer is provided. Elements are furthermore present which cause an asymmetry force and thus determine the direction in which the domains are propagated. The electrically conductive material and the elements are present in a single pattern which is constructed from at least a layer of magnetic material.

Abstract: Continuous film type, current-access bubble memories are designed for low power operation by including, along the current paths, areas of reduced width. The areas of reduced widths are characterized by relatively high current densities, which are preferred, for example, for expansion detected or operation, without an increase in power consumption.

Abstract: Magnetic bubble functional elements are implemented by aperture patterns in a single layer of electrically-conducting material. The operations of the elements are compatible with single-level conductor driven bubble memories described in A. H. Bobeck patent applications, Ser. Nos. 857,921 now U.S. Pat. No. 4,143,419 issued Mar. 6, 1979 and 856,925, filed Dec. 6, 1977, and in A. H. Bobeck-F. J. Ciak patent application, Ser. No. 899,578, filed Apr. 24, 1978 now abandoned.

Abstract: A current access bubble memory system includes a method and device for propagating and switching isolated bubbles within a plurality of orthogonal propagation channels. The device includes two orthogonal arrays of parallel current conductors oriented at 45.degree. angles to the two orthogonal bubble translation axes. The conductors in each array are regularly spaced a distance S apart from center to center. The first array of conductors are connected in parallel to a first current source and the second array of conductors are connected in parallel to a second current source. The propagation channels are defined by confining means to have a width d where d is the bubble diameter. The centerline of the channels are spaced a distance of about .sqroot.2 S/8 from the center of adjacent conductor intersections. Bubble translation occurs through sequential activation of the two bipolar current sources.

Abstract: A conductor-access magnetic bubble memory is realized with a single electrically-conductive film for the propagation of bubbles. The film is characterized by sequences of apertures in the film. The sequences define paths for bubble movement in response to controlled current pulses. Ion-implanted regions offset with respect to the aperture edges ensure unidirectional bubble movement along the paths.