Serial Read/write Patents (Class 365/221)
  • Patent number: 11211114
    Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 28, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, John E. Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright
  • Patent number: 11070383
    Abstract: A random code generator includes an address Y decoder, an address X decoder, a PUF entropy pool, a processing circuit and an entropy key storage circuit. The address Y decoder includes plural Y control lines. The address Y decoder selectively activates the plural Y control lines according to a first address Y signal. The address X decoder includes plural X control lines. The address X decoder selectively activates the plural X control lines according to a first address X signal. The PUF entropy pool generates an output data according to the activated Y control lines and the activated X control lines. When the random code generator is in a normal working state, the processing circuit processes the output data into a random code according to at least one entropy key from the entropy key storage circuit.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 20, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Meng-Yi Wu, Hsin-Ming Chen
  • Patent number: 11042507
    Abstract: Disclosed herein are systems and methods for deleting files. In one aspect, an exemplary method comprises, obtaining at least initial data about a file to be deleted in accordance with an instruction to remove the file from a data storage device, analyzing the file to be deleted and the data storage device to determine at least deletion parameters of the file to be deleted, performing a dynamic formation of a deletion algorithm, wherein the formation further includes the formation of a structure for writing and a determination of a location for the writing during the deletion of the file in accordance with the determined deletion parameters and rules of formation, and deleting the file by applying the deletion algorithm.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 22, 2021
    Assignee: AO Kaspersky Lab
    Inventor: Oleg V. Zaitsev
  • Patent number: 11010310
    Abstract: Apparatus, systems, computer readable storage mediums and/or methods may provide memory integrity by using unused physical address bits (or other metadata passed through cache) to manipulate cryptographic memory integrity values, allowing software memory allocation routines to control the assignment of pointers (e.g., implement one or more access control policies). Unused address bits (e.g., because of insufficient external memory) passed through cache, may encode key domain information in the address so that different key domain addresses alias to the same physical memory location. Accordingly, by mixing virtual memory mappings and cache line granularity aliasing, any page in memory may contain a different set of aliases at the cache line level and be non-deterministic to an adversary.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: David M. Durham, Siddhartha Chhabra, Michael E. Kounavis, Sergej Deutsch, Karanvir S. Grewal, Joseph F. Cihula, Saeedeh Komijani
  • Patent number: 11004531
    Abstract: A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Haeng Seon Chae
  • Patent number: 10832768
    Abstract: Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John F. Schreck, George B. Raad
  • Patent number: 10795592
    Abstract: An information handling system includes a processing unit that is coupled to a memory device by a communication channel. The processing unit includes a memory controller and is configured to host a basic input output system (BIOS). The memory device, which may include a dual in-line memory module (DIMM), stores serial presence detect (SPD) information. In an embodiment, the BIOS obtains the SPD information and parameters of the communication channel, such as channel impedance and channel length. In this embodiment, the BIOS uses a look-up table to determine an equalization of the communication channel based on the obtained SPD information and the obtained parameters of the communication channel, and utilizes the memory controller to set the equalization of the communication channel, such as by setting or controlling settings of transmission and reception components of the memory controller.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 6, 2020
    Assignee: Dell Products, L.P.
    Inventors: Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 10720204
    Abstract: According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Matthew Berzins
  • Patent number: 10649916
    Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 12, 2020
    Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.
    Inventors: Michael Peeters, Fabrice Marinet, Jean-Louis Modave
  • Patent number: 10534554
    Abstract: Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device. The apparatus and method use a random number to offset the read or write address in a memory cell. The random number is generated by determining the leakage current of memory cells. In another embodiment, random data can be written or read in parallel to thwart hackers from determining contents of data being written or read by monitoring sense amplifiers.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 14, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Patent number: 10466755
    Abstract: A power control device includes a memory device and a resistor coupled to the memory device. The memory device includes a first memory block storing a plurality of groups of performance parameters and a second memory block storing a power supply program. A resistance of the resistor corresponds to one of the groups of performance parameters. The power control device is configured to control power supply to an electronic device coupled to the power control device according to the power supply program and the one of the groups of performance parameters corresponding to the resistance of the resistor.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: November 5, 2019
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventor: Shijuan Qin
  • Patent number: 10452533
    Abstract: Systems and methods for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA) are described. One such method includes generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 22, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Kiran Kumar Gunnam
  • Patent number: 10395696
    Abstract: A double data rate memory includes a circuit board, a goldfinger connection interface, at least 16 first IC chips, at least 16 second IC chips, a first and a second read-only memory. The circuit board has a first surface, a second surface, a first region and a second region. The first IC chips are disposed on the first surface. The second IC chips are disposed on the second surface. The first read-only memory is connected with the first and the second IC chips disposed on the first region. The second read-only memory is connected with the first and the second IC chips disposed on the second region. 10 pins of the goldfinger connection interface are connected with the second read-only memory and the first and the second IC chips disposed on the second region to make them operate. At least 32 IC chips are effectively operated in single one memory.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 27, 2019
    Assignee: APACER TECHNOLOGY INC.
    Inventors: Yung-Chih Wu, Rui-Cheng Lin
  • Patent number: 10366742
    Abstract: Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 10353852
    Abstract: A memory system includes a semiconductor memory device including a plurality of memory blocks, including a first block storing data and a second block storing backup data, a plurality of pins, and a controller configured to output a control signal to the semiconductor memory in accordance with the command. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are available, the controller is configured to transmit the data in the first block to the outside of the memory system. When the controller receives from outside of the memory system, a read command for the data in the first block, and the data in the first block are not available, the controller is configured to transmit the backup data in the second block to the outside of the memory system.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kodera, Yoshio Furuyama
  • Patent number: 10268604
    Abstract: A resource arbiter in a system with multiple shared resources and multiple requestors may implement an adaptive resource management approach that takes advantage of time-varying requirements for granting access to at least some of the shared resources. For example, due to pipelining, signal timing issues, or a lack of information, more resources than are required to perform a task may need to be available for allocation to a requestor before its request for the needed resources is granted. The requestor may request only the resources it needs, relying on the arbiter to determine whether additional resources are required in order to grant the request. The arbiter may park a high priority requestor on idle resources, thus allowing requests for those resources by the high priority requestor to be granted on the first clock cycle of a request. Other requests may not be granted until at least a second clock cycle.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: April 23, 2019
    Assignee: Oracle International Corporation
    Inventor: John Deane Coddington
  • Patent number: 10236044
    Abstract: A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Norikazu Yoshida
  • Patent number: 10224098
    Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 5, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: HakJune Oh, Hong Beom Pyeon, Jin-Ki Kim
  • Patent number: 10095623
    Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 9, 2018
    Assignee: INTEL CORPORATION
    Inventors: Andrey Kluchnikov, Jayesh Iyer, Sergey Y. Shishlov, Boris A. Babayan
  • Patent number: 10025517
    Abstract: A memory system includes a memory apparatus including a write driver and a memory controller configured to control the memory apparatuses. The memory controller includes a command comparison circuit configured to compare word line addresses, bit line addresses, and pieces of write data of a first write command and a second write command and output a simultaneous write control signal having a first level when the bit line addresses and the pieces of write data are the same as each other and most significant bits (MSBs) of the word line addresses are different from each other and a processor configured to transfer a simultaneous write command for simultaneously operating the first write command and the second write command to the memory apparatus when the simultaneous write control signal having the first level is output from the command comparison circuit.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 17, 2018
    Assignee: SK hynix Inc.
    Inventor: Tae Ho Kim
  • Patent number: 9898267
    Abstract: System and method for performing correlation analysis. A program that includes multiple program structures and one or more data objects is stored. Each data object is shared by at least two of the program structures. For each program structure, decomposition effects on each of the data objects shared by the program structure resulting from each of a respective one or more optimizing transforms applied to the program structure are analyzed. One or more groups of correlated structures are determined based on the analyzing. Each group includes two or more program structures that share at least one data object, and at least one optimizing transform that is compatible with respect to the two or more program structures and the shared data object. For at least one group, the at least one optimizing transform is usable to transform the two or more program structures to meet a specified optimization objective.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 20, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Hojin Kee, Haoran Yi, Tai A. Ly, Newton G. Petersen, James M. Lewis, Dustyn K. Blasig, Adam T. Arnesen, Taylor L. Riche
  • Patent number: 9898023
    Abstract: According to one embodiment, there is provided a power management method for connecting a server to office machines to control electric power of the office machines. The office machines respectively store machine side power plans, which are operation states with respect to transition times. The server stores server side power plans of the office machines and subjects electric powers of the office machines to management control. The power management method includes comparing the server side power plan stored in the server and the machine side power plan stored in the office machines, comparing, when an operation state based on the server side power plan and an operation state based on the machine side power plan are different, power consumptions in the operation state based on the server side power plan and an operation state based on the machine side power plan, and changing an operation state of the office machine to be an operation state with small power consumption.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 20, 2018
    Assignees: TOSHIBA TEC KABUSHIKI KAISHA, KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya Inagi, Yoshikatsu Kamisuwa, Makoto Yasuhira, Shigenori Fujiwara
  • Patent number: 9754676
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Patent number: 9747230
    Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: August 29, 2017
    Assignee: Rambus Inc.
    Inventors: Minghui Han, Amir Amirkhany, Ravindranath Kollipara, Ralf Michael Schmitt
  • Patent number: 9680773
    Abstract: One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: June 13, 2017
    Assignee: Altera Corporation
    Inventors: Zun Yang Tan, Tat Mun Lui, Boon Jin Ang, Chiang Wei Lee, Richard Jin Guan Saw, Want Sent Khor
  • Patent number: 9659621
    Abstract: A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 23, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Young Seo, Chul Woo Park
  • Patent number: 9642286
    Abstract: A cooling controller of a cooling canister is configured to coordinate control of a set of fans coupled with the cooling canister with another set of fans coupled with an adjacent cooling canister. The cooling canister and the adjacent cooling canister include openings that are coupled together that permit air to flow between the cooling canister and the adjacent cooling canister. In some embodiments, the cooling control also coordinates control of a damper in at least one of the coupled openings of the coupled cooling canister and adjacent cooling canister.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 2, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Felipe Enrique Ortega Gutierrez, Christopher Strickland Beall, Darin Lee Frink
  • Patent number: 9633705
    Abstract: A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array from which a page is to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: April 25, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshihiro Ueda
  • Patent number: 9626529
    Abstract: A secure data storage device for preventing tampering with data stored thereon includes a two-dimensional memory array for storing data, the array includes a predetermined number of data words. Each data word includes a set of bits, and is associated with a single physical address in the memory array. A key storage area for storing a key of the data storage device is included in the device. The secure data storage device includes an address conversion unit configured to convert a logical address to a corresponding physical address which points to a location in the memory array. The device includes a bit mixing unit for mixing bit values of an input data word to obtain a mixed word value, such that the mixed word value is a rearrangement of the bit values of the input data word. The device is electrically connectable to a host.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 18, 2017
    Assignee: Winbond Electronics Corp.
    Inventors: Nir Tasher, Mark Luko, Uri Kaluzhny
  • Patent number: 9552867
    Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Soo Sohn, Uk-Song Kang, Kwang-Il Park, Chul-Woo Park, Hak-Soo Yu, Jae-Youn Youn
  • Patent number: 9520179
    Abstract: A read count circuit and a write count circuit, each for providing a count of data read from or written to, respectively, an asynchronous FIFO memory device. These circuits use read/write clock and read/write enable inputs, the selection of which depend on whether a read or write count is being provided. Essentially, the circuit comprises a shift register having a number of cascaded flip-flops, where the number of flip-flops is based on a ratio of one clock frequency to the other. An AND element at the output of each flip-flop AND's the output of the associated flip-flop with a read/write enable signal. A pulse generator at the output of each AND element synchronizes the outputs of the AND elements with the read/write clock. An adder then sums the outputs of the pulse generators. A counter increments with the adder output and decrements with a read/write enable signal, upon each read/write clock signal, thereby providing a read/write count output.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: December 13, 2016
    Assignee: SOUTHWEST RESEARCH INSTITUTE
    Inventor: Mark A. Johnson
  • Patent number: 9424230
    Abstract: In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: August 23, 2016
    Assignee: NEC CORPORATION
    Inventors: Tomoyoshi Kobori, Katsutoshi Seki
  • Patent number: 9405705
    Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventors: Michael Shachar, Barak Rotbard, Oren Golov, Uri Perlmutter, Dotan Sokolov, Julian Vlaiko, Yair Schwartz
  • Patent number: 9263108
    Abstract: The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 16, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaaki Iijima
  • Patent number: 9250811
    Abstract: Techniques for implementing a data queuing and/or caching scheme for optimizing data storage are described herein. Data write requests are received and processed by at least queuing the requests and/or associated data for recording upon one or more data storage devices. The order within the queue, as well as the order in which the queued requests are serviced, may, in some embodiments, be optimized. The stored data are verified by determining the position of a write pointer implemented by the one or more data storage devices relative to the contents and/or position of the queued data requests.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: February 2, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Kestutis Patiejunas
  • Patent number: 9159442
    Abstract: A serial memory may have memory arranged in a plurality of memory blocks, a serial interface for receiving a read instruction and associated memory address; and a controller configured to only store a plurality of most significant bits from each memory block which are accessed in parallel before an entire address has been received through the serial interface. The controller is further configured to stream out one of the plurality of most significant bits upon full reception of the memory address while retrieving the remaining bits from memory using the entire address and stream out the remaining bits after the most significant bits have been streamed out.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 13, 2015
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Silvia Czeides
  • Patent number: 9087017
    Abstract: Memory circuitry, a data processing apparatus and a method of storing data are disclosed. The memory circuitry comprises: a memory for storing the data; and control circuitry for controlling power consumption of the memory by controlling a rate of access to the memory such that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein the control circuitry is configured to determine a priority of an access request to the memory and to maintain the average access delay at or above the predetermined value by delaying at least some accesses from access requests having a lower priority for longer than at least some accesses from access requests having a higher priority.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 21, 2015
    Assignee: ARM Limited
    Inventors: Timothy Charles Mace, Ashley John Crawford
  • Patent number: 9036416
    Abstract: Data, normally read using a page-by page read process, can be recovered from memory cells connected to a broken word line by performing a sequential read process. To determine whether a word line is broken, both a page-by page read process and a sequential read process are performed. The results of both read processes are compared. If the number of mismatches between the two read processes is greater than a threshold, it is concluded that there is a broken word line.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 19, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Nima Mokhlesi, Lanlan Gu, Ashish Pal Singh Ghai, Deepak Raghu
  • Publication number: 20150117130
    Abstract: Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Inventors: Michael JONES, David ESKELDSON, Darrin ALBERS
  • Patent number: 9019776
    Abstract: A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Chih-Huei Hu, Chia-Wei Chang, Der-Min Yuan
  • Patent number: 9015405
    Abstract: A method of storing data into a memory array converts an input string into a first binary array with (m?1) rows and (n?1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: April 21, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi, Pascal Vontobel
  • Patent number: 9001607
    Abstract: A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Adrian E. Ong
  • Patent number: 8988950
    Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Oh, Ho-Yong Song, Seong-Jin Jang
  • Patent number: 8953396
    Abstract: A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin, and data is transmitted over data pins in response to commands and addresses received on the serial command and address pin.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Patent number: 8934309
    Abstract: In aspects of the invention, an auxiliary memory circuit includes a shift register wherein a plurality of flip-flops are cascade-connected and a plurality of inversion circuits that invert and output outputs of each D flip-flop. A main memory circuit includes a switch, which acts in accordance with a signal from the auxiliary memory circuit, and an EPROM connected in series to the switch and driven by a writing voltage. A variable resistance circuit includes a switch, which acts in accordance with a signal from the auxiliary memory circuit, and a resistor connected in series to the switch. With aspects of the invention, it is possible for terminals of the writing voltage and a writing voltage to be commonized. Also, it is possible to provide a low-cost semiconductor physical quantity sensor device that can carry out electrical trimming with the voltage when writing into the EPROM kept constant.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: January 13, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuhiro Matsunami, Mutsuo Nishikawa
  • Patent number: 8897090
    Abstract: A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: November 25, 2014
    Assignee: Conversant Intellectual Property Management Incorporated
    Inventor: HakJune Oh
  • Patent number: 8898375
    Abstract: A memory controlling method, a memory controller and a memory storage apparatus are provided. The method includes identifying whether a transmission mode between the memory storage apparatus and a host system belongs to a first transmission mode or a second transmission mode and grouping memory dies of the memory storage apparatus into a plurality of memory die groups. The method also includes applying a first erasing mode to erase data stored in the memory dies when the transmission mode belongs to the first transmission mode and applying a second erasing mode to erase the data stored in the memory dies when the transmission mode belongs to the second transmission mode, wherein at least a part of the memory die groups are enabled simultaneously in the first erasing mode and any two of the memory die groups are not enabled simultaneously in the second erasing mode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 25, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hung Hou, Hoe-Mang Mark
  • Patent number: 8880782
    Abstract: A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 4, 2014
    Assignee: Hewlett Packard Development Company, L. P.
    Inventors: Erik Ordentlich, Ron M. Roth, Gadiel Seroussi
  • Patent number: 8867573
    Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchronizer, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: October 21, 2014
    Assignee: Nokia Corporation
    Inventors: Pasi Kolinummi, Mika Koikkalainen, Juhani Vehvilainen
  • Patent number: 8772869
    Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono