Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

Abstract: An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.

Abstract: A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.

Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: Space, power and performance are improved by a memory device having multiple modes of operation for elastic data transfer. The memory device is comprised of first and second elastic store memory blocks, each containing 16 (18 bit) memory locations, and a write/read decoder. The first memory block receives write data from a first (18 bit) input data bus, and outputs two memory locations (36 bits) of read data onto a four memory location (72 bit) output data bus. The second memory block receives write data from multiplexed first and second (18 bit) input data buses and outputs two memory locations of read data onto the four memory location (72 bit) output data bus. The write address decoder receives a 5 bit write address, wherein the write address decoder will, as a function of a mode signal for effectively changing the address space for writing data, direct write data received at the data inputs of the first and second elastic store blocks to the correct memory locations.

Abstract: A self-addressing FIFO for transferring data between clock domains while avoiding the necessity of using a clock tree stores address information as bits of a data word and uses these bits to generate the next address, thus eliminating loading the clock signal with a separate counter. While data must be valid at the clock edges and the clock period still needs to be controlled, clock skew is not an issue and therefore general purpose routing may be used for the input or output clock. Users may input or output data to external devices without ever using on-board global clock resources.

Abstract: An input/output (I/O) circuit of a memory device performs I/O and stores data for write-backs. The write-back data may be used for destructive read operations. The I/O circuit may also be configured to perform data balancing, write-verifies and built-in self test (BIST).

Abstract: Memory cells of a storage device are addressed in n-bit word(s). Each of the n-bit word memory cells are partitioned into k (k≧2) groups of n/k bits. The memory cells are sequentially selected in n/k bits. Data of the selected n/k bit memory cells are read by n/k sense amplifiers and serially output from the storage device as readout data. The storage device requires much less chip area for n/k sense amplifiers and reduced peak currents in a read operation.

Abstract: First-in first-out (FIFO) memory devices include a plurality of memory devices that are configured to support any combination of dual data rate (DDR) or single data rate (SDR) write modes that operate in-sync with a write clock signal (WCLK) and DDR or SDR read modes that operate in-sync with a read clock signal (RCLK). These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.

Abstract: An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.

Abstract: A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD, /WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.

Abstract: A multi-port memory with an array that is implemented without the additional signal lines and transistors usually found in prior multi-port memories. The multi-port memory includes a port control circuit that senses accesses from different ports and sequences the accesses to the array. The multi-port memory also includes an input/output structure for holding data associated with the accesses as they are sequenced.

Abstract: An apparatus and method is disclosed for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.

Abstract: A nonvolatile semiconductor memory device comprises an address buffer, a column address register, a selection circuit, a data input/output circuit, and a controller. The controller controls the column address changes of the memory device during the read/write operation. When external addresses are applied to a first input/output pins while data is transferred from a second input/output pins to an internal register or is transferred from the internal register to the second input/output pins through the data input/output circuit, the control circuit stores the external addresses in the column address register as a column address. A page size of the nonvolatile semiconductor memory device having such a column address change function can be increased irrespective of a memory system.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

Abstract: The invention relates to a dual-port DRAM memory location having a capacitor and two transfer gates whose load paths are connected in series. The series connection is arranged between two data transmission lines. This arrangement serves to provide a dual-port memory location which independent of one another, can be read or written by two data processing units. The decisive advantage of the inventive memory locations in a DRAM memory architecture is the size-optimized design. The possibility of providing a memory architecture with substantially reduce space requirements. The inventive memory location is very immune to noise due to its design, due to the small number of switching elements and short length of conductor paths. The small number of transistors and short length of conductor paths also permits to reduce the time required for accessing the data. The invention also relates to a DRAM semiconductor memory having dual-port memory locations.

Abstract: A command storing control circuit stores in storing units a plurality of commands supplied the latest of the supplied commands so as to execute the memory operation. A command reading control circuit reads the commands stored in a command storing area during a test mode. If incorrect data are written into a semiconductor memory, causing the system mounting the semiconductor memory to become inoperable, the cause of the trouble can be efficiently determined by utilizing the commands stored in the command storing area. As a result, the efficiency of development of the system can be improved, for example, and the cost of developing the system can be reduced. Moreover, the quality of the system can be also improved.

Abstract: Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

Abstract: A memory control apparatus for controlling the operation of a memory array in a serial memory such as a serial EEPROM employs a command control section for registering in a shift register the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit for such clock signal control.

Abstract: An apparatus comprising a flag generation circuit configured to generate an empty flag signal in response to (i) a read clock, (ii) a write clock and (iii) a look ahead bitwise comparison configured to detect when a write count signal minus a read count signal is equal to 1.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: First and second data is transferred in parallel through a first signal transmission path, amplified by first and second relay amplification circuits, and transmitted via a second signal transmission path to first and second output registers, and an output circuit is provided for serially outputting the first and second data held by the first and second output registers, respectively, on the basis of address information. With respect to data to be outputted first of the first and second data, output timing of the data to be outputted later is delayed, data to be outputted first is made to correspond to the first output register, data to be outputted later is made to correspond to the second output register, and the transfer rate of the second signal transmission path corresponding to the first output register is set higher than that of the second signal transmission path corresponding to the second output register.

Abstract: A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.

Abstract: The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.

Abstract: A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

Abstract: A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.

Abstract: A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality of clock pulse waves, each having substantially equal period and each being out of phase with respect to other clock pulse waves; an output including at least one output terminal corresponding to one of the clock pulse waves; and a zero phase circuit configured to sequentially couple the plurality of clock pulse waves to the corresponding output terminals.

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract: Outside core circuit, link circuits are concentratedly arranged in an LT link portion. The LT link information sent from the LT link portion is serially transferred to transfer control circuit. Transfer control portion converts the serially transferred link information to parallel information, and transfers the parallel information to latch circuits arranged in the core circuit and corresponding to circuits requiring the LT link information. An influence on an interconnection layout by laser trimmable link elements is eliminated.

Abstract: An apparatus comprising a memory array having a first port and a one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.

Abstract: An address input is received earlier than data input, and a result of decoding of a column address at the time of writing and results of substitution determination for a redundancy memory column are held in a latch circuit corresponding to each bank. When the data arrives at the bank, the data is immediately written to each bank, utilizing the results of address processing. Operation frequency of the chip is not limited by the conventionally experienced wasteful wait time for the data in the process of writing, and efficient data input/output is possible.

Abstract: A semiconductor memory circuit capable of conducting an efficient test by using a memory tester is provided. A semiconductor memory circuit includes a memory cell array; a plurality of main data lines for conducting reading and writing every plural bits in parallel; and a shift register for converting parallel data read from memory cell array to the main data lines into serial data and supplying the converted data to data input/output terminals, and for converting write data supplied from the data input/output terminals in series into parallel data and supplying the converted data to the main data lines, and at least a portion of a plurality of the main data lines are arranged so as to be across each other between the memory cell array and the shift register. As a result, data compression is enabled during a test by a memory tester.

Abstract: A FIFO memory device includes a write address generating circuit generating a write address in response to a write clock signal and a read address generating circuit generating a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating circuit compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.

Abstract: The present invention discloses a method for data input/output for memory which minimizes losses of data interruption when switching between reading and writing. A method for data input/output comprises the steps of: holding predetermined data from memory array 12 upon m-th (m is integer) read command; outputting the predetermined data to common I/O 30 and holding new data from memory array 12 upon (m+1)-th read command; holding predetermined data from common I/O 30 upon n-th (n is integer) write command; and storing the predetermined data in memory array 12 and holding new data from common I/O 30 upon (n+1)-th write command.

Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Abstract: A state machine comprising a first input receiving a first write clock, a second input receiving a first read clock, a third input receiving a first programmable Almost Empty look-ahead signal, a fourth input receiving a second write clock, a fifth input receiving a second read clock, and a sixth input receiving a second programmable Almost Empty look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Empty output flag that is at a first logic state when a FIFO is Almost Empty and is at a second logic state when the FIFO is Not Almost Empty.

Abstract: There is provided a serial access memory and a data write/read method applicable thereto. The serial access memory is able to function as the prior art FIFO type serial access memory and as the prior art line access type serial access memory, too. This serial access memory 101 is provided with a memory cell array 11, a write register group 17, a read register group 20, and a write/read register group 32. The write/read register group 32 is made up of write/read registers WRreg-1 to WRreg-m. These write/read registers are prepared by the same number as that of memory cells (m pieces) connected with each of word lines WL1 to WLn, in the same way as the write registers Wreg-1 to Wreg-m forming the write register group 17 and the read registers Rreg-1 to Rreg-m forming the read register group 20.

Abstract: A core memory containing an array of core cell memory elements are accessed using a cascode barrel reading arrangement and method. The cascode barrel read uses a plurality of cascodes and a plurality of sense amplifiers to read core cells that have consecutive array addresses. The core cells are connected with the plurality of cascodes via a core cell selector. After data from a core cell from a particular cascode has been read and the next consecutive core cell is being read from a different cascode, the original cascode looks ahead to the core cell with the next highest address. Consequently, when the sense amplifier is ready to sense the original cascode again, the data from the core cell with the next highest address has already been loaded and is immediately ready to be read.

Abstract: The present invention concerns a circuit comprising a memory, a flag/array address circuit and a flag logic circuit. The memory may be configured to read and write data in response to one or more memory address signals. The flag/array address circuit may be configured to present one or more flag address signals in response to (i) one or more enable signals and (ii) a control signal. The flag logic circuit may be configured to present one or more logic flags in response to the one or more flag address signals.

Abstract: M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being “empty” and “full”, respectively.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.