Abstract: A control circuit controls a column decoder and a parity column decoder such that parity data is input/output to a memory cell array at a timing different from that of input/output of data corresponding to the parity data to/from the memory cell array. Therefore, a terminal for parity data input/output is not necessary, and a memory device can be adapted to an ECC function without increasing a memory bus width.

Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.

Abstract: A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.

Abstract: Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, the cell string formed with floating gate memory cell transistors such that their control gates each are respectively connected to a plurality of word lines, and its drain-source channels are series connected to each other between a string select transistor and a ground select transistor. The memory device also includes a multiple-speed mode option part for generating a multiple-speed option signal, and an addressing circuit for selecting a page size and block size of the memory cell array different from one another in response to a state of the multiple-speed option signal.

Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: A semiconductor memory having burst mode operation includes a memory cell array, a sense amplifier circuit determining data of memory cells, a latch circuit having first and second latch groups and latching data of a sense amplifier, an enable circuit provided with an chip enable signal and controlling readout operation the semiconductor. The enable circuit instructs the circuit for readout operation to activate until the latch circuit latches data even if the chip enable signal indicates stopping the readout operation of semiconductor memory to output data of memory cells correctly.

Abstract: A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.

Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.

Abstract: A semiconductor memory device includes a plurality of internal banks of different sizes. The internal banks are suitable for and correspond to the memory needs of a plurality of master devices. Master devices are assigned banks having sizes matched to the needs of the master devices so that inclusion of multiple buffers in a bank can be avoided. A master device that requires a small buffer is assigned a memory bank having a small size, and an external master that requires a large amount of memory is assigned a large bank. Reduction of the average number of master devices sharing each bank improves performance by reducing the number of page misses caused when different master interleave accesses of different pages in the same bank.

Abstract: A state machine comprising a first input receiving a first write clock, a second input receiving a first read clock, a third input receiving a first programmable Almost Empty look-ahead signal, a fourth input receiving a second write clock, a fifth input receiving a second read clock, and a sixth input receiving a second programmable Almost Empty look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Empty output flag that is at a first logic state when a FIFO is Almost Empty and is at a second logic state when the FIFO is Not Almost Empty.

Abstract: A memory system on a semiconductor body is tested by testing components formed on the semiconductor body. A programmable clock signal generator receives an external clock signal and selectively generates an output clock signal having a frequency at a predetermined multiple of the received external clock signal. A counter receives the output clock signal from the clock signal generator and generates output signals having a cyclical binary count up to the predetermined multiple of the received external clock signal. Memory locations in a programmable look-up memory store separate commands for testing the memory system. The programmable look-up memory receives each of selective remotely generated binary encoded address signals to access a separate predetermined look-up memory section, and the binary output signals from the counter for sequentially accessing separate memory locations within the separate predetermined look-up memory section.

Abstract: A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of the memory circuit, and then writing the data to a memory of the memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write command to the memory for writing the data to the memory without further pre-charging and activating the designative memory page.

Abstract: Method of storing and retrieving information by exposing cells of a storage medium to a first beam of light having a first set of properties affecting the optical properties of said storage medium, and by exposing a plurality of individual cells, forming a page of information, of said storage medium to a second beam of light having a second set of properties. A third light beam from said storage medium forms an image of said page on a detecting means. The detected light image is converted into electric data signals, each bit of said data signals corresponding to a cell of said storage medium. The first beam of light is generated by a first light source and there is provided an electrooptical means having an electric input for receiving data and being arranged for modulating said first light beam in dependance of said data.

Abstract: A method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory is provided. While memory accessing agents, such a microprocessors, typically have a fixed memory access size (e.g., number of bits or bytes exchanged with a memory device in a single operation), DDR memory provides twice the memory burst capability of SDRAM. A method and apparatus is provided to allow memory access agents to exchange data with both SDRAM and DDR memory. Smaller groups of data may be combined or larger groups of data may be separated to allow compatibility. Buffering is provided to accommodate proper timing. Both SDRAM and DDR memory may be used simultaneously.

Abstract: A memory system including a memory controller that operates in conformity with fast page mode (FPM) memory devices and an extended-data output (EDO) memory device configured to operate with the FPM memory controller by having an output enable input receiving a column address strobe (CAS) signal from the memory controller. The EDO memory device terminates its data cycle upon negation of the CAS signal, so that it operates in a similar manner as an FPM memory device. This prevents data corruption and bus cycle contention. The memory system includes a memory board coupled through a memory board connector, which receives the CAS signal from the memory controller. The memory board includes one or more module connectors, each having an output enable contact receiving the CAS signal. The EDO memory device is mounted on a memory module and includes an output enable input pin which receives the CAS signal when the memory module is plugged into the memory board.

Abstract: The present invention stores and retrieves digital information by altering the phase transmission characteristics of a multiple layer phase recording by modulating the carrier frequency and the carrier frequency angle. These layers are organized into several regions, called page areas, which contain an array of juxtaposed encoded digital information data. Each page area may have several pages of digital information; each recorded with a different carrier frequency and carrier angle. The data layers are stacked together and aligned such that the page areas and encoded digital information on them are also aligned with each other into books. When one of these books is selectively illuminated by a controllable light source, a lenslet aligned with that book projects the transformed images of the data pages within that book, through a shutter array, and a reimaging lens onto a photosensor detector array.

Abstract: A burst page access unit for a semiconductor memory device which has a plurality of memory cell arrays for storing bit data therein. The burst page access unit comprises a row decoder for decoding a row address signal from an address input line in response to a row address strobe signal to select a desired one of the memory cell arrays, an internal address counter for incrementing a column address signal from the address input line by one in response to a column address strobe signal to generate an internal column address signal, and a column decoding circuit for decoding the internal column address signal from the internal address counter to select a desired one of memory cells in the memory cell array selected by the row decoder. According to the present invention, the burst page access unit can enhance the successive data access speed to increase the bandwidth of the semiconductor memory device.

Abstract: SDRAM 1000 outputs data, in a 2-bit prefetch operation, by simultaneously selecting two columns in memory cell array banks A0 and A1 in accordance with column select signals YE0-YEk and YO0-YOk issued from Y-address operation circuit 68. In a full page mode, data are output from all columns crossing rows alternately selected in memory cell array banks A0 and A1 in accordance with an internal address signal issued from a Y-address counter circuit 82.

Abstract: A burst page access unit for a semiconductor memory device which has a plurality of memory cell arrays for storing bit data therein. The burst page access unit comprises a row decoder for decoding a row address signal from an address input line in response to a row address strobe signal to select a desired on of the memory cell arrays, an internal address counter for incrementing a column address signal from the address input line by one in response to a column address strobe signal to generate an internal column address signal, and a column decoding circuit for decoding the internal column address signal from the internal address counter to select a desired one of memory cells in the memory cell array selected by the row decoder. According to the present invention, the burst page access unit can enhance the successive data access speed to increase the bandwidth of the semiconductor memory device.

Abstract: A page-mode semiconductor memory device comprises a matrix of memory cells arranged in rows and columns, each row forming a memory page of the memory device and comprising at least one group of memory cells, memory page selection means for selecting a row of the matrix, and a plurality of sensing circuits each one associated with a respective column of the matrix. The memory cells are multiple-level memory cells which can be programmed in a plurality of c=2b(b>1) programming states to store b information bits, and the sensing circuits are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells, at each step one of said b information bits being determined, said at least one group of memory cells of a row forming a number b of memory words of a memory page.

Abstract: A memory device having normal and extended data out (EDO). modes includes an array of memory cells arranged in plurality of rows and columns, first and second data latches which store data, a column address input which receives a column address signal, and a column address strobe input which receives a column address strobe signal. First latch control means, responsive to said column address input and to the column address strobe input, electrically couples one memory cell in the array of memory cells and the first data latch when a column address signal is asserted at the column address input and electrically decouples the one memory cell and the first data latch when a column address strobe signal is asserted at the column address strobe input, thereby latching data present in the one memory cell prior to assertion of the column address strobe signal in the first data latch.

Abstract: An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.

Abstract: A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.

Abstract: The present invention relates to a control circuit and method for controlling a data line switching circuit in a semiconductor memory device having a memory cell array, a row decoder for designating a row of a memory cell, a column decoder for designating a column thereof, a bit line sense amplifier which senses a signal of a bit line and amplifies it, and a column selection gate circuit which comprises a plurality of MOS transistors and selectively applies output signals of the bit line sense amplifier to input/output lines via a MOS transistor gated by an output signal of the column decoder among the plurality of MOS transistors.

Abstract: An apparatus for accessing an extended data output dynamic random access memory (EDO DRAM) is disclosed. A conventional fast page mode (FPM) DRAM is converted by the present invention to conform to an EDO DRAM. The present invention comprises a conventional FPM DRAM, a read-cycle generating circuit for generating a signal that defines a read cycle, a flip-flop for latching data signals from the FPM DRAM, an output control circuit for generating a control signal to control a data switch that will pass the latched data signals. The data signals come directly from the FPM DRAM and the latched data signals come from the data switch are combined to form extended data signals coupled to a system data bus.

Abstract: An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

Abstract: A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.

Abstract: An optical memory is disclosed in which data is stored in an optical data layer capable of selectively altering light such as by changeable transmissivity, reflectivity, polarization, and/or phase. The data is illuminated by controllable light sources and an array of multi-surface imaging lenslets project the image onto a common array of light sensors. Data is organized into a plurality of regions or patches (called pages) and by selective illumination of each data page, one of the lenslets images the selected data page onto the light sensors. Light in the data image pattern strikes different ones of the arrayed light sensors, thereby outputting a pattern of binary bits in the form of electrical data signals.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: A random access memory (RAM) having an array of memory cells the signal lines to which are activatable by corresponding current sources. The memory is divided into "pages", and control pulses are produced to turn on the current sources involved in activating the signal lines to any page of memory cells being accessed and to turn off the remainder. The control pulses are directed through a pipelined pair of registers, and a look-ahead logic circuit examines the two pipelined control pulses identified as the "present" and "next" pulses. This logic circuitry serves to turn on the current sources for the page of memory to be accessed during the next clock time, and to maintain in an on state the current sources for the page of memory presently being accessed.

Abstract: An optical memory stores data in an optical data layer capable of selecting altering light such as by changeable transmissivity. Data is organized into a plurality of regions or patches (called pages) in which each page contains a field of data spots storing binary data as the presence or absence of a hole. The data is illuminated by controllable light sources and an array of single element diffractive imaging lenslets, one for each data page, projects the image onto a common array of light sensors. By selective illumination of each data page, one of the single element lenslets images the selected data page of holes onto the light sensors. By selecting a hole size and using a certain range of restricted acceptance angle grooves on the diffractive elements, the data image is optimized for a single diffractive element lens.

Abstract: A page in, burst-out FIFO buffer that stores only words in a single page and transfers the words to a DRAM utilizing a page mode transfer to increase data throughput and decrease latency offloading DRAM bandwidth.

Abstract: An optical memory is disclosed in which data is stored in an optical data layer capable of selectively altering light such as by changeable transmissivity or polarization. The data is illuminated by controllable light sources and an array of multi-surface imaging lenslets project the image onto a common array of light sensors. Data is organized into a plurality of regions or patches (called pages) in which each page contains a field of data spots that encode multiple states or levels of data by the amount of transmissivity or polarization of that spot. By selective illumination of each data page, one of the lenslets images the selected data page onto the light sensors. Light in the data image pattern strikes different ones of the arrayed light sensors, thereby outputting the multiple levels per spot in the form of electrical data signals that are A/D converted to digital.

Abstract: A MOS memory device operating at high speed which is so constructed as to hold the sense amplifier activating signals SAP and SAN at high potential and at low potential, respectively, even after the completion of a memory access, and keep the sense amplifier 30a in activated state to hold read data from memory cells. This memory device includes a block decoder which designates mutually different cell array blocks synchronized with a row selection signal RAS and a column selection signal CAS so that it is possible at the time of input of the column selection signal CAS to execute write/read operation in page mode that extends over the cell array blocks.

Abstract: An optical cache memory architecture is utilized that has the advantages of fast access time, high bandwidth and high density. The optical cache memory architecture stores data holographically with greatly reduced crosstalk and distortions. The memory architecture uses the beam fanning effect present within a high gain photorefractive crystal to eliminate the so-called Bragg degeneracy.

Abstract: A semiconductor memory device, in which based on a write and non-write states of a memory transistor, a signal corresponding to a page mode and a normal mode is generated, and a switch circuit activates all sense amplifiers corresponding to memory array blocks and transfers data read out of the memory array blocks to the sense amplifiers in the page mode and also activates one of the sense amplifiers and successively transfers the data read out of the memory cell array blocks to the one activated sense amplifier according to an address signal in the normal mode. A plurality of sense amplifiers are activated in the page mode and the minimum number of the sense amplifiers is activated in the normal mode to eliminate a waste of a consumption power.

Abstract: A latch circuit is provided between a column switch connected to the input/output sides for selecting data lines and a tristate buffer connected to the write side of a memory array, or between the column switch and a sense amplifier connected to the readout side of the memory array. The latch circuit has a capacity corresponding to a plurality of data contents in the tristate buffer or the sense amplifier. While data set in a portion of the latch circuit is being output, the next data can be set in another portion of the latch circuit.

Abstract: An improved method of programming EEPROM cells in a memory array, wherein a cell page can be programmed and erased without disturbing other cell pages in the array, and further, an individual cell can be reprogrammed without disturbing other cells in the array. The user can selectively erase and program cells in the array by controlling the operating conditions of the word lines, bit lines, and Vss lines coupled to those cells according to the method of the present invention.

Abstract: A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.

Abstract: A plurality of reflective diffusing holographic memory elements (16) is positioned on a memory plate (14). An array (24) of detectors (22) faces at least one of the memory elements. A laser (26) illuminates the selected memory element and the data stored therein is reflected onto the array for reading. A new memory element may be illuminated or may be brought into interrogation position.

Abstract: A holographic memory read-out system in which multiple pages of information are angularly multiplexed onto a recording medium, either planar or volume. For read-out of the hologram, a selected one of a plurality of surface-emitting semiconductor lasers arranged in a two-dimensional array is activated. The coherent output beam is passed through a collimating lens which produces a coherent plane-wave having a direction dependent upon which laser in the array produced the output beam. The plane-wave uniformly irradiates the recording medium to thereby diffract a selected image at a set angle to an imaging apparatus.

Abstract: A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.

Abstract: A semiconductor memory is comprised of four arrays (10), (12), (14) and (16) that have the memory elements therein arranged in accordance with pixel positions on a display. The memory arrays have associated shift registers (34), (36), (38) and (40) which have data loaded in parallel and output in a serial format to the display. Each of the shift registers can be connected in a circulating fashion or a shift register of adjacent arrays can be cascaded. Switches (56), (58), (60) and (62) are provided for configuring the shift registers for either circulation or cascading of data. In the circulating mode, the input and output of the shift registers is multiplexed on one pin whereas in the cascaded configuration, one array receives a dedicated serial input and the other array in the cascaded pair outputs the serial output on a dedicated pin.

Abstract: The same basic ROM circuit may be used to provide memories of increased capacity for pre-existing systems having different fixed numbers of address inputs. The appropriate page configuration is selected to accommodate the number of address inputs in the system. The system is adapted to generate a page address signal having the required number of bits on the data bus. The selected page configuration is obtained by mask programming the address decoder and input buffer circuits. The page address signal from the data bus is routed through the data transfer buffers and stored in a RAM for use in conjunction with the row and column address inputs.

Abstract: An eraseable solid state optical memory has an array of selectively energizeable photoemitters which are imaged by suitable imaging means onto a data mask to optically address data stored thereon. To that end, the data mask is an eraseable optical recording medium, such as a tellurium suboxide or other chalcogenide material. A data writer is provided for programming, erasing and re-programming the data mask in situ while self-aligning the imaging means with the programmed data mask. The data mask may be erased and/or re-programmed in whole or part, thereby extending the utility of these memories to the storage of data that is subject to change.

Abstract: Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

Abstract: An improved memory device operable at a high speed and with a small power consumption is disclosed. The memory device comprises memory cells arrayed in rows and columns, a row decoder for selecting the rows, a column decoder for selecting columns, a shift register arranged in parallel with the column decoder, first control means for operatively enabling the shift register and second control means for suppressing the operation of the column decoder when the shift register is enabled.

Abstract: A ratioless semiconductor read only memory circuit comprises a plurality of insulated gate field-effect transistors being arranged in the form of a matrix consisting of columns and columns, bit lines of the rows of the transistors connected in parallel a sampling transistor connected in series to each of the rows of the transistors and each of the bit lines, and a row selection circuit connected to the respective bit lines for selecting one of the bit lines. The transistors of said array corresponding to individual bits are of the enhancement type or the depletion type depending on desired logic content.