Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.

Abstract: A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a first voltage generation unit generating a first power supply voltage supplied to the first selection unit; a second voltage generation unit generating a second power supply voltage supplied to the second selection unit, when a start-up signal is active; a switch short-circuiting first and second power supply lines, when a short-circuit signal is active; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal and the start-up signal after completion of access operations.

Abstract: A semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, includes: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.

Abstract: A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base address and linear or interleaved burst sequence controls. For every I/O, eight bits of data are presented to a 9-to-1 multiplexer. The first of eight bits in the burst sequence is the access time-limiting bit and is preselected by the burst base addresses of the 9-to-1 multiplexer. Subsequent bits in the burst sequence have extra half-cycles to be output, and use look-aside 8-to-1 multiplexers controlled by a burst counter with timings synchronized to the burst data clock timings.

Abstract: Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation.

Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: To efficiently access pixel data stored in memory in the X direction and Y direction when carrying out error correction processing. In a data output section 10, a pixel block consisting the desired 2×2 pixel data W1-W4 is selected by inputting a address, and pixel data continuously aligned in an arbitrary direction, that is, in the X direction or Y direction, are output inputting output pixel selection signals V1 and V2. Specifically, two pixels W1, W2, or W3, W4, which are continuously aligned in the X direction, are selected when signals V1 and V2=0 and V1=0 and V2=1, and two arbitrary pixels W1, W3 or W2, W4, which are continuously aligned in the Y direction, are selected when signal V1=1 and V2=0 and V1 and V2=1.

Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.

Abstract: Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. Decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals.

Abstract: A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes.

Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

Abstract: A FIFO memory eliminates the delay associated with selecting memory locations during a read and write operation and prevents data intended to be saved from changing during the write operation. The FIFO memory includes a shift register having a plurality of memory locations, data input and data output terminals coupled to the memory, a first memory location coupled to the data output terminal that is immediately output enabled in response to a read operation, and a single pointer arrangement coupled to the memory locations for selectively saving data contents in successive memory locations coincidentally with the occurrence of successive write operations.

Abstract: A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in the row direction of the input section and by reading out in the column direction of the input section, write section for selectively writing data into a first pair of memory cells of said corner turn memory array; and readout section for simultaneously reading data from a second pair of memory cells which are different from the first pair of memory cells.

Abstract: A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynamic random access memory array provides additional buffering capability. Input and output FIFOs are connected to the data and address bussed of the digital signal processor. The control of the digital signal processor is via a host processor connected to the digital signal processor by a serial communication link.

Abstract: A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed.

Abstract: In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read data into serial data for output, circuits are provided that allow selective reversing of the order of parallel conversion on the serial input data and of serial conversion on the parallel data read from the memory array. This serial memory is also provided with a memory controller to reverse the ascending or descending order of the access address for the memory array in the read and write operations.

Abstract: The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and erase operations. The invention reduces the effective programming time of a single cell and of an entire row of cells that program using hot electrons.According to another aspect of the invention the asymmetry in programming of split gate EEPROM is used to reverse bias the cell so a plurality of digital bits that were stored by D/A converter in the cell according to a curve are read out by an A/D converter with large voltage difference between logical states.

Abstract: A semiconductor memory device comprises a memory cell array in which cascade-gate dynamic memory cells are arranged in a matrix and which contains word lines connected in common to the memory cells in the same row and bit lines connected in common to the memory cells in the same column, and serial access control means which serially accesses a plurality of memory cells in a given column of the memory cell array, reads a plurality of bits of information in time-sequence from one of the memory cells storing information, and then sequentially rewrites the bits of information into a different memory cell unused for storing valid data, in the same column where the memory cell exists.

Abstract: A delay apparatus comprises one or a plurality of shift registers, a plurality of signal accumulating capacitors which are mutually coupled by transfer transistors, a plurality of write switches each of which is arranged between an input terminal and either one of the capacitors and which are controlled by outputs of the shift registers, and a plurality of read switches which are arranged between the plurality of capacitors and an output terminal and are controlled by the outputs of the shift registers, wherein the signal charges accumulated in the one capacitor are capacitively divided into other capacitors through the transfer transistors for transferring the signal charges.

Abstract: A three dimensional memory enabling both pixel and bit slice data to be stored and retrieved through different ports. A memory circuit (30) is divided into a lower memory block (32a) and an upper memory block (32b). Each memory block is organized into 256 rows .times.16 groups (pixel planes) of eight columns (bit planes). Eight bits of pixel data are stored at a selected row and pixel plane of the upper or lower memory block, and sixteen bits of pixel data are stored at a selected row and bit plane of the upper or lower memory block. Address bits determine the location of pixel data and bit slice data. A bit plane port is used to access data in the bit slice format and another port is used to access data in the pixel format. Bit slice data input through the bit plane port and stored in the memory circuit can be read as pixel data through the pixel port, and vice versa.

Abstract: An apparatus for storing digital data includes a clock pulse source and plural serial shift register stages storing data bits. Digital data signals, each having plural databits, are coupled to and shifted in the stages in synchronization with the clock pulses. Data stored in the memory stages stages are held in a non-erasable memory unit provided for each stage while an emergency causing a failure of a power supply of the shift register occurs.

Abstract: A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means for erasing through the gate of the flash EEPROM cell.

Abstract: Two dimensional charge coupled device (CCD) memories are coupled to acoustic charge transport devices (ACT) which act as input and/or output multiplexers for the memories. In a preferred embodiment of the invention, the input to a NXM memory is in the form of an optical image projected on the CCD device and the output stage of each column of the memory is provided to one of N FET switches. A 1-D ACT device has multiple taps each connected to the gate of one of the FET switches and as an impulse signal propagates along the ACT channel, the FET switches are successively triggered causing the column outputs to be provided to a summing device to generate a serial output.In an alternative embodiment forming a corner-turn memory, an ACT tapped delay line has a number of equally spaced electrode taps equal to the number of columns of a CCD corner-turn array and each tap is connected to an electrical switch which in turn is connected to an input cell of a bordering row of the array.

Abstract: Data to be sent to a frame buffer memory keeping output data in a bit map form is subdivided into square blocks. The words arranged in the row direction are rotated in a column direction by a bit each time the row address is increased. The rotation amount is attained by adding the row and column addresses associated with the square block.

Abstract: A circuit configuration for the identification of integrated semiconductor circuitries includes n programmable elements. A common line is connected to the programmable elements. An n-stage serial-parallel shift register has a data input, n parallel outputs, and a clock input for controlling a shift function of the serial-parallel shift register as a function of a clock signal to be applied to the clock input. Transistors each have a drain connected to a respective one of the programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of the serial-parallel shift register. Instead of n-stage serial-parallel shift register, it is also possible to use a clocked n-stage oscillator, such as a ring oscillator, or an n-stage counter, such as ring counter.

Abstract: An SPS charge coupled device memory is described which is useful for storing video pictures. The memory avoids accumulation of charge below the de-interlacing electrodes controlling the transfer of data to the series output register by using two different procedures for generating the de-interlacing clocks for the odd channels and for the even channels of the parallel section. These procedures are carried out sequentially with an adjustable difference in time.

Abstract: The present invention constitutes a memory system comprising a multiple number of individual memory units (40-47) for storing digital data from a variable number of data input streams and for efficiently using the memory capacities of the memory units in the system by controlling the routing of data between the memory units. Each one of the memory units includes a set of input multiplexers (100-103), a set of shift/shadow registers (110-113) and a memory component (120) having a RAM memory array (121). The components of the memory units are implemented on a single integrated circuit chip. The input multiplexers allow alternate data streams to be selected for input to the shift/shadow registers. The shift/shadow registers are operative for enabling data to be transferred to and from the memory array at speeds slower than the rate at which these data are received by the system.

Abstract: The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.

Abstract: A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respectively, which are controlled by a basic clock signal (g1) and further signals. Thus FIFO memory makes it possible to pass an input data stream arriving at an input data rate (g2) through the FIFO memory in such a way that the output data stream appears at the output (da) at an output data rate (g3) momentarily different from the input data rate (g2). On a time average, however, the two data rates are equal, so that data can be written into and read from the FIFO memory simultaneously at different rates.

Abstract: A database is stored in a mass memory. For this purpose, it is first divided into main cells and then into base cells according to a predetermined regular division pattern. Each base cell is then checked to see whether its data content is sufficient to occupy substantially completely a storage parcel having a predetermined capacity. If this is the case, the base cell is thus accommodated in a storage parcel; if this is not the case, adjacent base cells are grouped until a storage parcel is occupied substantially completely. The operation of addressing a storage parcel is effected by the use of a main cell table in which address pointers are stored, each of which points to a base cell table. In the base cell table, an index is given for each base cell and this index indicates in which storage parcel the relevant base cell is accommodated.

Abstract: An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations.

Abstract: A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To this end there are provided two address registers (4, 5) and a logic tree structure (8) which consists of modules. At each level of the tree structure a module receives a part of the information from the two address registers in order to determine, possibly co-controlled by information received from a higher level of the tree, whether one or both limit addresses are situated within the address range covered by the module and, if the answer is negative, to determine whether all addresses of this address range must be activated or remain deactivated.

Abstract: A memory access control apparatus has a plurality of request reception sections, respectively connected to a plurality of units for supplying requests, for receiving a block read request from the corresponding units, and dividing the block read request into a plurality of read requests and outputting the divided read requests, a selector for selecting one of outputs from the request reception sections and outputting the selected output, a request processing section for processing the request output from the selector and outputting reply data to a corresponding unit, and a main memory connected to the request processing section.

Abstract: A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock signals have individual clocking phases and are sequentially generated such that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof.

Abstract: A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.

Abstract: A dynamic memory device comprises a dynamic memory circuit, an input buffer circuit for temporarily storing data each time it is received from a source external to the device; an output buffer circuit for temporarily storing data each time it is read out from the dynamic memory circuit and for outputting the stored data in a unit of a predetermined number of words each time a request for reading is made; and a control circuit for controlling the input and output buffer circuits so that reading and writing operations can be performed independently of a refreshing operation.

Abstract: An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.

Abstract: A memory device which employs multilevel memory cells has a basic arrangement in which a write device writes multilevel information corresponding to binary data of plural bits in the memory cells and a readout device outputs binary data of plural bits representing the multilevel information read out of the memory cells. The memory device includes a multilevel detector for detecting the information of the memory cells at one time and reference level generator for generating reference levels therefor, thereby permitting the reduction of the bit area of each memory cell and increased speed during the operation of the memory device.

Abstract: A matrix data transposer is disclosed which allows data stored in a matrix format to be transposed at high speed using parallel processing techniques. In one embodiment, the data are passed through a time delay means which delays each bit of a word a different amount. The time delayed data are then passed through a distribution means which operates to shift the data in position from rows to columns. The shifted data are then passed through a second time delay means to restore the data to its original timing, the end result being the data transposed so that what was originally one row of the data matrix is now one column of the matrix. A second embodiment achieves the same result using only one time delay means and two distribution means.

Abstract: A memory array associated with a display can be accessed in either one of two substantially orthogonal directions. The memory array is structured so that it may be accessed, such as for reading or writing, in either the horizontal or vertical direction. Pel position representations in the array are arranged so that vertically sequential pel positions in a given column are represented by data in sequential memory modules rather than by data in the same memory module. Likewise, horizontally sequential pels in a given row are represented by data in sequential modules rather than in the same module. The memory array is comprised of a plurality of separate memory modules and is structured so that both x and y directional accessing into and out of the array is accomplished on a bit addressable x,y field. This enables any bit string in the array to be addressed and to be read from or written into the array in either the x or y direction.

Abstract: A semiconductor memory device having a read-modify-write (RMW) configuration suitable for modifying a large number of data with high speed and a simple circuit. The RMW configuration includes a data input and output circuit (11, 14, 16) for simultaneously storing or reading a plurality of data into or from the memory cells, a data output circuit (10, 12, 13) for serially reading a plurality of data from the memory cells, and data modification circuits (15) for successively receiving the plurality of data from the data output circuit, modifying the received data if necessary and transmitting the modified data to the data input and output circuit.

Abstract: In a video computer system and the like having a bit-mapped RAM component including a shift register, an improved method is provided for rapidly clearing the RAM in order to prepare the system to receive new input data. More particularly, a preselected number of predetermined data bits corresponding to the number of columns in the RAM is serially shifted into the register. Thereafter, the contents of the shift register are progressively shifted into each of the rows in the RAM until all rows are filled.

Abstract: A memory system includes a data storage matrix having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a sequence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defective physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix. Redundancy control logic response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the redundant column between the data bits read from the data storage matrix according to its logical column address.

Abstract: A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided.

Abstract: The system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses and selectively actuable input and output gate connections to those buses to provide for selective shifting of bits between units to change the bit array.

Abstract: In a dual page memory system sharable by first and second processors, a plurality of storage elements are assigned to first and second pages accessible by the respective processor. An address decoder decodes addresses provided by either of the processors, and provides a selection signal corresponding to a predetermined storage element in each of the pages. A page selector couples the selection signal to the storage element in the page assigned to that processor. An access controller provides access to that processor to the storage element to which the selection is coupled. An assignment controller is provided to selectively swap corresponding storage elements between the pages.

Abstract: A semiconductor memory device including a random access memory cell array, a series/parallel data transfer circuit, transfer gate, an active pull-up circuit, and an active pull-down circuit. The transfer gate is inserted between bit lines of the random access memory cell array and the series/parallel data transfer circuit to carry out parallel transfer of data. Output data of the series/parallel data transfer circuit is simultaneously written in a group of memory cells of selected work lines by turning on the transfer gate and selection of a word line. When data of each output of steps of the series/parallel data transfer circuit is logic "1", the active pull-up circuit charges up a selected bit line of the random access memory cell array. When data of each output of steps of the series/parallel data transfer circuit is logic "0", the active pull-down circuit discharges a selected bit line of the random access memory cell array.

Abstract: An improved semiconductor memory device for serial scan applications is presented. The semiconductor memory device as presented includes a main memory means combined with an on-board means for implementing a shift register function. The shift register function of the present invention is implemented by utilizing a secondary memory means in conjunction with parallel loadable, multiple-bit address counters.

Abstract: In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).

Abstract: The invention relates to a charge-coupled SPS memory comprising a series input register, a parallel section and a series output register. In order to increase the retention time leakage current drain regions are provided beside the memory. Since the charge collected as a result of leakage current is largest during the transport through the outermost registers of the parallel section, only the sides of the parallel section are screened by the said draining regions which preferably consist of dummy registers. FIG. 1.