Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

Abstract: An operating method of a semiconductor device may comprise monitoring error handling information corresponding to an address of a semiconductor memory device, setting a refresh period for the address considering the error handling information and requesting a refresh request for the address.

Abstract: A new address transition detection (ATD) circuit for use on an address bus having a plurality of address signal lines comprises a first circuit for each address signal line and a second circuit. The first circuit has a first input, a second input and an output. The first input is coupled to an address signal line. The second input is coupled to an ATD signal. The first circuit saves the current level of the first input in response to an ATD pulse on the ATD signal and generates a change signal at its output by comparing the current level and the saved level of the first input. The second circuit has an input and an output. The second circuit receives on its input the change signal from the first circuit. In response, the second circuit generates the ATD pulse on the ATD signal at its output.

Abstract: In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.

Abstract: Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.

Abstract: A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator.

Abstract: Multi-channel semiconductor integrated circuit devices are provided including a plurality of memory devices that are independently accessible, each of the plurality of memory devices including at least one power generation unit and a control unit for controlling an operation of the at least one power generation unit, a detection unit for detecting an operation state of the plurality of memory devices, and a common control unit for commonly controlling an operation of the at least one power generation unit of the plurality of memory devices, according to the operation state of the plurality of memory devices detected by the detection unit. The control unit of each of the plurality of memory devices controls the operation of the at least one power generation unit of a corresponding one of the plurality of memory devices.

Abstract: A semiconductor memory includes a plurality of memory cells, a refresh request generator circuit for generating a refresh request signal to refresh the plurality of memory cells based on a number of clock cycles elapsed in a clock signal, a clock cycle detector circuit for detecting the clock cycle of the clock signal, and a refresh controller circuit for controlling a number of memory cells to refresh from among the plurality of memory cells, in accordance with the detected clock cycle.

Abstract: A dynamic memory module is fitted with a tamper detection circuit and a memory clear circuit responsive to a detected tampering signal for clearing the memory. A power retention circuit powers the memory, the tamper detection circuit, and the clearing circuit in the event that the main power fails. Failure of the main power or a System Reset may also initiate memory clearing.

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract: A nonvolatile memory device includes a plurality of memory blocks, a plurality of erasure detection units provided at the plurality of memory blocks, respectively, and configured to each detect erasure of the respective memory blocks, and a control unit configured to determine that a memory block is a bad memory block when a number of erasure operations performed on the memory block as detected by the respective erasure detection unit is greater than a reference value.

Abstract: A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal.

Abstract: An information processing apparatus includes a memory configured such that structural data areas holding therein structural data, each being constituted by a plurality of pieces of element data, are allocated to a plurality of memory banks, an address area detecting unit configured to detect whether an address value used to access the memory is included in a specific address area including an address used to access the plurality of pieces of element data and an address converting unit configured to convert the address value to an address value for the structural data area in the case that it has been detected that the address value is included in the specific address area.

Abstract: An information recording apparatus has a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled along the fine particles. Summary information may be recorded for plural information recording parts.

Abstract: Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.

Abstract: A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal.

Abstract: A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal.

Abstract: A detector circuit for detecting an external manipulation of an electrical circuit. The detector circuit includes a digital circuit which is sensitive to at least one of the effects of ionizing radiation or fluctuations of a supply voltage, and the output state of the digital circuit is indicative of an attack.

Abstract: Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock synchronization circuit and tracking and recording the control voltage are disclosed. For example, a clock synchronization controller provides an initial control voltage to the voltage controlled delay during initialization of the synchronization circuit until a phase dependent control voltage stabilizes. The stable phase dependent control voltage is substituted for the initial control voltage. Following stabilization of the phase dependent control voltage, a phase detector of the clock synchronization circuit is activated. A recovery control voltage is provided by the clock synchronization controller to the voltage controlled delay during recovery of the clock synchronization from a power-saving mode until the phase dependent control voltage stabilizes.

Abstract: Non-volatile (NV) semiconductor memories and methods of operating the same to reduce or eliminate a need for an external capacitance are provided. In one embodiment, the memory includes a memory cell comprising a random access memory (RAM) portion and a NV memory portion, and the method comprises steps of: (i) initially erasing the NV memory portion; and (ii) on detecting a drop in power supplied to the memory, programming the NV memory portion with data from the RAM portion while powering the memory from a capacitor. On restoration of power data is recalled from the NV memory portion into the RAM portion, and the NV memory portion erased. Preferably, the capacitor is integrally formed on a single substrate with the NV memory portion and RAM portion. More preferably, the capacitor comprises intrinsic capacitance between elements of the memory formed on the substrate. Other embodiments are also disclosed.

Abstract: A power-on management circuit for a memory device is provided. The power-on management circuit comprises a first external power-on voltage detector, a second external power-on voltage detector, a delay unit, a logic circuit, an internal power-on voltage detector, a voltage control circuit, a plurality of first electric pumps and a second electric pump. The first external power-on voltage detector has a first voltage threshold, receives a first external voltage, and generates a first control signal when the first external voltage is higher than the first voltage threshold. The second external power-on voltage detector has a second voltage threshold, receives a second external voltage, and generates a second control signal when the second external voltage is higher than the second voltage threshold.

Abstract: A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

Abstract: A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

Abstract: An information recording apparatus comprises a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled along the fine particles.

Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.

Abstract: A word line boost circuit includes a first pump circuit, a first transistor, a voltage detection circuit and a second pump circuit. The first pump circuit provides a gate boosted signal according to an address transfer detection (ATD) signal. The first transistor has a control terminal for receiving the gate boosted signal and a second terminal coupled to a target word line. The voltage detection circuit is for detecting a voltage level of the gate boosted signal and accordingly outputting a detection signal. The second pump circuit is for outputting a boost signal to a first terminal of the first transistor according to a voltage level of the detection signal. The boost signal boosts the target word line via the turned-on first transistor.

Abstract: Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

Abstract: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Abstract: A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write and the test circuit sets data to this selected bit line. The other bit line is used for data read, and the written data is set to this bit line in the normal operation. Whether each memory core is not defective is judged by EOR which confirms data set to the bit line and data set to the inverted bit line are mutually inverted each other. A test method is realized which can test a defect of each memory core of a semiconductor memory such as SRAM in a short time.

Abstract: Devices allow a system using a memory array, or the memory itself, to more efficiently control refresh intervals. This reduces standby current and the overhead associated with refresh operations. The device includes a variable analog refresh signal generation circuit that initiates a refresh operation on one or more memory cells of a memory array. The circuit integrates a refresh timer element with an event signal generator such that a refresh interval as defined by the refresh timer element is changed when events are detected that may change the data retention time of one or more memory cells. One or more of the circuits is placed to monitor an entire memory array, different sub-arrays, or different portions of different sub-arrays. This allows additional refresh operations to be closely tied to actual events, thus increasing overall efficiency.

Abstract: A semiconductor memory device controlling an output voltage level of a high voltage generator in response to a variation of temperature has a high voltage generator that provides a high voltage higher than a power source voltage through an output terminal, generates a temperature detection signal obtained by sensing a variation of a diode current based on a temperature variation, and adjusts a voltage level of the output terminal in response to the temperature detection signal. The device is able to automatically control an output voltage or current of the high voltage generator.

Abstract: A semiconductor memory device can stably supply a high voltage even if not only the PVT (Process, Voltage, and Temperature) fluctuations but also the level fluctuations of the external voltage are caused by the variation of the external environments. The driving force of a standby VPP generating unit and a plurality of active VPP generating units are changed according to the PVT fluctuations.

Abstract: A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature.

Abstract: The data output circuit for a semiconductor memory apparatus includes a plurality of pads in which a range of use is determined such that the respective pads are used exclusively in each of at least two kinds of unit data output modes or used commonly in all of the at least two kinds of unit data output modes, a plurality of data lines that transmit data from a plurality of memory banks to the outside of the memory banks, and a data output control unit that outputs data from a data line among the plurality of data lines, according to at least one control signal, to a signal line corresponding to a pad used in a currently set unit data output mode among the plurality of pads.

Abstract: A memory capable of suppressing increase in circuit size, reduction in a period for an original access and increase in power consumption while suppressing an imprint can be obtained. The memory includes a first count detection circuit for detecting an access frequency with respect to memory cells, a second count detection circuit for detecting an access frequency of each of memory cell blocks and a third count detection circuit detecting a no-access frequency resulting in an imprint.

Abstract: A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write and the test circuit sets data to this selected bit line. The other bit line is used for data read, and the written data is set to this bit line in the normal operation. Whether each memory core is not defective is judged by EOR which confirms data set to the bit line and data set to the inverted bit line are mutually inverted each other. A test method is realized which can test a defect of each memory core of a semiconductor memory such as SRAM in a short time.

Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.

Abstract: An access time adjusting circuit is used in a non-volatile memory to obtain an optimized access time in operation. The circuit includes an access time detecting unit, used to detect a performance status of the non-volatile memory under an operation clock and output the performance status. An access time controlling unit is used to generate at least one adjusting operation clock. Each the adjusting operation clock serves as the operation clock for the non-volatile memory. In addition, the non-volatile memory, the access time controlling unit, and the access time detecting unit are connected to form a detection and adjustment loop, so that an optimized operation clock is determined after checking the at least one adjusting operation clock.

Abstract: A circuit for setting one of a plurality of organization forms of an integrated circuit includes a detector circuit connected to an external connection of the integrated circuit. The external connection in at least one of the organization forms can be used for external communication of the integrated circuit. A signal can be impressed into a signal path connected to the external connection by the detector circuit. As a consequence, an output signal is generated at an output of the detector circuit. A control circuit sets one of the organization forms and receives the output signal of the detector circuit. One of the organization forms is set by the control circuit depending on the state of the output signal of the detector circuit. A module with a detector circuit can identify that organization form of the organization forms in which it is operated in the application.

Abstract: A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: In a data processor which comprises a semiconductor memory device, a potential on a bit line of the semiconductor memory device is monitored at the end of a precharge, required for the semiconductor memory device, to detect an anomalous frequency of a clock applied from the outside. The anomalous frequency is detected by determining whether or not the potential on the bit line has reached a predetermined potential. When the potential on the bit line has not reached a predetermined potential, the operation of a CPU is reset.

Abstract: An apparatus and method for dynamically centering a setup-time and hold-time window. An access window defined by a setup-time and a hold-time is determined. A determination is made whether the access window is centered about a centerline. The centerline is a point between a predetermined setup-time limit and a predetermined hold-time limit. A dynamic access window centering process is performed in response to the determination that the access window is not centered about the centerline. The dynamic access window centering process includes: determining that the access window has shifted from the centerline; and providing at least one of a dynamic delay and a dynamic speed-up of the access window based upon the determination that the access window has shifted from the centerline.

Abstract: A word line driver for flash memories using NMOS circuitry to reduce parasitic capacitance loading on boost circuitry in low-voltage applications. A delay scheme which delays turn-on of the driver's source-drain circuit for a short time after the turn-on of the driver transistors' gates allows the gate capacitance of the driver transistor to provide an extra boost.

Abstract: A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absence of an error of not properly modifying the data of the group of memory units and determining the completion of proper modification of the data of the group of memory units provided that an error is detected and the error can be corrected.