Flip-flop Patents (Class 365/49.11)
  • Patent number: 10672444
    Abstract: Provided herein is an apparatus that includes an address output circuit configured to output a first address signal including a plurality of bits including a first bit section and a second bit section, and a decoder circuit configured to decode the first address signal to generate a second address signal. The decoder circuit decides an output value of the second address signal based on the first bit section when a value of the second bit section is in a first value range. The decoder circuit decides the output value of the second address signal regardless of the first bit section when a value of the second bit section is in a second value range.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Satoshi Yamanaka
  • Patent number: 10658055
    Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
  • Patent number: 10157126
    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second sense line and configured to store a second element. An example apparatus might also include a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kyle B. Wheeler
  • Patent number: 10121541
    Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Futoshi Igaue, Kenji Yoshinaga, Naoya Watanabe, Mihoko Akiyama
  • Patent number: 10048701
    Abstract: Apparatus, such as a pump controller, features a signal processor configured at least to: receive signaling containing information about a linear set point control curve based at least partly on an adaptive set point control curve related to fluid being pumped by a pump in a pumping system, and determine a control set point based at least partly on the signaling received. The signal processor may be configured to provide a control signal containing information to control the pump based on the control set point determined.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 14, 2018
    Assignee: Fluid Handling LLC
    Inventors: Andrew A. Cheng, James J. Gu, Graham A. Scott
  • Patent number: 9502112
    Abstract: A semiconductor memory device capable of a high-accuracy data search is provided. Each of the memory cells can hold two bits of information and includes a first cell and a second cell. The semiconductor memory device also includes a match line and a search line pair to transfer search data. The semiconductor memory device further includes a logic operation cell to drive the match line based on comparison results between information held in the first and the second cell and search data transferred by the search line pair and a search line driver to drive the search line pair. In a state with the search line pair precharged to a third voltage between a first voltage and a second voltage, the search line driver drives, according to the search data, one and the other search line included in the search line pair to the first and the second voltage, respectively.
    Type: Grant
    Filed: January 24, 2016
    Date of Patent: November 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Nii
  • Patent number: 9224434
    Abstract: A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line, and a second data line. The second type is different from the first type. The first data line is coupled with a first terminal of the sense amplifier. The second data line is coupled with a second terminal of the sense amplifier. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hyun-Sung Hong
  • Patent number: 9177646
    Abstract: A content-addressable memory (CAM) with computational capability is described. The CAM includes an array of CAM cells arranged in rows and columns with a pair of search lines associated with each column of the array and a match line associated with each row of the array. The array of CAM cells is configured to implement, for a given cycle, either a read operation of data contained in a single selected column, or one of a plurality of different bitwise logical operations on data contained in multiple selected columns. All of the pairs of search lines in the columns of the array are configured to a certain state to implement the read operation or one of the plurality of different bitwise logical operations. A result of the read operation or one of the plurality of different bitwise logical operations is outputted onto all of the match lines in the array.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Igor Arsovski
  • Patent number: 9122816
    Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: September 1, 2015
    Assignee: Silicon Graphics International Corp.
    Inventor: Thomas Edward McGee
  • Patent number: 9043561
    Abstract: To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masashi Fujita
  • Patent number: 9042162
    Abstract: A static random access memory (SRAM) cell includes first and second n-channel transistors, first and second p-channel transistors, first and second enable transistors, and first and second pass gates. The first n-channel transistor, the first p-channel transistor, and the first enable transistor are connected in series between first and second reference potentials. The second n-channel transistor, the second p-channel transistor, and the second enable transistor are connected in series between the first and second reference potentials. The first pass gate is configured to selectively connect a first bitline to a first node. The first node is connected to a gate of the first n-channel transistor and a gate of the first p-channel transistor. The second pass gate is configured to selectively connect a second bitline to a second node. The second node is connected to a gate of the second n-channel transistor and a gate of the second p-channel transistor.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 26, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Peter Lee, Winston Lee
  • Patent number: 9036404
    Abstract: An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 9007798
    Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 14, 2015
    Inventor: Laurence H. Cooke
  • Patent number: 9007799
    Abstract: A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to the stored bit and to the stored complementary bit. The compare circuit may be implemented to compare a single-ended reference input to each of the stored bit and the complementary bit. The compare circuit may include a pass circuit to selectively provide the reference input to an output under control of the stored bit and the stored complementary bit, a pull-up circuit to selectively pull-up the output under control of the reference input and the stored complementary bit, and a pull-down circuit to selectively pull-down the output under control of the reference input and the stored bit. The reference input may be provided to multiple CAM cells, which may share compare circuitry.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventor: Khader Mohammad
  • Patent number: 9001568
    Abstract: An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Srinivasa Raghavan Sridhara
  • Patent number: 8995176
    Abstract: Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit. Various layout schemes for the dual-port SRAM cell are further disclosed. A gate electrode serves as the gate for a pull-down transistor and a pull-up transistor, a gate of a first partial dummy transistor, and a gate of a second partial dummy transistor. A butt contact connects a long contact to the gate electrode. The long contact further connects to a drain of a pull-down transistor, a drain of a pull-up transistor, a drain of a first pass gate, and a drain of a second pass gate, wherein the first pass gate and the second pass gate share an active region.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Publication number: 20150085554
    Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.
    Type: Application
    Filed: October 1, 2014
    Publication date: March 26, 2015
    Inventors: Esin Terzioglu, Nishith Desai, Rakesh Vattikonda, ChangHo Jung, Sei Seung Yoon
  • Patent number: 8982596
    Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 17, 2015
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Patent number: 8964453
    Abstract: Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 24, 2015
    Assignee: Synopsys, Inc.
    Inventors: Xi-Wei Lin, Victor Moroz
  • Patent number: 8964457
    Abstract: A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 8953354
    Abstract: A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8947900
    Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
  • Patent number: 8929116
    Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Michael T. Fragano, Travis R. Hebig
  • Patent number: 8929115
    Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 6, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Patent number: 8908409
    Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
  • Patent number: 8902624
    Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Naoya Watanabe
  • Patent number: 8891272
    Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Mihoko Wada
  • Patent number: 8885393
    Abstract: A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Apple Inc.
    Inventors: Ajay Bhatia, Hang Huang
  • Patent number: 8885379
    Abstract: The present disclosure concerns a self-referenced magnetic random access memory-based ternary content addressable memory (MRAM-based TCAM) cell comprising a first and second magnetic tunnel junction; a first and second conducting strap adapted to pass a heating current in the first and second magnetic tunnel junction, respectively; a conductive line electrically connecting the first and second magnetic tunnel junctions in series; a first current line for passing a first field current to selectively write a first write data to the first magnetic tunnel junction; and a second current line for passing a write current to selectively write a second write data to the second magnetic tunnel junction, such that three distinct cell logic states can be written in the MRAM-based TCAM cell.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: November 11, 2014
    Assignee: CROCUS Technology SA
    Inventors: Jeremy Alvarez-Herault, Yann Conraux, Lucien Lombard
  • Publication number: 20140328103
    Abstract: A content-addressable memory (CAM) with computational capability is described. The CAM includes an array of CAM cells arranged in rows and columns with a pair of search lines associated with each column of the array and a match line associated with each row of the array. The array of CAM cells is configured to implement, for a given cycle, either a read operation of data contained in a single selected column, or one of a plurality of different bitwise logical operations on data contained in multiple selected columns. All of the pairs of search lines in the columns of the array are configured to a certain state to implement the read operation or one of the plurality of different bitwise logical operations. A result of the read operation or one of the plurality of different bitwise logical operations is outputted onto all of the match lines in the array.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: International Business Machines Corporation
    Inventor: Igor Arsovski
  • Patent number: 8879334
    Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Ishii, Yoshikazu Saito, Shinji Tanaka, Koji Nii
  • Patent number: 8873278
    Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: October 28, 2014
    Assignee: Altera Corporation
    Inventors: Yanzhong Xu, Jeffrey T. Watt
  • Patent number: 8848411
    Abstract: A shared stack dual-phase CAM cell is provided. The CAM cell includes at least first and second stacks that share a single pair of pull-down transistors. At least one pair of pull-down transistors can thus be eliminated, reducing the area and power consumption of the CAM cell. Sharing of the single pair of pull-down transistors is enabled by time-staggered pre-charge and compare operations such that the pre-charge interval of the first stack corresponds to the compare interval of the second stack, and vice versa.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: September 30, 2014
    Assignee: Broadcom Corporation
    Inventor: Chetan Deshpande
  • Patent number: 8848413
    Abstract: Described is an apparatus which comprises: a memory cell with a data port; and a logic gate, coupled to the data port of the memory cell, to generate a data word-line signal according to data on the data port and an asynchronous word-line signal, wherein the logic gate is operable to gate data on the data port during low power mode.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventor: Eric Kwesi Donkoh
  • Patent number: 8842475
    Abstract: According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Masato Oda, Koichiro Zaitsu, Atsushi Kawasumi, Mari Matsumoto, Shinichi Yasuda
  • Patent number: 8837205
    Abstract: A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Ravindraraj Ramaraju, Andrew C. Russell
  • Patent number: 8837190
    Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 16, 2014
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8830732
    Abstract: A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 8804392
    Abstract: A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a CAM cell array, according to the voltage of a match line. The match amplifier zone comprises one or more NMOS transistors and one or more PMOS transistors. The match amplifier zone has a dead zone to an input of a voltage of the match line, and has a property that no flow-through current is present in the match amplifier zone.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masanobu Kishida
  • Patent number: 8787058
    Abstract: A method for comparing content addressable memory (CAM) elements is disclosed. Binary values are stored in a pair of CAM elements. A comparison value is provided to a group of comparators, the comparison value based on the binary value stored in the pair of CAM elements. A match value is provided to the group of comparators, the match value corresponding to a binary value pair to be compared with the binary value stored in the pair of CAM elements. A positive match result value is output from a selected group of comparators via an output line in response to the comparison value matching the match value.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Michael G. Butler, James Vinh
  • Publication number: 20140192579
    Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: Igor Arsovski, Michael T. Fragano, Travis R. Hebig
  • Patent number: 8767488
    Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: July 1, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Patent number: 8743579
    Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huai-Yang Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
  • Patent number: 8743581
    Abstract: A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yukit Tang, Kuoyuan Hsu, Derek Tao
  • Patent number: 8675397
    Abstract: The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8625320
    Abstract: Quaternary CAM cells are provided that include a compare circuit having a discharge path between a match line and ground potential, the single discharge path consisting essentially of a single transistor. In an embodiment, the single transistor has a gate coupled to a pull-down node and the compare circuit includes first and second gating transistors connected in series between the pull-down node and a ground potential, the first gating transistor having a gate to receive a comparand bit, and the second gating transistor having a gate to receive a complemented comparand bit.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: January 7, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Dimitri Argyres
  • Publication number: 20130322145
    Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 5, 2013
    Applicant: Raytheon Company
    Inventors: Jeong-Gyun Shin, Micky Harris
  • Patent number: 8576599
    Abstract: A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jagreet S. Atwal, Joseph S. Barnes, Kerry Bernstein, Robert J. Bucki, Jason A. Cox
  • Patent number: 8570791
    Abstract: A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jack Liu
  • Patent number: 8542514
    Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 24, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sethuraman Lakshminarayanan, Myongseob Kim