Abstract: A parallel processor in associative content-addressable memory (PPAC) is provided. Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. The PPAC described herein provides a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based complementary metal-oxide-semiconductor (CMOS), which facilitates automated design and portability among technology nodes.

Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

Abstract: A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

Abstract: A method for testing a circuit includes performing, by a test engine, a test of a memory element of the circuit, the test accesses a memory location in the memory element, the memory location is identified by an address, and the memory location is accessed via a first port associated with a first port select bit. The method further includes, in response to detecting a failure associated with the memory location, determining an existing entry for the address in a failed address register, and determining that the existing entry in the failed address register is associated with a second port select bit, distinct from the first port select bit. The method further includes, in response to the second port select bit being distinct from the first port select bit, setting a multi-port failure flag for the memory element that is being tested.

Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.

Abstract: A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

Abstract: The consumption current of a TCAM device is reduced. A semiconductor device includes multiple sub-arrays each including a TCAM cell array. Each sub-array searches the corresponding part of the input search data. Each sub-array outputs the search result indicative of a match for every entry without searching, when the corresponding first control signal is activated.

Abstract: A content addressable memory has many elements in one memory cell; thus, the area of one memory cell tends to be large. In view of the above, it is an object of an embodiment of the present invention to reduce the area of one memory cell. Charge can be held with the use of a channel capacitance in a reading transistor (capacitance between a gate electrode and a channel formation region). In other words, the reading transistor also serves as a charge storage transistor. One of a source and a drain of a charge supply transistor is electrically connected to a gate of the reading and charge storage transistor.

Abstract: A content addressable memory system, method and computer program product is described. The memory system comprises a location addressable store having data identified by location and multiple levels of content addressable stores each holding ternary content words. The content words are associated with references to data in the location addressable store and the content words containing at least one next entry bit for sorting content words in a physical ordered sequence to create content ordered memory. The content store levels might be implemented using different technologies that have different performance, capacity, and cost attributes. The memory system includes a content based cache for improved performance and a content addressable memory management unit for managing memory access operations and virtual memory addressing.

Abstract: A graph display system that represents graph nodes as grid cells in a two-dimensional grid. Graph edges are represented by placing the edge's nodes in adjacent grid cells, thus eliminating the entanglement of edges that are typically drawn as lines between scattered nodes. Relatedness of two nodes sharing an edge is indicated by the edge's weight. The display system prioritizes placement of higher weight edges such that more related information is grouped together in nearby grid cells. Any graph with n nodes and e edges can be displayed and browsed.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

Abstract: Content addressable memory (CAM) devices provide for high density, low cost CAM devices. CAM devices include a non-volatile memory array having a plurality of NAND memory cell strings, wherein a NAND memory cell string of the non-volatile memory array comprises a plurality of CAM memory cells, and wherein the CAM memory cells comprise non-volatile memory cells of a same NAND memory cell string. The CAM devices further include a control circuit, wherein the control circuit is adapted to search data words stored in the plurality of NAND memory cell strings for a match to at least a portion of an input data word.

Abstract: Methods for storing a feature vector, as well as related comparison units and systems. One such method involves programming a string of memory cells of memory to store do not care data as at least a portion of a value of an attribute of the feature vector.

Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.

Abstract: A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare circuit to compare a reference input to the stored bit and to the stored complementary bit. The compare circuit may be implemented to compare a single-ended reference input to each of the stored bit and the complementary bit. The compare circuit may include a pass circuit to selectively provide the reference input to an output under control of the stored bit and the stored complementary bit, a pull-up circuit to selectively pull-up the output under control of the reference input and the stored complementary bit, and a pull-down circuit to selectively pull-down the output under control of the reference input and the stored bit. The reference input may be provided to multiple CAM cells, which may share compare circuitry.

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.

Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.

Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: According to one disclosed embodiment, a content-addressable memory (CAM) system configured for reduced power consumption includes a sensing circuit utilized to apply a sense voltage to a matchline of the CAM system, a valid bit cell coupled to the matchline, and a power cut-off circuit configured to isolate the sense voltage from the matchline when an invalid validity state is stored in the valid bit cell, thereby reducing power consumption by the CAM system. In one embodiment, the power cut-off circuit isolates the sense voltage from the matchline by decoupling the sensing circuit from a control signal when an invalid validity state is stored in the valid bit cell.

Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.

Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.

Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

Abstract: A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.

Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.

Abstract: According to one disclosed embodiment, a content-addressable memory (CAM) system configured for reduced power consumption includes a sensing circuit utilized to apply a sense voltage to a matchline of the CAM system, a valid bit cell coupled to the matchline, and a power cut-off circuit configured to isolate the sense voltage from the matchline when an invalid validity state is stored in the valid bit cell, thereby reducing power consumption by the CAM system. In one embodiment, the power cut-off circuit isolates the sense voltage from the matchline by decoupling the sensing circuit from a control signal when an invalid validity state is stored in the valid bit cell.

Abstract: Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.

Abstract: A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

Abstract: The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.

Abstract: Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

Abstract: A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.

Abstract: Aspects of the disclosure provide a CAM module that can be used independent of a defective entry line. The CAM module can include at least a CAM array having at least X CAM entry lines, and an additional CAM entry line. Each CAM entry line may include a selection line for enabling the CAM entry line for writing and/or reading and an entry output for indicating matching to a search key. Further, the CAM module can include a decoder unit that can decode an address to enable one out of X word-lines, and an encoder unit that can encode X matching outputs to a matching address according to a predetermined priority sequence. Additionally, the CAM module can include a switching unit coupling the CAM array with the decoder unit and the encoder unit.

Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.

Abstract: A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode. In the calibration mode, a leakage-free sense operation is performed to determine the differential voltage generated on the bit lines in response to a data value. Then, a leakage-susceptible test read operation is performed to determine the differential voltage generated on the bit lines in response to the data value. A detection circuit measures the difference between the differential voltages generated in the leakage-free and leakage-susceptible test read operations to generate a compensation signal, which subsequently adjusts the bit line compensation current during the normal mode.

Abstract: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair.

Abstract: The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.

Abstract: Aspects of the disclosure provide a CAM module that can be used independent of a defective entry line. The CAM module can include at least a CAM array having at least X CAM entry lines, and an additional CAM entry line. Each CAM entry line may include a selection line for enabling the CAM entry line for writing and/or reading and an entry output for indicating matching to a search key. Further, the CAM module can include a decoder unit that can decode an address to enable one out of X word-lines, and an encoder unit that can encode X matching outputs to a matching address according to a predetermined priority sequence. Additionally, the CAM module can include a switching unit coupling the CAM array with the decoder unit and the encoder unit.

Abstract: A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result.

Abstract: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged according to a 2-dimensional priority scheme. Data words outside a selected 1×M column are masked to be ignored in determining a match, and the CAM is searched. Each search includes N compare cycles and each compare cycle having a different 1×M column selected. A highest priority match per compare cycle is pipelined from a priority encoder with the pipelined matches arranged to communicate a priority order in a first dimension of the 2-dimensional priority scheme.

Abstract: A segmented ternary content addressable memory (TCAM) search architecture is disclosed. In one embodiment, a TCAM device with a row of TCAM cells includes a first segment of the TCAM cells for determining a match of corresponding search bits of a search string with a first portion of a stored string in the first segment of the TCAM cells, an evaluation module for generating a search enable signal if the match of the corresponding search bits with the first portion of the stored string is determined, and a second segment of the TCAM cells for determining a match of remaining search bits of the search string with a remaining portion of the stored string in response to the search enable signal.

Abstract: Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison.

Abstract: A disclosed embodiment is a range checking CAM array comprising a plurality of words, where each of the plurality of words comprises a plurality of bound check cells. Each of the plurality of bound check cells outputs a corresponding plurality of match signals and a corresponding plurality of bound check signals. The corresponding plurality of match signals and corresponding plurality of bound check signals are combined to produce a range check output indicating whether data on a data input bus is within a target range. The plurality of bound check cells may be coupled to form at least one cascade of bound check cells, where each cascade of bound check cells may be terminated at a ripple logic. The CAM array produces a final range check output based on the corresponding plurality of match signals and the corresponding plurality of bound check signals.

Abstract: A content addressable memory (CAM) is provided that can perform wide word searches. At least one CAM memory core having a plurality of bit pattern entry rows is included in the CAM. In addition, search logic is included that, is capable searching particular rows during each cycle. The search logic is also capable of allowing match line results of unsearched rows to remain unchanged during a cycle. The CAM further includes a serial AND array in communication with the bit pattern entry rows, wherein the serial AND array is capable of computing a match result for wide word entries that span multiple bit pattern entry rows. In one aspect, a match line enable signal is provided to the serial AND array, which facilitates computation of the match result.