Abstract: A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.

Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.

Abstract: A database system is operable to receive a plurality of records of a dataset for storage. A plurality of segment row data is generated from the plurality of records and a plurality of parity data corresponding to the plurality of segment row data is generated. The plurality of segment row data is stored via a first storage mechanism. The plurality of parity data is stored via a second storage mechanism. Execution of a plurality of queries against the dataset is facilitated by accessing the plurality of segment row data via the first storage mechanism. A storage failure of one of the plurality of segment row data via the first storage mechanism is detected. The one of the plurality of segment row data is recovered for storage via the first storage mechanism based on accessing at least one parity data via the second storage mechanism.

Abstract: A memory device includes a plurality of memory cell arrays each configured to include a plurality of memory cells, a plurality of peripheral circuits each configured to perform operations on the plurality of memory cell arrays, a plurality of control logics configured to control the plurality of peripheral circuits, and a control logic selector configured to activate at least one control logic among the plurality of control logics according to a type of a command received from the memory controller.

Abstract: Examples include receiving a first minimum value in a range of consecutive networking integers, determining a first ternary content-addressable memory (TCAM) value based on the minimum, determining a number of trailing zeros in the first TCAM value, determining a proposed TCAM mask based on the number of trailing zeros and a binary opposite of the TCAM value, comparing the proposed TCAM mask to a maximum value associated with the range, determining a first TCAM mask for the first TCAM value based on the comparison, and setting the first TCAM value and the first TCAM mask in a networking device TCAM.

Abstract: A method of generating a behavioral model of a computer system. A processor partitions a system log of process events into a plurality of strands sharing common characteristics. The processor selects attributes from the strands and generates first distinct n-grams that include attributes from successive events within a strand. The processor generates a first plurality of n-gram groups, each including a plurality of the first distinct n-grams in which a first one of the plurality of first distinct n-grams coexists in a strand also containing a second one of the plurality of first distinct n-grams. The processor generates a first plurality of n-gram group arrangements, each containing a plurality of n-gram groups, and each of the n-gram groups included, in combination, in at least one strand, and the behavioral model containing the first distinct n-grams, the first plurality of n-gram groups, and the first plurality of n-gram group arrangements.

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract: A memory subsystem employs spare memory cells external to one or more memory devices. In some embodiments, a processing system uses the spare memory cells to replace individual selected cells at the protected memory, whereby the selected cells are replaced on a cell-by-cell basis, rather than exclusively on a row-by-row, column-by-column, or block-by-block basis. This allows faulty memory cells to be replaced efficiently, thereby improving memory reliability and manufacturing yields, without requiring large blocks of spare memory cells.

Abstract: A fail address detector includes cam latch groups configured to store fail addresses and a comparing section connected to the cam latch groups in common and configured to detect whether or not a fail address corresponding to a comparison address exists among the fail addresses received from the cam latch groups. The cam latch groups share the comparing section in time division.

Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.

Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.

Abstract: A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: An energy-efficient CAM architecture provides increased speed of searching, reduced power consumption, or a tuned combination of increased speed of searching and reduced power consumption. The CAM comprises a plurality of CAM banks, a plurality of Bloom filters, each Bloom filter associated with a content addressable memory bank, each Bloom filter recording elements inserted into an associated content addressable memory bank, wherein the size of each Bloom filter is configured to reduce energy or power consumption of the content addressable memory apparatus. The size of each Bloom filter may be configured to reduce energy or power consumption of the content addressable memory apparatus.

Abstract: Incoming data packets are often processed according to their origination or destination port. In order to efficiently determine applicable rules based on port values, ranges are stored in association with corresponding rules in a ternary memory. In order to reduce the amount of required memory to store these ranges, extra unused bits of the ACL that includes the rule can be used. Further, to maximize the storage capability of these limited extra bits, most common ranges can be stored in one or more bit partitions depending on whether they encompass other most common ranges to be stored in the extra bits. Through partitioning and intelligent bit assignment, many ranges can be stored in the limited extra bits, and can each remain individually addressable.

Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.

Abstract: A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match.

Abstract: A content addressable memory (CAM) device to dynamically reduces power consumption between a search key and data stored in a plurality of CAM blocks by selectively disabling a number of CAM blocks, requested for the search operation by an external network processor, based upon the contents of the search key.

Abstract: A content addressable memory (CAM) row is disclosed. The CAM row includes one or more compare circuits coupled between a match line and a virtual-ground line. The compare circuits are configured to compare a search key with CAM cell data words. The CAM row also includes a pre-charge circuit controlled by a pre-charge signal, and includes a tank capacitor. The pre-charge circuit is configured to pre-charge the match line to a supply voltage in response to assertion of the pre-charge signal. A pull-down transistor dynamically discharges the virtual-ground line to ground potential.

Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.

Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.

Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.

Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.

Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. Further, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract: A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.

Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.

Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.

Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.

Abstract: Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.

Abstract: Aspects of the disclosure provide a method for encoding ranges in a ternary content addressable memory (TCAM). The method includes determining first positive ranges and first negative ranges corresponding to a first encoding range to be encoded in the TCAM. The first encoding range is in association with a first action. The first positive ranges include the first encoding range. The first negative ranges exclude the first encoding range. At least a first positive range and a first negative range are overlapping. Further, the method includes encoding the first positive ranges in first TCAM entries, and encoding the first negative ranges in second TCAM entries. At least one of the second TCAM entries has a higher priority than one of the first TCAM entries. Then, the method includes associating the first TCAM entries to the first action, and associating the second TCAM entries to a reject action.

Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.

Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

Abstract: A memory bit cell suitable for use in semiconductor integrated circuits that utilizes pushed design rules and layout geometries optimized by a semiconductor foundry for standard memory bit cells and edge-cell structures that provides a different functionality from that provided by the foundry standard bit cell. This different functionality is achieved by interconnecting the elements of one or a plurality of standard foundry bit cells and edge cells to implement a different circuit with different operation from the original bit cells and edge cells. The positioning and interconnection of the standard bit cells and edge cells are implemented in a manner so as to maintain the same periodic geometric proximity effects to the maximum degree possible. A preferred embodiment of this invention is to interconnect two standard foundry six-transistor SRAM bit cells and two edge cells to create a Ternary Content Addressable Memory bit cell with mask and compare functionality in addition to bit storage functionality.

Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.

Abstract: A network apparatus comprises a plurality of ports, and a forwarding engine coupled to the plurality of ports. The forwarding engine is configured to transfer data units received via at least some of the plurality of ports to one or more appropriate ports in the plurality of ports. The forwarding engine comprises a content addressable memory (CAM) device to store a plurality of data patterns organized in a plurality of groups, wherein the CAM device is configured to, responsive to input data, output in a single cycle a plurality of match indications corresponding to the plurality of groups. The forwarding engine also comprises a logic device coupled to the CAM device and configured to generate an action value based on the plurality of match indications, wherein the action value indicates an action to be taken by the forwarding engine.

Abstract: Methods for efficiently managing a ternary content-addressable memory (TCAM) by minimizing movements of TCAM entries include determining a first node and a second node in the TCAM, determining if there is a free TCAM entry between the first node and the second node, and storing the new entry in the free TCAM entry. Upon determining that a free TCAM entry does not exist between the first node and the second node, further determining a chain of nodes and then determining if there is a free TCAM entry in the chain of nodes. Upon determining that there is a free TCAM entry within the chain of nodes, moving the TCAM entries identified as the nodes in the chain of nodes to generate a free node nearest to the new entry and inserting the new entry in the free node. Moving the TCAM entries identified as the nodes in the chain of nodes preserves the order of the nodes.

Abstract: A method of placing a content addressable memory (CAM) into a low current state is disclosed. The CAM can include at least one storage location that does not store valid data for a compare operation and includes a plurality of CAM cells, each CAM cell having at least two data controllable impedance paths arranged in parallel with one another. The method can include configuring the majority of the CAM cells to store data values that maintain the corresponding at least two data controllable impedance paths in high impedance states.

Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

Abstract: A CAM device memory array having different types of memory cells. A CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data. In particular, at least one portion consists of binary CAM cells and the other portion consists of ternary CAM cells. The portions can be partitioned along the row, or matchline, direction or along the bitline direction. Since particular data formats only require predefined bit positions of a word of data to be ternary in value, the remaining binary bit positions can be stored in binary CAM cells. Therefore, the CAM device memory array will occupy an overall area that is less than memory arrays of the same density consisting exclusively of ternary CAM cells.

Abstract: Disclosed herein is a method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In the method and apparatus described herein, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.

Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.