Segmented/partitioned Of Cells Patents (Class 365/49.16)
  • Patent number: 9575891
    Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M?A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 21, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John R. Riley, Russell Schreiber, Donald R. Weiss, John J. Wuu, William A. McGee
  • Patent number: 9406403
    Abstract: A memory subsystem employs spare memory cells external to one or more memory devices. In some embodiments, a processing system uses the spare memory cells to replace individual selected cells at the protected memory, whereby the selected cells are replaced on a cell-by-cell basis, rather than exclusively on a row-by-row, column-by-column, or block-by-block basis. This allows faulty memory cells to be replaced efficiently, thereby improving memory reliability and manufacturing yields, without requiring large blocks of spare memory cells.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: August 2, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Vilas Sridharan, James M. O'Connor
  • Patent number: 9208879
    Abstract: A fail address detector includes cam latch groups configured to store fail addresses and a comparing section connected to the cam latch groups in common and configured to detect whether or not a fail address corresponding to a comparison address exists among the fail addresses received from the cam latch groups. The cam latch groups share the comparing section in time division.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 8, 2015
    Assignee: SK HYNIX INC.
    Inventor: Sang Oh Lim
  • Patent number: 9158607
    Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Patent number: 9025354
    Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventor: Shankar Channabasappa
  • Patent number: 8995160
    Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics SA
    Inventors: Olivier Menut, David Turgis, Lorenzo Ciampolini
  • Patent number: 8982596
    Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 17, 2015
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Bindiganavale S. Nataraj, Sandeep Khanna
  • Patent number: 8953354
    Abstract: A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8934278
    Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 13, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Rakesh Vattikonda, Nishith Desai, ChangHo Jung, Sei Seung Yoon, Esin Terzioglu
  • Patent number: 8929115
    Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 6, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Patent number: 8917530
    Abstract: An energy-efficient CAM architecture provides increased speed of searching, reduced power consumption, or a tuned combination of increased speed of searching and reduced power consumption. The CAM comprises a plurality of CAM banks, a plurality of Bloom filters, each Bloom filter associated with a content addressable memory bank, each Bloom filter recording elements inserted into an associated content addressable memory bank, wherein the size of each Bloom filter is configured to reduce energy or power consumption of the content addressable memory apparatus. The size of each Bloom filter may be configured to reduce energy or power consumption of the content addressable memory apparatus.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: December 23, 2014
    Assignee: University of Rochester
    Inventor: Tolga Soyata
  • Patent number: 8909857
    Abstract: Incoming data packets are often processed according to their origination or destination port. In order to efficiently determine applicable rules based on port values, ranges are stored in association with corresponding rules in a ternary memory. In order to reduce the amount of required memory to store these ranges, extra unused bits of the ACL that includes the rule can be used. Further, to maximize the storage capability of these limited extra bits, most common ranges can be stored in one or more bit partitions depending on whether they encompass other most common ranges to be stored in the extra bits. Through partitioning and intelligent bit assignment, many ranges can be stored in the limited extra bits, and can each remain individually addressable.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 9, 2014
    Assignee: Broadcom Corporation
    Inventor: Parineeth M. Reddy
  • Patent number: 8902624
    Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Naoya Watanabe
  • Patent number: 8891273
    Abstract: A method within a ternary content addressable memory (TCAM) includes receiving a match line output from a previous TCAM stage at a gate of a pull-up transistor of a current TCAM stage and at a gate of a pull-down transistor of the current TCAM stage. The method sets a match line bar at the current TCAM stage to a low value, via the pull-down transistor, when the match line output from the previous TCAM stage indicates a mismatch. The method also sets the match line bar at the current TCAM stage to a high value, via the pull-up transistor, when the match line output from the previous TCAM stage indicates a match.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Rakesh Vattikonda, Nishith Desai, Changho Jung
  • Patent number: 8891272
    Abstract: There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. A priority encoder and row decoder portion shares a row address register including more than one row. Each row of the row address register corresponds to each entry of a TCAM array mat and retains each address. Each row of the row address register corresponds to each word line and match line of the TCAM array mat. Writing data to the TCAM array mat activates word line for a row retained in the row address register corresponding to a specified address. Searching for the TCAM array mat activates a match line for the TCAM array mat. The row address register for the corresponding row stores the address of an entry for the TCAM array mat matching search data.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Mihoko Wada
  • Patent number: 8861241
    Abstract: A content addressable memory (CAM) device to dynamically reduces power consumption between a search key and data stored in a plurality of CAM blocks by selectively disabling a number of CAM blocks, requested for the search operation by an external network processor, based upon the contents of the search key.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: October 14, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Cristian Estan
  • Patent number: 8837188
    Abstract: A content addressable memory (CAM) row is disclosed. The CAM row includes one or more compare circuits coupled between a match line and a virtual-ground line. The compare circuits are configured to compare a search key with CAM cell data words. The CAM row also includes a pre-charge circuit controlled by a pre-charge signal, and includes a tank capacitor. The pre-charge circuit is configured to pre-charge the match line to a supply voltage in response to assertion of the pre-charge signal. A pull-down transistor dynamically discharges the virtual-ground line to ground potential.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 16, 2014
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Ganesh Krishnamurthy, Dimitri Argyres
  • Patent number: 8837190
    Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 16, 2014
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8787059
    Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: July 22, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Vinay Iyengar
  • Patent number: 8773880
    Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: July 8, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Dimitri Argyres
  • Patent number: 8767428
    Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics International N. V.
    Inventor: Vivek Asthana
  • Patent number: 8767429
    Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. Further, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 1, 2014
    Assignee: Broadcom Corporation
    Inventors: Christopher Gronlund, Mark Winter
  • Patent number: 8767488
    Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: July 1, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S. Nataraj
  • Patent number: 8687398
    Abstract: A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8659926
    Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 25, 2014
    Assignee: Adesto Technologies Corporation
    Inventor: Narbeh Derhacobian
  • Patent number: 8654555
    Abstract: A control signal generator to generate control signals for a readout integrated circuit (ROIC) includes a content addressable memory (CAM) and a random access memory (RAM). The CAM may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals. The RAM may have data stored within it that is indicative of particular control signals that are to be toggled at the times indicated within the CAM.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 18, 2014
    Assignee: Raytheon Company
    Inventors: Jeong-Gyun Shin, Micky Harris
  • Patent number: 8638582
    Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Dimitri Argyres
  • Patent number: 8564998
    Abstract: Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 22, 2013
    Assignee: Renesas Electronic Corporation
    Inventor: Kazunari Inoue
  • Patent number: 8542514
    Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 24, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sethuraman Lakshminarayanan, Myongseob Kim
  • Patent number: 8468296
    Abstract: Aspects of the disclosure provide a method for encoding ranges in a ternary content addressable memory (TCAM). The method includes determining first positive ranges and first negative ranges corresponding to a first encoding range to be encoded in the TCAM. The first encoding range is in association with a first action. The first positive ranges include the first encoding range. The first negative ranges exclude the first encoding range. At least a first positive range and a first negative range are overlapping. Further, the method includes encoding the first positive ranges in first TCAM entries, and encoding the first negative ranges in second TCAM entries. At least one of the second TCAM entries has a higher priority than one of the first TCAM entries. Then, the method includes associating the first TCAM entries to the first action, and associating the second TCAM entries to a reject action.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: June 18, 2013
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Rami Cohen
  • Patent number: 8462533
    Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: June 11, 2013
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8451640
    Abstract: A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: May 28, 2013
    Assignee: Broadcom Corporation
    Inventors: Christopher Gronlund, Mark Winter
  • Patent number: 8441828
    Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Naoya Watanabe
  • Patent number: 8355269
    Abstract: A memory bit cell suitable for use in semiconductor integrated circuits that utilizes pushed design rules and layout geometries optimized by a semiconductor foundry for standard memory bit cells and edge-cell structures that provides a different functionality from that provided by the foundry standard bit cell. This different functionality is achieved by interconnecting the elements of one or a plurality of standard foundry bit cells and edge cells to implement a different circuit with different operation from the original bit cells and edge cells. The positioning and interconnection of the standard bit cells and edge cells are implemented in a manner so as to maintain the same periodic geometric proximity effects to the maximum degree possible. A preferred embodiment of this invention is to interconnect two standard foundry six-transistor SRAM bit cells and two edge cells to create a Ternary Content Addressable Memory bit cell with mask and compare functionality in addition to bit storage functionality.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 15, 2013
    Assignee: eSilicon Corporation
    Inventor: Michael Anthony Zampaglione
  • Patent number: 8320148
    Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: November 27, 2012
    Assignee: Adesto Technologies Corporation
    Inventor: Narbeh Derhacobian
  • Patent number: 8284582
    Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 9, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazunari Inoue
  • Patent number: 8199547
    Abstract: A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: June 12, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, Michael D. Snyder
  • Patent number: 8176242
    Abstract: A network apparatus comprises a plurality of ports, and a forwarding engine coupled to the plurality of ports. The forwarding engine is configured to transfer data units received via at least some of the plurality of ports to one or more appropriate ports in the plurality of ports. The forwarding engine comprises a content addressable memory (CAM) device to store a plurality of data patterns organized in a plurality of groups, wherein the CAM device is configured to, responsive to input data, output in a single cycle a plurality of match indications corresponding to the plurality of groups. The forwarding engine also comprises a logic device coupled to the CAM device and configured to generate an action value based on the plurality of match indications, wherein the action value indicates an action to be taken by the forwarding engine.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: May 8, 2012
    Assignee: Marvell International Ltd.
    Inventors: Michael Shamis, Roman Ronin, Tal Anker
  • Patent number: 8090901
    Abstract: Methods for efficiently managing a ternary content-addressable memory (TCAM) by minimizing movements of TCAM entries include determining a first node and a second node in the TCAM, determining if there is a free TCAM entry between the first node and the second node, and storing the new entry in the free TCAM entry. Upon determining that a free TCAM entry does not exist between the first node and the second node, further determining a chain of nodes and then determining if there is a free TCAM entry in the chain of nodes. Upon determining that there is a free TCAM entry within the chain of nodes, moving the TCAM entries identified as the nodes in the chain of nodes to generate a free node nearest to the new entry and inserting the new entry in the free node. Moving the TCAM entries identified as the nodes in the chain of nodes preserves the order of the nodes.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 3, 2012
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Kevin Kwun-Nan Lin, Gefan Zhang, Rajeshekhar Murtinty
  • Patent number: 8085568
    Abstract: A method of placing a content addressable memory (CAM) into a low current state is disclosed. The CAM can include at least one storage location that does not store valid data for a compare operation and includes a plurality of CAM cells, each CAM cell having at least two data controllable impedance paths arranged in parallel with one another. The method can include configuring the majority of the CAM cells to store data values that maintain the corresponding at least two data controllable impedance paths in high impedance states.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 27, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Martin Fabry
  • Patent number: 8077492
    Abstract: A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito, Hideyuki Noda
  • Patent number: 8031502
    Abstract: A CAM device memory array having different types of memory cells. A CAM device memory array is subdivided into at least two different portions, where each portion uses only one particular type of CAM cell, and each portion is dedicated to storing a particular type of data. In particular, at least one portion consists of binary CAM cells and the other portion consists of ternary CAM cells. The portions can be partitioned along the row, or matchline, direction or along the bitline direction. Since particular data formats only require predefined bit positions of a word of data to be ternary in value, the remaining binary bit positions can be stored in binary CAM cells. Therefore, the CAM device memory array will occupy an overall area that is less than memory arrays of the same density consisting exclusively of ternary CAM cells.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: October 4, 2011
    Assignee: Mosaid Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 7969758
    Abstract: Disclosed herein is a method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In the method and apparatus described herein, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 28, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sunder Rathnavelu Raj
  • Patent number: 7957172
    Abstract: According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: June 7, 2011
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 7957171
    Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: June 7, 2011
    Assignee: Hiroshima University
    Inventors: Md. Anwarul Abedin, Tetsushi Koide, Hans Juergen Mattausch, Yuki Tanaka
  • Patent number: 7936577
    Abstract: A content addressable memory (CAM) may include a plurality of precharge circuits, each coupled to a group of CAM cells and comprising a first precharge path that is temporarily enabled in response to an activated first control signal, and a second precharge path that is temporarily enabled in response to an activated second control signal and a valid indication that indicates whether or not the corresponding group of CAM cells stores valid data, the valid indication being different than the first and second control signals.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 3, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Martin Fabry
  • Patent number: 7924590
    Abstract: A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: April 12, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Alexei Starovoitov, Maheshwaran Srinivasan, Varadarajan Srinivasan, Sandeep Khanna, Sachin Joshi, Mark Birman
  • Patent number: 7920399
    Abstract: A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match line segment, and a match line control circuit having an input coupled to the corresponding match line segment, an output coupled to the match line segment in a next row segment, and a control terminal to receive a corresponding enable signal. The configuration circuit has an input to receive configuration information indicative of a width and depth configuration of the CAM array and having outputs to generate the enable signals.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: April 5, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Vinay Iyengar, Chetan Deshpande, Sandeep Khanna
  • Patent number: 7911818
    Abstract: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: March 22, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Scott Chu
  • Patent number: 7903443
    Abstract: The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: March 8, 2011
    Assignee: National Chiao Tung University
    Inventors: Po-Tsang Huang, Wei Hwang, Shu-Wei Chang