Compare/search/match Circuit Patents (Class 365/49.17)
  • Patent number: 10956335
    Abstract: Data blocks are cached in a persistent cache (“NV cache”) allocated from as non-volatile RAM (“NVRAM”). The data blocks may be accessed in place in the NV cache of a “source” computing element by another “remote” computing element over a network using remote direct memory access (“RMDA”). In order for a remote computing element to access the data block in NV cache on a source computing element, the remote computing element needs the memory address of the data block within the NV cache. For this purpose, a hash table is stored and maintained in RAM on the source computing element. The hash table identifies the data blocks in the NV cache and specifies a location of the cached data block within the NV cache.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 23, 2021
    Assignee: Oracle International Corporation
    Inventors: Zuoyu Tao, Jia Shi, Kothanda Umamageswaran, Juan R. Loaiza
  • Patent number: 10930348
    Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 23, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10861549
    Abstract: A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai, Hsin-Chih Yu, Shu-Ru Wang
  • Patent number: 10861508
    Abstract: A methodology and structure for a encoding a data stat signal in the data lock signal, e.g., the data strobe signal such as DBQ. The data strobe signal can maintain the clock continuity, e.g., the rise and fall edges are at the timing signal, and the data inversion can be based on the amplitude of the data strobe signal. This allows the data set on the data lines, e.g., D0-D7, to either be non-inverted or inverted, to save power consumed in the memory device.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 8, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Shiv Mathur, Nitin Gupta, Ramakrishnan Subramanian
  • Patent number: 10847224
    Abstract: Systems, devices, and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). The TCAM comprises a plurality of memristor-based TCAM (mTCAM) cells, each consisting of two memristors and two transistors. The first and second memristors are connected in series, with a first end of the first memristor connected to a first data line, first end of the second memristor connected to a second data line, and the second ends of the resistors connected together at a common node. The drain of a programming transistor is connected to the common node, with the source connected to a third data line, and the gate connected to a word line. Common node is further connected to the gate of a match-line transistor, such that if a mismatch is detected common node applies a voltage to the gate to pull-down the voltage on a pre-charged match line.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10782968
    Abstract: A substring can be detected within a string of data elements through a method that includes partitioning and distributing the string of data elements to an ordered list of segments having equal lengths greater than or equal to the length of the substring. A substring match within a segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. A carry vector that includes the substring match can be created, in response to detecting the substring match that is a partial match. It can be determined that a carry vector exists by comparing the substring with the segment of the ordered list of segments, and it can be subsequently determined that a full match exists between the carry vector and the segment of the ordered list of segments.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Razvan Peter Figuli, Stefan Payer, Cedric Lichtenau, Kerstin C. Schelm
  • Patent number: 10762960
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 10741228
    Abstract: A memory device capable of reading reference data while achieving optimization of electric power consumption is provided. A memory device includes a memory area storing reference data of N (?1) dimensions each composed of M (?1) bits. A number of memory grains each composed of nonvolatile memory and power drivers paired with the memory grains to supply electrical power to the memory grains are provided in each region specified by column lines in the number and M row lines, the number being one to N inclusive. When the power driver receives a control signal from the corresponding one of the column lines, a control signal from the corresponding one of the M row lines, and a clock signal, the power driver supplies electrical power to the memory grain in synchronization with the clock signal.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: August 11, 2020
    Assignee: Tohoku University
    Inventors: Yitao Ma, Tetsuo Endoh
  • Patent number: 10714181
    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin
  • Patent number: 10594577
    Abstract: A method including: in a network element that includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element and a utilization management process running on the network element, the utilization management process performing operations including: obtaining a plurality of entries of the one or more hardware memory resources representing utilization of the one or more hardware memory resources by network traffic passing through the network element; sorting the plurality of entries of the one or more hardware memory resources by statistics associated with the network traffic passing through the network element to produce sorted entries; and sending the extracted to a network management application for display is disclosed. An apparatus and one or more non-transitory computer readable storage media to execute the method are also provided.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 17, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Deven Walia, Rakesh B. Goudar, Samar Sharma
  • Patent number: 10580490
    Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Koji Nii
  • Patent number: 10565341
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10545865
    Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit may multiply bit vectors representing key values by a sparse bit matrix and may add a constant bit vector to the results. The hash function sub-circuits may be constructed using odd-parity circuits that accept as inputs subsets of the bits of the bit vectors representing the key values. The sparse bit matrices may be chosen or generated so that there are at least twice as many 0-bits per row as 1-bits or there is an upper bound on the number of 1-bits per row. Using sparse bit matrices in the hash function sub-circuits may allow the lookup circuit to perform lookup operations with very low latency.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 28, 2020
    Assignee: Oracle International Corporation
    Inventors: Guy L. Steele, Jr., David R. Chase
  • Patent number: 10496642
    Abstract: A hardware accelerator 2 for performing queries into, for example, an indexed text log files is formed of plurality of hardware execution units (text engines) 4, each executing a partial query program upon the same full set of input data. These partial query programs may switch between different query algorithms on up to a per-character basis. The sequence of data when loaded into a buffer memory 16 for querying may be searched for delimiters as the data is loaded. The hardware execution units may support a number match program instruction which serves to identify a numeric variable, and to determine a value of that numeric variable located at a variable position within a sequence of characters being queried.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: December 3, 2019
    Assignee: The Regents of the University of Michigan
    Inventors: Prateek Tandon, Thomas Friedrich Wenisch, Michael John Cafarella
  • Patent number: 10418103
    Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 17, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Brent Buchanan, John Paul Strachan, Le Zheng, Catherine Graves
  • Patent number: 10387251
    Abstract: In one embodiment, error detection and correction is performed in a content-addressable memory using single-bit position lookup operations. A lookup operation is performed generating a resultant match vector reflective of matching a single-bit position within each of multiple content-addressable memory entries against a corresponding bit value at the single-bit position within a lookup word. The resultant match vector is processed to determine if there are any errors and typically which entries contain a wrong bit value. The correct match vector (e.g., having no errors) is determined from the correct stored matching values (e.g., those used to program the content-addressable memory entries) and the value at the single-bit position within the lookup word. One embodiment compares the correct and resultant match vectors, while one embodiment performs this comparison using an error-correcting code of the correct match vector.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: August 20, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Doron Shoham, Ilan Lisha
  • Patent number: 10379926
    Abstract: A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 13, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen Long Chang, Ken Hui Chen, Su Chueh Lo, Chia-Feng Cheng
  • Patent number: 10366756
    Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
  • Patent number: 10360965
    Abstract: A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Marco Domenico Tiburzi
  • Patent number: 10347337
    Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Alexander Fritsch
  • Patent number: 10339043
    Abstract: An apparatus, system, and method is described for calculating a composite index into a customizable hybrid address space that is at least partially compressed to locate a longest prefix match (“LPM”) of a prefix string comprised of a plurality of multi-bit strides (“MBSs”). The device comprises: a mask-and-count logic for generating a base index into memory for a first MBS whose addresses are not compressed; a logical-shift apparatus that selectively uses a variable portion of the second MBS to generate an offset index from the given base index per an amount the second MBS addresses were actually compressed; and an add logic that adds the base index to the offset index to form the composite index that locates the LPM using a single access into memory. A compressed vector contains compression information of the second MBS in an information density format greater than a single bit to a single address.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 2, 2019
    Assignee: MoSys, Inc.
    Inventor: Michael J Miller
  • Patent number: 10324866
    Abstract: An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the register. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Ichimura, Takeshi Kuga
  • Patent number: 10262738
    Abstract: In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 16, 2019
    Assignee: NEC CORPORATION
    Inventors: Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi
  • Patent number: 10090033
    Abstract: A physically-unclonable-function (PUF) circuit and the control method thereof are provided, and the control method can be applied to the magnetoresistive device. The control method includes providing a first energy to a plurality of magnetic-tunnel junction (MTJ) devices after initializing the MTJ devices to a resistance state, and determining whether the hamming weight of at least one of the MTJ devices which has a predetermined resistance state is within a predetermined range or not.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 2, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Duan-Lee Tang, Yu-Sheng Chen, Ding-Yeong Wang
  • Patent number: 10074428
    Abstract: In a recording technique in which a plurality of light spots are simultaneously formed by using an ultra-short pulse laser and a spatial phase modulator, and a plurality of recording dots having refractive indexes different from those of the vicinities thereof are formed inside a recording medium, it is hard to make recording quality and a recording density compatible. Therefore, a plurality of dots are recorded at a predetermined dot pitch, and then other dots are recorded between the recorded dots.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 11, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Shiozawa, Yasuhiko Shimotsuma, Masaaki Sakakura, Kiyotaka Miura, Miki Nakabayashi
  • Patent number: 9984730
    Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of a negative supply rail positive boost circuit can be employed to weaken an NFET pull-down transistor in a storage circuit of a memory bit cells having a PFET write port(s).
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 29, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jihoon Jeong, Francois Ibrahim Atallah, Keith Alan Bowman, David Joseph Winston Hansquine, Hoan Huu Nguyen
  • Patent number: 9977625
    Abstract: A data processing system may include at least two memory systems including first and second memory systems to which a logical address and a command are applied in parallel from a host.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventor: Byung-Soo Jung
  • Patent number: 9911496
    Abstract: A k-nearest neighbors associative memory includes: a clock counting type associative memory that holds R pieces of reference data and outputs, for each of the R pieces of reference data, a match signal that becomes active when a clock count corresponding to a distance between the reference data and given search data has been reached; and a k-nearest neighbors clustering circuit that, every time at least one of the R match signals output from the clock counting type associative memory becomes active, selects a piece of class data, out of R pieces of class data representing classes of the R pieces of reference data, corresponding to each of the at least one active match signal, until k match signals out of the R match signals become active, and determines a class having a largest number of pieces of data when the selected total k pieces of class data are classified.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 6, 2018
    Assignee: HIROSHIMA UNIVERSITY
    Inventors: Hans Juergen Mattausch, Shogo Yamasaki
  • Patent number: 9892789
    Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Alexander Fritsch
  • Patent number: 9880747
    Abstract: A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: January 30, 2018
    Assignee: XITORE, INC.
    Inventor: Mike Hossein Amidi
  • Patent number: 9824738
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory area, a first selection circuit for selecting a bit line of the first memory area, a second memory area, a second selection circuit for selecting a bit line of the second memory area, and a third selection circuit arranged between the first selection circuit and the second selection circuit and configured to select either the first selection circuit or the second selection circuit.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumiyoshi Matsuoka, Tadashi Miyakawa
  • Patent number: 9824756
    Abstract: Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: November 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Brand, Minsik Cho, Ruchir Puri, Andrew J. Sullivan
  • Patent number: 9761289
    Abstract: A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David E. Schmitt, Tobias Werner, Brian J. Yavoich
  • Patent number: 9721661
    Abstract: An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 1, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Le Zheng, John Paul Strachan
  • Patent number: 9715470
    Abstract: Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to initiate a DMA transfer; providing, by the adapter, a translation tag (‘XTAG’) to the accelerator; receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; generating, by the adapter, a DMA instruction comprising a real address based on the XTAG; and sending, by the adapter, the generated DMA instruction comprising the real address to a communications bus.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Etai Adar, Lakshminarayana B. Arimilli, Yiftach Benjamini
  • Patent number: 9717011
    Abstract: In a telecommunications network, information about events that occur at nodes (27) is sent to event-based management applications (31) in operations and maintenance servers (21). Event reports (23) comprising such event information are replaced or accompanied in data packets by event summaries (33). The summaries (33) can be used to route the data packets to the correct event-based management application (31) with less processing time and resources than if the event reports (23) are used for routeing, because information about the events can be obtained from the summaries (33) more easily than from the event reports (23). Routeing using the summaries (33) may be done in a fast path. Some event-based management applications can use the summaries (33) instead of the event reports (23), which can also save processing time and resources, and such event-based management applications may be performed in a fast path.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: July 25, 2017
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Yangcheng Huang, Jan Groenendijk
  • Patent number: 9704575
    Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Michael T. Fragano, Robert M. Houle, Thomas M. Maffitt
  • Patent number: 9697910
    Abstract: An aspect includes a method of multi-match error detection in content addressable memory (CAM) testing. The method includes loading a content addressing row of a CAM section with a row test address word. Data value rows of a random access memory (RAM) section are loaded with unique test patterns in each of the data value rows having a same number of on-state bits per data value row. A row test is initiated to search for a matching content addressing row in the CAM section corresponding to the row test address word. A row test result is received as one or more data value rows from the RAM section identified as having a content addressing row in the CAM section that matches the row test. The row test result is compared to an aspect of one or more of the unique test patterns to determine whether the row test has failed.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, Pradip Patel, Daniel Rodko
  • Patent number: 9613710
    Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Chung-Chieh Chen, Yu-Der Chih
  • Patent number: 9613700
    Abstract: A content addressable memory (“CAM”) field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 4, 2017
    Assignee: Invecas, Inc.
    Inventors: Harold Pilo, Gerald P. Pomichter, Michael Lee, John Edward Barth, Jr.
  • Patent number: 9589514
    Abstract: Methods and apparatus for reduced bandwidth pulse width modulation are disclosed. A system includes a digital controller circuit coupled to a data interface, the digital controller circuit configured to receive image data for display and further configured to encode line data for transmission to a spatial light modulator using a data compression scheme; and the spatial light modulator coupled to the data interface and configured to receive encoded data and to decode the encoded data to produce unencoded data corresponding to pixel data for display on an array of pixel elements in the spatial light modulator; wherein data transmitted from the digital controller circuit to the spatial light modulator further comprises encoded data that is formed from bit planes using a data compression scheme to form partial lines of data. Additional methods and apparatus are disclosed.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: March 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Todd Alan Clatanoff, Jeffrey Matthew Kempf
  • Patent number: 9583192
    Abstract: The present disclosure relates to content addressable memories (CAM), and more particularly, to a searchable CAM structure having self-reference matchline precharge and local feedback control and method of use. The present disclosure includes a structure which includes: a sense line connected to a sensing device; a feedback line connected to the sense line at a tap point between a first end and a second end of the sense line; and a local precharge controller connected to the tap point by the feedback line to control precharging of the sense line according to a state of the feedback line.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Michael T. Fragano, Thomas M. Maffitt, Robert M. Houle
  • Patent number: 9583163
    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Tiwari, Kyle Wheeler
  • Patent number: 9571396
    Abstract: A system may include receiving a packet, of a packet stream, including control tags in a header portion of the packet and classifying each of the control tags into a category selected from a set of possible categories. The set of possible categories may include an unambiguous interposable (UI) category that is assigned to a control tag that corresponds to an unambiguous parsing interpretation and that is interposable within a sequence of the control tags, and an ambiguous interposable (AI) category that is assigned to a control tag in which the control tag has an ambiguous parsing interpretation and in which the control tag is interposable within the sequence of the control tags. The method may further include determining parsing operations to perform for the packet based on the classified categories of the control tags and based on the packet stream of the packet.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: February 14, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: David Talaski, Avanindra Godbole, Jean Marc Frailong, Fanyun Kong
  • Patent number: 9569561
    Abstract: A network device receives data packets and derives a key from headers in the packets. A search engine in the device searches, or performs a table lookup, for information based on the key and multiple programmable masks. The search engine includes a hash based search engine that comprises multiple mask modules each to mask an input key with a respective programmable mask, to produce multiple masked keys. The search engine also includes an array of hash modules each corresponding to a respective one of the masked keys and including a hash table. Each of the hash modules searches its hash table for a data value based on a hash of the corresponding masked key, and outputs a found data value, if any, resulting from the search. A selector selects among the found data values and output the selected data value.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 14, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Christopher A. Wildman, Laura Sharpless
  • Patent number: 9564183
    Abstract: A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: February 7, 2017
    Assignee: Invecas, Inc.
    Inventor: John Edward Barth, Jr.
  • Patent number: 9471582
    Abstract: A computer determines a degree of information duplication between at least two files included in an original pre-fetch list. The computer generates a re-ordered pre-fetch list by re-ordering the files included in the original pre-fetch list. The re-ordering is based, at least in part, on the degree of information duplication between the two files included in the original pre-fetch list. The files included in the original pre-fetch list are re-ordered by grouping files containing higher degrees of duplicate information closer together in the re-ordered pre-fetch list.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kalyan C. Gunda, Mukti Jain, Sandeep R. Patil, Riyazahamad M. Shiraguppi
  • Patent number: 9412470
    Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-pil Son, Young-soo Sohn
  • Patent number: 9406381
    Abstract: A search unit including a distributor TCAM and a DRAM search unit and a method to divide a database of TCAM rules is disclosed. The method includes selecting a rule having multiple “don't care” values and selecting a bit of the rule having a “don't care” value, generating two distributor rules based on the selected rule, associating rules of the database which match each of the distributor rules with the distributor rule they match to create subset databases, and repeating the steps of selecting, generating and associating until the average number of rules in each subset database is at or below a predefined amount. A DRAM storage unit has a section for each subset database, where each section is pointed to by a different distributor rule. A DRAM search unit matches an input key to one of the rules in the section pointed to by the matched distributor rule.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 2, 2016
    Assignee: GSI TECHNOLOGY ISRAEL LTD.
    Inventors: Avidan Akerib, Oren Agam, Eli Ehrman
  • Patent number: 9400711
    Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: July 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, Mihir A. Pandya, Andrew C. Russell