Abstract: A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.

Abstract: A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract: A read, write, and match circuit for a low-voltage content addressable memory. A write circuit inputs signals for storing data in the memory cells, a read circuit retrieves the stored data from the memory cells, and a match circuit compares the data stored in the memory cell with the data searched by the match circuit. The circuits for writing, reading and matching are separated from each other and exempt from mutual interference.

Abstract: A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.

Abstract: A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.

Abstract: The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.

Abstract: Techniques for providing a unified view of a domain model to a user are described herein. In one embodiment, in response to a first search query received from a client via a first search mechanism (e.g., outside of the relational DB) for a list of persistent objects representing data entries of a relational database, it is determined whether the persistent objects have been accessed via a second search query via a second search mechanism based on an object identifier of the persistent object. If the requested persistent object has been accessed via a second search query, an identical instance of the persistent object is returned to the client as a result of the first search query. Other methods and apparatuses are also described.

Abstract: According to an example embodiment, a CAM cell included in a CAM may include a phase change memory device, a connector, and/or a developer. The phase change memory device may be configured to store data. The phase change memory device may have a resistance that may be varied according to the logic level of the stored data. The connector may be configured to control writing data to the phase change memory device and reading data from the phase change memory device. The developer may be configured to control reading data from the phase change memory device in a search mode in which the data stored in the phase change memory device is compared to the search data.

Abstract: Disclosed herein is a method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In the method and apparatus described herein, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.

Abstract: A search engine includes a storage module to store a plurality of data patterns, a plurality of busses to receive a plurality of representations of a search word, a selector corresponding to at least one of the plurality of data patterns to select one of the plurality of representations of the search word for comparing to the at least one of the plurality of data patterns, and a logic circuit operatively coupled to the storage module, to the plurality of busses, and to the selector to compare the selected one of the plurality of representations of the search word to the at least one of the plurality of data patterns.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.

Abstract: For receiving an input data, a pattern data and a data clock signal and outputting a hit signal and an address signal, a content addressable memory includes a plurality of content addressable memory units connected in series, each content addressable memory unit being adapted to receive the input data and the data clock signal and to output a comparison result signal, and an encoder coupled to the comparison result signal of each content addressable memory unit and adapted for outputting a hit signal and a memory address signal subject to the comparison result signal received.

Abstract: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.

Abstract: A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced.

Abstract: A scheme for bit cell designs for ternary content addressable memory for comparing search data with content data is disclosed. In one embodiment, a system for comparing search data with content data stored in a ternary content addressable memory (TCAM) unit, includes a first static logic gate for comparing a first content data with a first search data, and a second static logic gate coupled to the first static logic gate for comparing a second content data with a second search data. The content data comprises the first content data and the second content data and the search data comprises the first search data and the second search data. The first static logic gate forwards a signal for disabling the second static logic gate if the first content data does not match with the first search data.

Abstract: The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption. According to the present invention, since the binary content addressable memory according to the present invention has a smaller number of transistors than those of the conventional binary content addressable memory, a memory can be fabricated in a smaller size, thereby improving the degree of integration as one of most important factors in the memory design. In addition, improvement of the degree of integration contributes to miniaturization and lightweightness of the product in its design.

Abstract: A content addressable memory (CAM) may include a plurality of precharge circuits, each coupled to a group of CAM cells and comprising a first precharge path that is temporarily enabled in response to an activated first control signal, and a second precharge path that is temporarily enabled in response to an activated second control signal and a valid indication that indicates whether or not the corresponding group of CAM cells stores valid data, the valid indication being different than the first and second control signals.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.

Abstract: A content addressable memory (CAM) device includes an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line, a spare CAM row including a plurality of CAM cells coupled to a spare match line, and row replacement circuitry configured to functionally replace a defective CAM row and each subsequent CAM row in the array with corresponding next adjacent CAM rows, wherein a last CAM row in the array is functionally replaced by the spare CAM row.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular expression search operations. The compiler selectively converts the regular expression into a number of various bit groups, and the image loader loads corresponding bit groups into the CAM cells, into a number of memory elements that control configuration of the PRS, and into the counter circuits.

Abstract: A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.

Abstract: An apparatus and method of programming a search engine to implement regular expression search operations are disclosed that selectively transform a source regular expression into an equivalent reformulated regular expression in response to a determination of the architectural characteristics of the search engine. In this manner, the regular expression can be reformulated to optimize the configuration and available resources of the associated search engine.

Abstract: A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair.

Abstract: A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows.

Abstract: The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.

Abstract: A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.

Abstract: A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array.

Abstract: A dynamic, content addressable memory (CAM) cell includes a match line, a write line, a first pair of complementary bit lines for read and search operations, and a second pair of complementary bit lines for write operations; a first storage transistor connected between one of the first pair of complementary bit lines and the match line; a second storage transistor connected between the other of the first pair of complementary bit lines and the match line; a first write transistor connected between a gate of the first storage transistor and one of the second pair of complementary bit lines; and a second write transistor connected between a gate of the second storage transistor and the other of the second pair of complementary bit lines, with both the first and second write transistors having a gate connected to the write line.

Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Abstract: A scheme for ultra-low power content addressable memory based on a ripple search is disclosed. In one embodiment, a system for content addressable memory (CAM), includes a storage unit for storing a portion of content data, and a match module for comparing the portion of the content data with a respective portion of search data received by the match module. The match module includes a first static logic gate associated with a first half of the storage unit storing a sub-portion of the portion of the content data, and a second static logic gate associated with a second half of the storage unit. The first static logic gate forwards a signal for disabling the second static logic gate if the sub-portion of the portion of the content data does not match with a respective sub-portion of the portion of the search data.

Abstract: The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.

Abstract: The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

Abstract: A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result.

Abstract: A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract: A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value.

Abstract: A counter circuit is configured to simultaneously maintain individual character match count values for a plurality of overlapping substrings of an input string of characters that match a portion of a regular expression stored in a plurality of rows of content addressable memory (CAM) cells of a ternary CAM device. The counter circuit is selectable between a normal operational mode in which all matching portions of the input string are identified, and a minimum match length operational mode in which only matching portions of the input string that have at least a specified minimum number of characters are identified.

Abstract: An N-way mode CAM (content addressable memory) array includes M rows that each contain N subwords. Each of the N subwords has a respective mode cell. Additionally, a mode input bus is coupled to each mode cell of each of the N subwords, and a data input bus is coupled to each of the M rows. The mode input bus and the data input bus can uniquely identify as a match a single subword or a plurality of subwords in one of the M rows during a search operation. The N-way mode CAM further includes a row address encoder/generator coupled to each of the M rows, and an address output bus coupled to each of the row address encoder/generators. The mode input bus is also coupled to each of the row address encoder/generators. A uniquely identified single subword address may be outputted on the address output bus.

Abstract: A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows.

Abstract: A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.

Abstract: In a method for detecting patterns, a plurality of data patterns is stored in a memory, and a data block from a stream of data is received. A first subset of the data block is compared in parallel to the plurality of data patterns. A second subset of the data block is compared in parallel to the plurality of data patterns, wherein the second subset partially overlaps the first subset. At least one signal is generated that indicates a detected data pattern in the data block.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract: Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged according to a 2-dimensional priority scheme. Data words outside a selected 1×M column are masked to be ignored in determining a match, and the CAM is searched. Each search includes N compare cycles and each compare cycle having a different 1×M column selected. A highest priority match per compare cycle is pipelined from a priority encoder with the pipelined matches arranged to communicate a priority order in a first dimension of the 2-dimensional priority scheme.