Magnetic Cell Patents (Class 365/50)
  • Patent number: 10559357
    Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Lattice Semiconductor Corporation
    Inventor: Ronald L. Cline
  • Patent number: 10372359
    Abstract: The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 6, 2019
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 9818465
    Abstract: A self-referenced MRAM cell comprises a first portion of a magnetic tunnel junction including a storage layer; a second portion of the magnetic tunnel junction portion including a tunnel barrier layer, a sense layer and a seed layer; the seed layer comprising a material having high spin-orbit coupling such that passing a sense current along the plane of the sense layer and/or seed layer exerts a spin-orbit torque adapted for switching a sense magnetization of the sense layer. A memory device comprising a plurality of the MRAM cells and a method for operating the memory device are also disclosed.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 14, 2017
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Sebastien Bandiera
  • Patent number: 9437294
    Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 6, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Roberto Gastaldi
  • Patent number: 9368200
    Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: June 14, 2016
    Assignee: Unity Semiconductor Corporation
    Inventors: Bruce Lynn Bateman, Christophe Chevallier, Darrell Rinerson, Chang Hua Siau
  • Patent number: 8913423
    Abstract: An apparatus includes a memory cell including a magnetic tunnel junction (MTJ) structure coupled between a bit line and a source line. The MTJ structure includes a free layer coupled to the bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. A physical dimension of the pinned layer produces an unbalanced offset magnetic field which corresponds to a first switching current of the MTJ structure that enables switching from the first state to the second state when a first voltage is applied to the bit line and corresponds to a second switching current that enables switching from the second state to the first state when the first voltage is applied to the source line.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Seung H. Kang, Xiaochun Zhu
  • Patent number: 8908407
    Abstract: A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 9, 2014
    Assignee: Rambus Inc.
    Inventors: Brent Steven Haukness, Mark D. Kellam
  • Patent number: 8885379
    Abstract: The present disclosure concerns a self-referenced magnetic random access memory-based ternary content addressable memory (MRAM-based TCAM) cell comprising a first and second magnetic tunnel junction; a first and second conducting strap adapted to pass a heating current in the first and second magnetic tunnel junction, respectively; a conductive line electrically connecting the first and second magnetic tunnel junctions in series; a first current line for passing a first field current to selectively write a first write data to the first magnetic tunnel junction; and a second current line for passing a write current to selectively write a second write data to the second magnetic tunnel junction, such that three distinct cell logic states can be written in the MRAM-based TCAM cell.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: November 11, 2014
    Assignee: CROCUS Technology SA
    Inventors: Jeremy Alvarez-Herault, Yann Conraux, Lucien Lombard
  • Patent number: 8879307
    Abstract: A magnetoresistive device of an embodiment includes: first and second devices each including, a first magnetic layer having a changeable magnetization perpendicular to a film plane, a second magnetic layer having a fixed and perpendicular magnetization, and a nonmagnetic layer interposed between the first and second magnetic layers, the first and second devices being disposed in parallel on a first face of an interconnect layer; and a TMR device including a third magnetic layer having perpendicular magnetic anisotropy and having a changeable magnetization, a fourth magnetic layer having a fixed magnetization parallel to a film plane, and a tunnel barrier layer interposed between the third and fourth magnetic layers, the TMR device being disposed on a second face of the interconnect layer, and the third magnetic layer being magnetostatically coupled to the first magnetic layers of the first and second devices.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Naoharu Shimomura, Hiroaki Yoda, Junichi Ito, Minoru Amano, Chikayoshi Kamata, Keiko Abe
  • Patent number: 8767453
    Abstract: A magnetic device includes a magnetic layer having a variable direction of magnetization, and a first antiferromagnetic layer in contact with the magnetic layer, the first antiferromagnetic layer being able to trap the direction of magnetization of the magnetic layer. The magnetic device also includes a layer made of a ferromagnetic material in contact with the first antiferromagnetic layer through its face opposite to the magnetic layer, the directions of magnetization of the magnetic and ferromagnetic layers being substantially perpendicular. A first layer among the magnetic and ferromagnetic layers has a magnetization, the direction of which is oriented in the plane of the first layer whereas the second of the two layers among the magnetic and ferromagnetic layers has a magnetization, the direction of which is oriented outside of the plane of the second layer.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Bernard Dieny, Jérôme Moritz
  • Patent number: 8717794
    Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 6, 2014
    Assignee: Crocus Technology Inc.
    Inventors: Bertrand F. Cambou, Neal Berger, Mourad El Baraji
  • Patent number: 8681538
    Abstract: A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Inaba
  • Publication number: 20140071728
    Abstract: Voltage controlled magnetoelectric tunnel junction (MEJ) based content addressable memory is described which provides efficient high speed switching of MEJs toward eliminating any read disturbance of written data. Each cell of said CAM having two MEJs and transistor circuitry for performing a write at voltages of a first polarity, and reads at voltages of a second polarity. If the data searched does not equal the data written in the CAM, then the match line state is changed.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 13, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Pedram Khalili Amiri, Richard Dorrance, Dejan Markovic, Kang L. Wang
  • Patent number: 8644058
    Abstract: Provided are a spin-injection element having high spin-injection efficiency, and a magnetic field sensor and a magnetic recording memory employing the element. The element comprises a barrier layer, a magnetic conductive layer, and a spin accumulation portion comprised of non-magnetic conductive material. In the element, a first spin accumulation layer (103) and the barrier layer (102) have respectively a body-centered cubic lattice structure. Due to this, the first spin accumulation layer (103) and the barrier layer (102) come into contact with each other through a boundary face with improved crystalline symmetry. Thereby, lattice matching is improved and scattering of the tunnel electrons in the ?1 band is prevented, resulting in improvement in the spin polarizability. Further, the characteristics of the device employing the spin injection element are improved.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 4, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Masaki Yamada, Hiromasa Takahashi
  • Patent number: 8605479
    Abstract: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Cyrille Dray, Alexandre Ney, Karl Hofmann
  • Patent number: 8576601
    Abstract: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Tomoaki Inokuchi, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito, Atsuhiro Kinoshita, Kosuke Tatsumura
  • Publication number: 20130208523
    Abstract: The present disclosure concerns a self-referenced magnetic random access memory-based ternary content addressable memory (MRAM-based TCAM) cell comprising a first and second magnetic tunnel junction; a first and second conducting strap adapted to pass a heating current in the first and second magnetic tunnel junction, respectively; a conductive line electrically connecting the first and second magnetic tunnel junctions in series; a first current line for passing a first field current to selectively write a first write data to the first magnetic tunnel junction; and a second current line for passing a write current to selectively write a second write data to the second magnetic tunnel junction, such that three distinct cell logic states can be written in the MRAM-based TCAM cell.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 15, 2013
    Applicant: CROCUS TECHNOLOGY SA
    Inventor: CROCUS TECHNOLOGY SA
  • Patent number: 8400867
    Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
  • Patent number: 8289765
    Abstract: A magnetic random access memory (MRAM) cell with a thermally assisted writing procedure comprising a magnetic tunnel junction formed from a magnetic storage layer, a reference layer, and an insulating layer inserted between the reference layer and the storage layer; and a first strap portion laterally connecting one end of the magnetic tunnel junction to a first selection transistor; wherein the cell further comprises a second strap portion extending opposite to the first strap portion and connecting laterally said one end of the magnetic tunnel junction to a second selection transistor, and in that said first and second strap portions being adapted for passing a portion of current via the first and second selection transistors. The disclosed cell has lower power consumption than conventional MRAM cells.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: October 16, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Erwan Gapihan, Mourad El Baraji
  • Patent number: 8261367
    Abstract: Data, stored in MRAM-cells should be protected against misuse or read-out by unauthorized persons. The present invention provides an array of MRAM-cells provided with a security device for destroying data stored in the MRAM-cells when they are tampered with. This is achieved by placing a permanent magnet adjacent the MRAM-array in combination with a soft-magnetic flux-closing layer. As long as the soft-magnetic layer is present, the magnetic field lines from the permanent magnet are deviated and flow through this soft-magnetic layer. When somebody is tampering with the MRAM-array, e.g. by means of reverse engineering, and the flux-closing layer is removed, the flux is no longer deviated and affects the nearby MRAM-array, thus destroying the data stored in the MRAM-cells.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: September 4, 2012
    Assignee: Crocus Technology, Inc.
    Inventors: Kars-Michiel Hubert Lenssen, Robert Jochemsen
  • Publication number: 20120218802
    Abstract: One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 30, 2012
    Inventors: Takao MARUKAME, Tomoaki INOKUCHI, Hideyuki SUGIYAMA, Mizue ISHIKAWA, Yoshiaki SAITO, Atsuhiro KINOSHITA, Kosuke TATSUMURA
  • Patent number: 8238143
    Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and the magnesium (Mg) capping layer.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 7, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Xiaochun Zhu, Xia Li, Seung H. Kang
  • Patent number: 8228702
    Abstract: The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively connected to one extremity of the first and second straps; a first and second current lines; and a conductive line electrically connecting in series the first and second magnetic tunnel junctions at their ends opposed to the ones connecting the first and second straps. The cell disclosed herein has smaller size and can be advantageously used in memory devices having a high cell density array.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Mourad El Baraji
  • Patent number: 8228703
    Abstract: A method for writing a magnetic random access memory-based ternary content addressable memory cell comprising a first magnetic tunnel junction being formed from a storage layer, a sense layer having a magnetization direction adjustable relative to the magnetization of the storage layer, and an insulating layer between the storage and sense layers; a sense line coupled with the storage layer; a first field line and a second field line, and the first field line being orthogonal to the second field line; comprising: providing a first write data to said storage layer via the second field line to store a first stored data with a high or low logic state; characterized in that, the method further comprises providing the first write data to said storage layer via the first field line to store the first stored data with a masked logic state.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 24, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Mourad El Baraji
  • Patent number: 8138758
    Abstract: A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric field pulse to the ferromagnetic region so as to cause orientation of magnetic anisotropy to change for switching magnetisation between the first and second orientations.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 20, 2012
    Assignees: Hitachi, Ltd., Universite Paris Sud XI, Centre National de la Recherche Scientifique
    Inventors: Joerg Wunderlich, Tomas Jungwirth, Jan Zemen, Bryan Gallagher, Claude Chappert, Thibaut Devolder
  • Patent number: 8098541
    Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
  • Patent number: 7969768
    Abstract: A magnetic random access memory of an aspect of the present invention including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed and recording layers, wherein the magnetization directions of the fixed and recording layers are in a parallel state or in an anti-parallel state depending on a direction of a current flowing between the fixed and recording layers, a first transistor having a gate and a first current path having one end connected to the fixed layer, a second transistor having a gate and a second current path having one end connected to the recording layer, a first bit line to which other end of the first current path is connected, and a second bit line to which other end of the second current path is connected.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryousuke Takizawa, Kenji Tsuchida
  • Patent number: 7948783
    Abstract: An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: May 24, 2011
    Assignee: NEC Corporation
    Inventors: Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Nobuyuki Ishiwata, Shuichi Tahara
  • Patent number: 7940600
    Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 10, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
  • Patent number: 7898833
    Abstract: A magnetic element with thermally-assisted writing using a field or spin transfer provided, including a magnetic reference layer referred to as the “trapped layer,” the magnetization of which is in a fixed direction, and a magnetic storage layer called the “free layer” having a variable magnetization direction and consisting of a layer made of a ferromagnetic material with magnetization in the plane of the layer and magnetically coupled to a magnetization-trapping layer made of an antiferromagnetic material. A semiconductor or an insulating layer with confined-current-paths is sandwiched between the reference layer and the storage layer. At least one bilayer, consisting respectively of an amorphous or quasi-amorphous material and a material having the same structure or the same crystal lattice as the antiferromagnetic layer, is provided in the storage layer between ferromagnetic layer, which is in contact with the semiconductor or insulating layer with confined-current-paths, and antiferromagnetic layer.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: March 1, 2011
    Assignee: Commissariat A l' Energie Atomique
    Inventors: Lucian Prejbeanu, Cécile Maunoury, Bernard Dieny, Clarisse Ducruet, Ricardo Sousa
  • Patent number: 7894228
    Abstract: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: February 22, 2011
    Assignee: Crocus Technology S.A.
    Inventors: Jean-Pierre Nozieres, Virgile Javerliac
  • Publication number: 20110002151
    Abstract: The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively connected to one extremity of the first and second straps; a first and second current lines; and a conductive line electrically connecting in series the first and second magnetic tunnel junctions at their ends opposed to the ones connecting the first and second straps. The cell disclosed herein has smaller size and can be advantageously used in memory devices having a high cell density array.
    Type: Application
    Filed: June 23, 2010
    Publication date: January 6, 2011
    Applicant: CROCUS TECHNOLOGY SA
    Inventors: Virgile Javerliac, Mourad El Baraji
  • Patent number: 7864564
    Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideto Hidaka
  • Patent number: 7826260
    Abstract: A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell, the magnetic field rotates the magnetization orientation of the free magnetic layer without switching a resistance state of the magnetic tunnel junction data cell.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: November 2, 2010
    Assignee: Seagate Technology LLC
    Inventors: Wenzhong Zhu, Yiran Chen, Xiaobin Wang, Zheng Gao, Haiwen Xi, Dimitar V. Dimitrov
  • Patent number: 7791917
    Abstract: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: September 7, 2010
    Assignee: Crocus Technology S.A.
    Inventors: Jean-Pierre Nozieres, Virgile Javerliac
  • Patent number: 7751220
    Abstract: An associative memory device includes a magnetically responsive layer adapted to store a representation of a pattern, the magnetically responsive layer includes magnetic nanoparticles as a magnetically active component. The magnetic nanoparticles of the associative memory device are dispersed in a solvent with variable viscosity, and the magnetically responsive layer is a layer of ferrofluid.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: July 6, 2010
    Inventor: Vladislav Korenivski
  • Publication number: 20100110744
    Abstract: A method for writing a magnetic random access memory-based ternary content addressable memory cell comprising a first magnetic tunnel junction being formed from a storage layer, a sense layer having a magnetization direction adjustable relative to the magnetization of the storage layer, and an insulating layer between the storage and sense layers; a sense line coupled with the storage layer; a first field line and a second field line, and the first field line being orthogonal to the second field line; comprising: providing a first write data to said storage layer via the second field line to store a first stored data with a high or low logic state; characterized in that, the method further comprises providing the first write data to said storage layer via the first field line to store the first stored data with a masked logic state.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 6, 2010
    Applicant: CROCUS TECHNOLOGY SA
    Inventors: Mourad El Baraji, Virgile Javerliac
  • Patent number: 7712147
    Abstract: Data, stored in MRAM-cells (12) should be protected against misuse or read-out by unauthorised persons. The present invention provides an array (10) of MRAM-cells (12) provided with a security device (14) for destroying data stored in the MRAM-cells (12) when they are tampered with. This is achieved by placing a permanent magnet (16) adjacent the MRAM-array (10) in combination with a soft-magnetic flux-closing layer (18). As long as the soft-magnetic layer (18) is present, the magnetic field lines (20) from the permanent magnet (16) are deviated and flow through this soft-magnetic layer (18). When somebody is tampering with the MRAM-array (10), e.g. by means of reverse engineering, and the flux-closing layer (18) is removed, the flux is no longer deviated and affects the nearby MRAM-array (10), thus destroying the data stored in the MRAM-cells (12).
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: May 4, 2010
    Assignee: NXP B.V.
    Inventors: Kars-Michiel Hubert Lenssen, Robert Jochemsen
  • Patent number: 7646627
    Abstract: Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: January 12, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Hideto Hidaka
  • Publication number: 20090213632
    Abstract: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking.
    Type: Application
    Filed: April 13, 2009
    Publication date: August 27, 2009
    Inventors: Jean-Pierre Nozieres, Virgile Javerliac
  • Publication number: 20090109719
    Abstract: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking.
    Type: Application
    Filed: January 5, 2009
    Publication date: April 30, 2009
    Inventors: Jean-Pierre Nozieres, Virgile Javerliac
  • Patent number: 7518897
    Abstract: A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: April 14, 2009
    Assignee: Crocus Technology S.A.
    Inventors: Jean-Pierre Nozieres, Virgile Javerliac
  • Patent number: 7518907
    Abstract: A magnetoresistive element includes a first ferromagnetic layer having a first magnetization, the first magnetization having a first pattern when the magnetoresistive element is half-selected during a first data write, a second pattern when the magnetoresistive element is selected during a second data write, and a third pattern of residual magnetization, the first pattern being different from the second and third pattern, a second ferromagnetic layer having a second magnetization, and a nonmagnetic layer arranged between the first ferromagnetic layer and the second ferromagnetic layer and having a tunnel conductance changing dependent on a relative angle between the first magnetization and the second magnetization.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: April 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Nakayama, Tadashi Kai, Tatsuya Kishi, Yoshiaki Fukuzumi, Toshihiko Nagase, Sumio Ikegawa, Hiroaki Yoda
  • Patent number: 7499303
    Abstract: A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: March 3, 2009
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Shih-Ked Lee
  • Patent number: 7487290
    Abstract: Where realtime performance-critical processing is executed in parallel with data integrity-critical processing, embodiments of the invention improve the realtime performance by raising the data transfer efficiency for sequential access-dominant realtime processing. In one embodiment, if a non-realtime processing command is received while read-ahead is in progress for a realtime processing command, processing of the non-realtime processing command is not started until a certain amount of data is cached. In addition, in order to prevent the periodicity disturbance of realtime processing, when the processing of the non-realtime processing command is postponed, the read-ahead is continued maximally until the timestamp at which the next realtime processing command is expected to be issued.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: February 3, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Yukie Hiratsuka, Manabu Nishikawa
  • Patent number: 7471551
    Abstract: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When the element size is made small so as to improve the integration degree of the magnetic memory, according to the scaling law, the writing current can be made small. In the present invention, the resistance to the spin injection magnetization reversal due to a reading current is high, so that the magnitude of the writing current can be lowered.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: December 30, 2008
    Assignee: TDK Corporation
    Inventor: Tohru Oikawa
  • Patent number: 7460382
    Abstract: A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates the processor information to another semiconductor die. Control logic controls the device interface.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: December 2, 2008
    Assignee: Marvell International Ltd.
    Inventor: Masayuki Urabe
  • Publication number: 20080285323
    Abstract: The present invention provides an associative memory device based on a ferromagnetic nano-colloid, or ferrofluid. The design comprises inductive input and output units for training the ferrofluid as well as sensors incorporated into the output units for performing recall.
    Type: Application
    Filed: October 27, 2006
    Publication date: November 20, 2008
    Inventor: Vladislav Korenivski
  • Patent number: 7423902
    Abstract: A storage device includes memory cells disposed in a matrix. The memory cells each include a storage element whose resistance changes from a higher state to a lower state when an electric signal of a first threshold level or higher is applied and whose resistance changes from the lower state to the higher state when an electric signal of a second threshold level or higher whose polarity is different from the polarity of the electric signal of the first threshold level or higher is applied, and a circuit element connected in series with the storage element. In a state in which an erasing voltage is applied to at least one memory cell on which erasing is currently being performed, after the lapse of a predetermined time from the application, an erasing voltage is applied to at least one memory cell on which erasing is to be next performed.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: September 9, 2008
    Assignee: Sony Corporation
    Inventors: Hironobu Mori, Hidenari Hachino, Nobumichi Okazaki
  • Patent number: 7406561
    Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: July 29, 2008
    Inventor: Madian Somasundaram