Abstract: According to one embodiment, a semiconductor memory device includes a plurality of global bit lines, a plurality of word lines, a plurality of bit lines, a plurality of resistance change films, a plurality of semiconductor layers, a gate insulating film, and a plurality of gate electrodes. Spacing in the first direction between the plurality of semiconductor layers is larger than spacing in the second direction between the plurality of semiconductor layers. The plurality of gate electrodes is separated in the first direction.

Abstract: A memory device responding to device commands for operational controls. An embodiment of memory device includes one or more memory elements, a system element including a memory controller, and a physical interface including command input pins to receive commands for the memory device. The commands include commands for operational controls for the memory device, including one or both of a first command for a reset control to reset the memory device and a second command for a clock enable (CKE) control to halt internal clock distribution for the memory device.

Abstract: According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit changing a condition of initialization of each of non-completed elements in which the initialization is not completed among the resistance change elements based on a number of completed elements in which the initialization is completed among the resistance change elements.

Abstract: A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.

Abstract: A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

Abstract: A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.

Abstract: A provided memory device is compatible with a mono-rank or multi-ranks. A plurality of memory layers are stacked in the memory device. The memory device receives an address signal and chip select signals in response to a chip identification signal and a mode signal used to determine a mono-rank or multi-ranks. The plurality of memory layers operate as the mono-rank accessed by the address signal, or operate as the multi-ranks accessed by the chip select signals.

Abstract: Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.

Abstract: A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are electrically connected to control gates of the memory cells. A plurality of bit lines are electrically connected to one end of a current path of the memory cells. A sense amplifier part detects data stored in the selected memory cells. A power supply part converts an external power supply voltage to an internal power supply voltage and supplies the internal power supply voltage to the sense amplifier part. A power supply wire extends above the memory cell array and is provided to range from the power supply part to the sense amplifier part.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract: A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N1i of the first chip and the node N2i of the second chip, wherein 1?i?n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.

Abstract: A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.

Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.

Abstract: A semiconductor device includes a first set of stacked structures including alternately stacked insulating layers and conductive layers disposed on a substrate, and arranged in a generally parallel configuration with respect to each other, a second set of stacked structures including alternately stacked insulating layers and conductive layers disposed on the substrate between the first stacked structures, and arranged in a generally parallel configuration with respect to each other, a first wiring structure configured to electrically couple conductive layers located on the same layer in different stacked structures of the first set of stacked structures, a second wiring structure configured to electrically couple conductive layers located on the same layer in different stacked structures of the second set of stacked structures, and a third wiring structure configured to electrically couple the first wiring structure and the second wiring structure with an operation circuit.

Abstract: A process of forming a through-silicon via (TSV) in a die includes forming a movable member in the TSV that can be actuated or that can be a sensor. Action of the movable member in the TSV can result in a logic word being sent from the TSV die to a subsequent die. The TSV die may be embedded in a substrate. The TSV die may also be coupled to a subsequent die.

Abstract: A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.

Abstract: A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel.

Abstract: A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

Abstract: Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.

Abstract: A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.

Abstract: A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

Abstract: A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit.

Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.

Abstract: The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a voltage-generator die. The 3D-array die comprises a plurality of vertical memory strings. At least a voltage-generator component for the 3D-array die is located on the voltage-generator die instead of the 3D-array die. The 3D-array die and the voltage-generator die have substantially different back-end-of-line (BEOL) structures.

Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines through the multiple layers of planes. The pillar lines are of a first type that act as local bit lines and a second type that provide access to the word lines by having respective memory elements preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.

Abstract: Storage apparatus (20) includes a memory (30) and an encryption processor (28), which is configured to receive and encrypt data transmitted from one or more computers (24) for storage in the memory. A one-way link (32) couples the encryption processor to the memory so as to enable the encryption processor to write the encrypted data to the memory but not to read from the memory.

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.

Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.

Abstract: Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.

Abstract: A semiconductor device includes a plurality of cylindrical structures located at vertices and central points of a plurality of hexagons in a honeycomb pattern, and a unitary support having a plurality of openings. Each of the openings exposes a part each of four of the cylindrical structures. Each of the openings has the shape of a parallelogram or an oval substantially. A first distance between opposite cylindrical structures of a first pair of the four cylindrical structures exposed by each opening is shorter than a second distance between opposite cylindrical structures of a second pair of the four cylindrical structures exposed by the opening. The first distance is equal to a distance between the central point and each of the vertices of the hexagon.

Abstract: Embodiments relate to systems and methods for simplified addressing of a memory device whose total memory capacity is extendible by an additional memory capacity or a factor to a total extended memory capacity, the method comprising dividing the additional memory capacity into a set of binary memory fractions of the total memory capacity such that a sum of all binary memory fractions equals the additional memory capacity, and addressing each one of the binary memory fractions by a binary based addressing scheme.

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: The present disclosure provides a method for manufacturing a three-dimensional semiconductor memory device. In the method, a storage array is divided into a plurality of storage sub-arrays. As a result, a respective via of each storage sub-array can be etched respectively, which is different from the prior art, where a via for a bottom electrode of a plurality of layers of resistive cells is etched at one time. The vias are filled with metal so that storage sub-arrays are connected with each other. The method for manufacturing the three-dimensional semiconductor memory device according to the present disclosure can substantially reduce process complexity and difficulty of etching process in high-density integration, and also improve a number of layers of the resistive cells integrated in the storage array.

Abstract: According to one embodiment, a resistance change memory includes a first memory cell, a word line, a first bit line, first and second inverters, first to sixth MOS transistors, and a control circuit. The first transistor is connected to the first output terminal of the first inverter. The second transistor is connected to the second output terminal of the second inverter. The fifth transistor has a first current path whose one end is connected to the first voltage terminal of the first inverter. The sixth transistor has a second current path whose one end is connected to the third voltage terminal of the second inverter. The control circuit makes the first and second transistors a cutoff state by a first signal and makes the fifth and sixth transistors the cutoff state by a second signal in a standby state.

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract: A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described.

Abstract: Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Abstract: A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.

Abstract: A semiconductor memory apparatus includes a first chip including a refresh signal generation unit which is configured to receive an external command and generate a refresh signal; and a second chip including a first delay unit which is configured to receive the refresh signal through a first through-silicon via and delay the received refresh signal, a first selection unit which is configured to output an output signal of the first delay unit to the first chip through a second through-silicon via in response to a first select signal, and a first core region which is configured to receive the output signal of the first delay unit and perform a refresh operation.

Abstract: A method and system of analyzing a network to identify a network defect allows user selection of traffic subset to be recorded. After recording the selected traffic subset of the network traffic during network operation, the recorded traffic is then replayed at least in part to the network to replicate, and thus assist in identifying, the network defect.

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Abstract: An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality of microstructures define a detectable first state if they are not bent such that end portions thereof, which are distal with respect to the support, do not touch each other, and the two adjacent microstructures of the plurality of microstructures define a detectable second state if they are bent such that the end portions thereof, which are distal with respect to the support, touch each other and are fixed to each other.

Abstract: A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.

Abstract: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract: A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged.