Abstract: In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.

Abstract: A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmission element to provide access to the data stored in the data store element. Each memory cell has the dual function of storing and transmitting (i.e. shifting) data. The memory cell array is coupled to first and second registers and a shuffle signal generator. In operation, data is shuffled column by column through the array, such that only two columns of memory cells are activated at any time. The shuffle memory herein disclosed may form subarrays of each of a data storage array and a redundancy storage array that are coupled to an improved error detector and corrector to form a high performance fault tolerant orthogonal memory system.

Abstract: A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.

Abstract: In order to reduce the down time of a computer (1, 4-8) caused by a fault or interrupt in the program run, program recovery points are provided which are time-dependent or can be preset in the main program of a useful program, and when these recovery points are reached, the computer status is stored in at least one fault-tolerant archival memory (5, 6). The computer status includes the status of the variables of a useful program being executed, the register status of the processor (1) and the register status of the input/output devices of the computer. During execution of the useful program, at least a part of the current computer status is stored in a main memory (4) and copied into an archival memory (6) when a program recovery point is reached.

Abstract: A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is grouped to form a fixed recirculation path. The word length can be varied by modifying stored data in the shift register without changing its recirculation path.

Abstract: A FIFO memory system organizes a memory with N word storage locations into M pointer-based random access memories, each containing N/M storage locations. A sequence of data words is written into and read out of the M RAMs in a cyclical fashion. An M fold increase in write rate is obtained by an input control logic which causes all M RAMs to be in a different stage of the shift-in cycle at the same time. Similarly, an M fold increase in read rate is obtained by an output control logic which causes all M RAMs to be simultaneously in a different stage of the shift-out cycle. The output signals of the RAMs being read are multiplexed to generate the original sequence.

Abstract: The invention relates to a shift register structure and its control. The positioning and/or synchronization of data contained in this register for the purpose of serial operation are essentially obtained by acquisition of data on at least one auxiliary output SA1 of this register R. In particular the invention enables a programmable delay buffer register to be produced very simply.

Abstract: A data storage system for storing multilevel, non-binary data includes a charge coupled device (CCD) shift register and a detection circuit for detecting the data level represented by the charge or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known data level. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause the output of an incrementing digital-to-analog converter to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which controls the switching transistors. The outputs of the sense amplifier and flip-flop are connected to an EXCLUSIVE NOR gate, whose output enables an up/down counter, which in turn provides the detected data level.

Abstract: A data storage system having a charge coupled device (CCD) shift register and a detection circuit for detecting the binary value represented by the charge level or signal within each cell location of the CCD shift register. The detection circuit includes a sense amplifier for comparing the signals from two adjacent cell locations, with one signal representing a known binary value. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors cause an adjustment voltage to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop, which in turn has an output initially set at the known binary value and which controls the switching transistors.

Abstract: A memory system includes means for injecting a multivalued signal with at least three information carrying voltage levels, in the form of electric charge, to a charge coupled device (CCD); and a detection means for detecting a multivalued signal level read out from the output terminal of CCD and feeding the voltage of the level back to the injecting means. The detection means comprises a level detection section for generating a combination of outputs predetermined correspondingly to the multivalued signal level and an output section for generating upon receipt of the combination of outputs an output having a voltage level corresponding to the combination of outputs.