Abstract: Methods, systems, and devices for address verification for a memory device are described. When a memory device receives a write command, the memory device may store, in association with the data written, an indication of a write address associated with the write command. When the memory device receives a read command, the memory device may retrieve data and a previously stored write address associated with the retrieved data, and the memory device may verify a read address associated with the read command against the previously stored write address associated with retrieved data. Thus, for example, the memory device may verify whether data read from the memory array based on an address associated with a read command is data that, when previously written to the memory array, was written in response to a write command associated with a matching address.

Abstract: A data storage method includes: acquiring target data to be stored, and classifying refresh rates of the target data to be stored according to a front-end system; subjecting the target data to be stored with high refresh rates as classified and the target data to be stored with low refresh rates as classified to a Hash calculation to obtain a first type Hash value and a second type Hash value; determining storage data segments corresponding to the first type Hash value and the second type Hash value according to a preset storage data segment determination relationship, and storing the target data to be stored with high refresh rates and the target data to be stored with low refresh rates into the storage data segments corresponding to the first type Hash value and the second type Hash value, respectively.

Abstract: Provided is a radio transmission device, a baseband processing device, a radio transmission method, and a radio reception device that can reduce the peak to average power ratio in multiplex transmission using the OAM transmission system. In a baseband processing device (10), a signal formation unit (11) forms N number of multiplex signals corresponding to N number of antenna devices (32) by multiplying M number (M is a natural number equal to or larger than 2) of data symbols that are different from and parallel to each other by a “corrected weighting matrix”. The “corrected weighting matrix” is obtained by adding the phase rotation matrix for suppressing the peak to a fixed OAM basic weighting matrix.

Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The backlog counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.

Abstract: The present invention is directed to a method for programming a memory cell that includes a two-terminal selector and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.

Abstract: An apparatus comprising a signal generator configured to produce a modulation signal, a filter coupled to the signal generator and configured to filter the modulation signal to produce a cancellation signal, and a reflective semiconductor optical amplifier (RSOA) coupled to the signal generator and the filter, wherein the RSOA is configured to generate an optical signal according to a difference between the modulation signal and the cancellation signal and transmit the optical signal towards a partial reflection mirror (PRM).

Abstract: A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

Abstract: Embodiments disclosed herein generally relate for efficiently retrieving boot code for a processor from serial NOR flash memory. When a boot code request is received, a request handler in data capture logic tags successive address read requests to indicate whether the requests indicate contiguous addresses in the NOR flash memory for the boot code. Different circuitry in the data capture logic operates on different mesochronous clock signals. One clock signal drives the capture of boot code from NOR flash, and the other controls synchronized tagging, storing, pre-fetching, and transmitting of the captured boot code data.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A first copier acquires data and determines a plurality of recipients to deliver split data. A data splitter 308 splits data into a plurality of data blocks and a dummy data generator 315 generates dummy data. A data delivery unit 310 delivers the data blocks and dummy data to the plurality of recipients. At the same time, the data delivery unit 310 outputs restoration information including information about the recipients of the data. Based on the restoration information, a second copier collects the plurality of data blocks and the dummy data from the plurality of recipients and discards the dummy data, acquiring the plurality of data blocks. The second copier reconstructs a set of data from the plurality of data blocks.

Abstract: In some embodiments, a method, apparatus and system for n-dimensional sparse memory using serial optical memory are presented. In this regard, a memory device is introduced to circulate a signal among a plurality of optical emitters and receivers. Other embodiments are also disclosed and claimed.

Abstract: In some embodiments, a method, apparatus and system for global shared memory using serial optical memory are presented. In this regard, a memory device is introduced to circulate a signal among a plurality of optical emitters and receivers. Other embodiments are also disclosed and claimed.

Abstract: A device and method for block transmission include a storage configured to store at least one transmission matrix relating to a set of symbols, and a processor configured to process at least part of the at least one transmission matrix to symbols forming at least a subset of the set of symbols for forming processed symbols. The device and method further include a generator configured to generate at least one transmission signal based on the processed symbols. The at least one transmission matrix is a direct product of a first matrix and a second matrix. The second matrix is different from an identity matrix. A size of each of the second matrix and the first matrix being at least two times two. At least one entry of the first matrix having a complex value.

Abstract: A digital memory matrix having memory cells in rows and columns, addressing of the memory cells is accomplished by control devices which perform arbitrary jumps of address, thereby avoiding addressing on adjacent lines. The jump increment is selectable. The control devices are control chains, two of which are provided, and the outputs of the control chains are connected to linking elements that in turn are connected to the memory lines. The linking elements are provided in groups.

Abstract: The present invention discloses an electronic memory system having semipermanent memory storage, a memory device for rapid data transfer and temporary memory storage, and controller for monitoring and controlling writes to the semipermanent memory storage.

Abstract: A method and apparatus for estimating the frequency of a periodic signal and for canceling the interference in a modem signal. Power line noise may interfere with electronic signals. Since power lines may be either 50 Hz or 60 Hz, depending on the country, frequency estimation of the periodic power line noise is necessary. Modem signals are received and autocorrelated in order to identify the periodic characteristics of the signal over time. Once the frequency is identified, the power line noise is modeled based on creating a circular buffer. Initially, the circular buffer is composed of scaled samples of one cycle of the fundamental frequency of the power line noise. Thereafter, samples are received, scaled, and combined with previous buffer values in order to update the buffer. In this manner, the buffer models the power line noise, so that the power line noise may be removed from the system.

Abstract: According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an enabling signal that enables access to a certain number of bits at a time. By operating together, the shift registers enable simultaneous access to a multiple of that number of bits. This multiple can be varied to design serial access memories with different word widths. According to another aspect of the invention, there need be only one shift register, but its stages are interleaved. The enabling signal is shifted from a first end of the shift register to a second end, skipping every other stage, then shifted back from the second end to the first end through the stages that were skipped. This operation is repeated cyclically.

Abstract: A FIFO memory eliminates the delay associated with selecting memory locations during a read and write operation and prevents data intended to be saved from changing during the write operation. The FIFO memory includes a shift register having a plurality of memory locations, data input and data output terminals coupled to the memory, a first memory location coupled to the data output terminal that is immediately output enabled in response to a read operation, and a single pointer arrangement coupled to the memory locations for selectively saving data contents in successive memory locations coincidentally with the occurrence of successive write operations.

Abstract: A non-volatile analog memory contains multiple recording pipelines for sampling and storing values representing an analog signal and/or multiple playback pipelines for playing a recorded signal. Each recording pipeline includes a sample-and-hold circuit and a write circuit coupled to a memory array associated with that pipeline and is capable of write operations that overlap write operations of other recording pipelines. Each playback pipeline includes a read circuit and a sample-and-hold circuit coupled to an associated memory array and is capable of read operations that overlap read operations of other playback pipelines. The pipelines operate sequentially during recording or playback, and the number of pipelines is selected according to a desired sampling frequency. One embodiment provides a modular integrated circuit architecture which allows a user selected number of ICs to be connected together to handle a desired sampling frequency.

Abstract: A semiconductor memory device for serially outputting previously loaded data from an integral memory is disclosed herein. The device is configured to output head data from a predetermined location in the memory by latching the head data directly from a common bus. In a preferred embodiment the head data is latched by a single latch circuit. In a method of the invention, the head data is transferred directly from a predetermined memory address onto a common bus. A latch circuit then latches the head data from the common bus. The latched head data is next presented to an output buffer. Thereafter, data is presented in a serial form from a plurality of serial registers to the output buffer.

Abstract: A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: An information reproducing apparatus for reproducing recorded data includes a buffer, a control device and a determining device. The buffer stores data blocks read out from a recording medium and includes first and second storage areas having respectively discontinuous storing and read addresses. The apparatus is controlled to execute in parallel a first process for storing the data blocks into the buffer and a second process for reading out the data blocks stored in the buffer to transfer the data blocks to a host apparatus. The determining device determines whether there are data in the first storage area to be transferred to the host apparatus by comparing a storing address in the buffer of the data which are being stored into the first storage area with a read address in the buffer of the data which are being read out from the first storage area. The first process is controlled so that a predetermined data block which has been read out from the recording medium is stored into the second storage area.

Abstract: A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of linear CCD arrays which store data as electrical charges, allows high speed memory access by reading and writing data through cache memory which stores row addresses corresponding to CCD arrays, and includes an address register for registering the address of cache memory data.

Abstract: A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A first pair of circular shift registers are used to control writing data to and reading data from the FIFO. The outputs of each register in each shift register are coupled to enable individual read and write lines of a FIFO memory device. A single logical one value circulates through the shift registers to indicate a FIFO location where data may be written to or from. Toggle latches are coupled to each shift register. The values in the toggle registers change responsive to a read or write operation. By comparing the logical one values in the corresponding positions in the shift registers, and considering the values from the toggle latches, EMPTY and FULL conditions are detected.

Abstract: A selectable width, burstable FIFO is described. A register memory stores x-bit and y-bit data. Each register of the register memory is y+1 bits wide. Y bits store x-bit and y-bit data and 1-bit tracks the data width within each register. A Burst Ready Logic means accepts an m-bit input to select a burst length from 2.sup.m possible burst lengths. Based on the m-bit input, the Burst Ready Logic outputs a signal indicating when the FIFO is burstable. The empty and full FIFO conditions are determined using a digital hysteresis. In one embodiment, the FIFO is used in an IBM-AT environment. Eight registers store 8-bit and 16-bit data. Each register is 17-bits wide so that 16-bits store 8-bit and 16-bit data. The remaining bit tracks whether the register contains 8-bit or 16-bit data. In this embodiment, the Burst Ready Logic accepts a 2-bit input to select from possible burst lengths of 1, 2, 4 or 8 bytes.

Abstract: A system and method are described for enforcing the validity of circulating pointers stored in a pointer FIFO (first-in-first-out) memory. One or more target pointers are generated and compared to circulating pointers. If a pointer does not circulate through the system within a pre-specified time, then a pointer has been lost and an error is reported. If a circulating pointer matches a target pointer, it is suppressed by being removed from the set of circulating pointers. Another timer is then set to determine whether further circulating pointers match a target pointer. If so, then multiple pointers to the same location are present and all duplicate pointers are suppressed. After expiration of the second time, the target pointers are added to the set of circulation pointers. This process repeats with new target pointers, so that the validity of the set of circulating pointers is verified.

Abstract: A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A read address ring counter (36) and write address ring counter (32) are responsive to respective read and write pulses to sequentially perform memory read and write operations. A comparator (40) compares the address outputs of the ring counters (36, 32) for equality. A read and a write signal generator (80, 60) are provided for producing respective read and write pulses in response to input transitions of read and write commands. A last operation R/W flip-flop (70) maintains an account of the last read and write memory operation processed by the system.

Abstract: A memory device having an addressing unit for addressing different values as addresses for input/output of data for each clock input during one cycle, and a memory inputting data at different designated addresses and cyclically outputting stored data. The memory device provides the operation of a shift register which is capable of determining the number of stages in accordance with the content of the addressing. By employing a memory which effects read-modify-write operations and by delivering input data obtained by the feedback of output data to this memory, the memory device can repeatedly output the same data. The memory device has a switch circuit operative in a first position for connecting an output of the memory to an input of the memory and in a second position for connecting the input of the memory to an external data source.

Abstract: There is provided method and apparatus for recording a waveform. By counting the intervals of change points of a recorded waveform and recording the count data, the waveform can be recorded for a long time.

Abstract: Information concerning the access to a first-in first-out buffer memory for reading and writing operations is indicated by the use of two supplemental memories which provide availability and validity information based upon unoccupied location information indicating a buffer memory location where data has been read, valid occupied location information indicating a buffer memory location where data has not yet been read, and non-valid occupied location information indicating that the location in the buffer memory has been overwritten. For each character stored in the buffer memory, there is a corresponding bit in the respective supplemental memories. The value of the bits in the respective memories indicates the availability of the memory and whether an overwrite will occur. The information contained in the supplemental memories is updated by a writing operation depending upon the availability status of the buffer memory at the time of writing.

Abstract: An arrangement of data cells which stores at least one matrix of data words which are arranged in rows and columns, the matrix being distributed in the arrangement in order to deliver/receive, via a single bus, permuted data words which correspond either to a row or to a column of the matrix. Each data cell is connected to the single bus via series-connected switches which are associated with a respective addressing mode, the switches which address a same word of a same mode being directly controlled by a same selection signal. Circulation members enable the original order of the data on the bus to be restored. An arrangement of this kind is used in a layered neural network system for executing the error backpropagation algorithm.

Abstract: A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a serial data register which includes a number of bit cells corresponding to one word of the memory cell array, a decoder for decoding an address signal and for successively making an access to each bit cell of the serial data register based on a decoded result, a register group comprising m+1 shift registers in correspondence with each digit of the address signal, where each of the shift registers comprise n registers which are connected to form a loop and m and n are integers satisfying m.gtoreq.

Abstract: An optical flip-flop circuit which includes an electrical power source for providing an electrical signal, a light-receiving element provided in series with the power source for switching the electrical signal in response to an optical signal, a light-emitting element for emitting the optical signal in response to the electric signal, an electrical signal path between the light-receiving element and the light-emitting element, whereby the electrical signal passes from the power source to the light-emitting element in response to the optical signal received by the light-receiving element, a light path for directing the optical signal from the light-emitting element to the light-receiving element, wherein the light path and the electrical signal path form a signal loop through which a signal circulates, said circulating signal comprising the electrical signal through the electrical signal path portion of the signal loop and the optical signal through the light path portion of the signal loop, and input/output m

Abstract: Forming the shift register as a plurality of memory locations in a memory array where the input port for writing into the memory and the output port for reading out of the memory are sequenced along the array. Thus the input and output ports are shifted with respect to the array instead of the information shifting with respect to fixed input and output ports. The length or number stages of the shift register may be varied by changing the displacement or offset of the output or reading port to the input or writing port in the sequence.

Abstract: An arrangement of data cells which stores at least one matrix of data words which are arranged in rows and columns, the matrix being distributed in the arrangement in order to deliver/receive, via a single bus, permuted data words which correspond either to a row or to a column of the matrix. Each data cell is connected to the single bus via series-connected switches which are associated with a respective addressing mode, the switches which address a same word of a same mode being directly controlled by a same selection signal.Circulation members enable the original order of the data on the bus to be restored. An arrangement of this kind is used in a layered neural network system for executing the error backpropagation algorithm.Application: Calculator, microprocessors, processor, neural network system.Reference: FIG. 4.

Abstract: A scan-register having first and second data input ports (SYS.sub.-- DATA, SCAN.sub.-- IN), a data output port, and inputs for at least first, second, third, and fourth control signals (SYS.sub.-- CLK, M.sub.-- LOAD, CLK.sub.-- B, CLK.sub.-- A).

Abstract: An optical memory cell constructed from an optical combiner, a 1.times.2 optical swtich and optical fibers. One input port of the optical combiner serves as the input to the memory cell. The output port of the optical combiner is connected to the input of the optical switch by an optical fiber. A first output port of said switch is connected by an optical fiber to the second input of the optical combiner, such that when said switch is in the straight-through state, an optical loop is formed through which an optical pulse can circulate. The second output of the optical switch serves as the output of the memory cell when said optical switch is in the cross-over state. Control signals are provided by a clock.

Abstract: An expandable first-in-first-out FIFO circuit is provided for storing data words in a plurality of data cells in response to a digital position control signal generated by a plurality of control cells such that the oldest data word is always present at the output data bus. The data cells are arranged in pairs for data transferring therebetween whereby the data words are placed in the upper and lower data cells of each pair before allocating data cells farther from the input data bus. The digital position control signal is represented as a first portion having a first logic state and a second portion having a second logic state, the boundary of which determines the occupied portion of the data cells which provides control of the movement of data words therein. The FIFO circuit is expandable without modification of the preexisting data cells or control cells simply by adding data cell pairs and associated control cells.

Abstract: A serial access memory device with the improved cascade buffer circuit for controlling serial access operation which has a small number of external terminals is disclosed. The cascade buffer circuit includes first and second external terminals, a first control circuit for enabling the memory device to perform write operation and read operation when the level at the first external terminal rises or falls and when the level at the first external terminal falls or rises, respectively and a second control circuit for operatively causing the second external terminal to rise or fall when the memory device completes write operation and causing the second external terminal to fall or rise when the memory device completes read operation, respectively.

Abstract: A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respectively, which are controlled by a basic clock signal (g1) and further signals. Thus FIFO memory makes it possible to pass an input data stream arriving at an input data rate (g2) through the FIFO memory in such a way that the output data stream appears at the output (da) at an output data rate (g3) momentarily different from the input data rate (g2). On a time average, however, the two data rates are equal, so that data can be written into and read from the FIFO memory simultaneously at different rates.

Abstract: A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is grouped to form a fixed recirculation path. The word length can be varied by modifying stored data in the shift register without changing its recirculation path.

Abstract: A memory matrix for storing control words for controlling a common control time division multiplexed (TDM) switch is formed by employing a plurality of shift registers connected in recirculating configuration. Synchronization of control word time slots in the memory matrix to system timing is realized by storing a timing marker which is advanced in identical manner as the control word time slots. If synchronization between the system timing and control word time slots is interrupted, it is restored by controllably inhibiting advancing of the control word time slots and the stored timing marker.

Abstract: A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled to a bypass bus. Data is introduced on the bypass bus, and control logic writes the data into the section nearest the output which is currently not full. The individual register stages are self-clocked, so that data is then shifted toward the output through any vacant registers. In another aspect, the register stages are arranged in sections of different length, with the shortes section closest to the output and the longest section closest to the input. Decreased fall-through delay is achieved by minimizing the length of the FIFO buffer actually traversed by the data while insuring that the order of the data remains unchanged.

Abstract: An improved NMOS storage cell for use in shift registers is disclosed. Among other components, it contains a pair of inverters--one them an enabling inverter. A pre-charge transistor is placed in parallel with the first inverter to decrease the rise time associated with the transition from a logic low level output to a logic high level output. The result of adding the pre-charge transistor to the circuit is to increase the speed of operation of the storage cell, without the accompanying decrease in density with prior art methods, where the components must be enlarged. Another aspect of the present invention which further increases the density of the cell is the elimination of the complement clock line found in many prior art storage cells. The previous combination of a second inverter and a pass transistor connected to a complement clock line, is replaced by an enabling inverter connected to the clock line.

Abstract: A fiber optic recirculating memory comprises a splice-free length of optical fiber which forms a loop that is optically closed by means of a fiber optic coupler. The coupler couples an optical signal input pulse to the loop for circulation therein, and outputs a portion of the signal pulse on each circulation to provide a series of output pulses. A pump source is included to pump the fiber loop with a pump signal having sufficient intensity to cause stimulated Raman scattering in the fiber loop, and thereby cause amplification of the circulating signal pulse. The fiber characteristics, coupler characteristics, and pump power are selected to yield a Raman gain which compensates for the total round-trip losses in the fiber loop, so as to provide an output pulse train of constant amplitude pulses. The invention may be implemented utilizing either a standard coupler or a multiplexing coupler.

Abstract: An integrated memory circuit includes a memory loop which comprises two gates which are controlled by a clock signal. The circuit is susceptible to a race condition so that correct operation cannot always be ensured. The "race" problem is solved by choosing the switching thresholds of the gate inputs receiving the clock signal so that the gates respond successively instead of (sustantially) simultaneously to the clock signal. The correct switching sequence of the gates and the correct operation of the memory circuit can thus be ensured.

Abstract: A circuit arrangement for controlling the read-out of stored information composed of first and second random access memories each having a plurality of addressable memory locations having a preferred order of write-in, an address input, an information input, and an information output, a first signal source connected to the information input of the second memory for writing information values into the memory locations of the second memory in the preferred write-in order, a second signal source connected to the information input of the first memory for writing into the memory locations of the first memory signals representing respective addresses of the second memory, and signal conducting device connected between the information output of the first memory and the address input of the second memory for delivering address signals to the second memory derived from values stored in successive memory locations of the first memory.

Abstract: A circuit has a logic memory, a preceding logic circuit, a succeeding logic circuit, and a function defining circuit. An input signal is taken by the preceding logic circuit, where a new logic state is produced based on the input signal and a present logic state in the logic memory executing a defined calculation. The content of the logic memory is taken over by the new logic state. The succeeding logic circuit produces an output signal based on the logic state of the logic memory executing a defined calculation. The calculation executed in the succeeding or preceding logic circuit is defined by the defining function circuit. Thus, the whole circuit operates with a desired function.

Abstract: A variable digital delay circuit is disclosed which utilizes a shift register to periodically sample a signal to be delayed and after a predetermined number of samples are collected as a group of zeros and ones making up a binary word the word is stored in parallel in a memory. After each binary word is stored in a memory a binary word previously stored in the memory is read out into a buffer store from which each individual bit is sequentially read out using a multiplexer at the same rate that the bits were originally taken to thereby recreate the original signal samples. The time delay is determined by how long the previously stored binary word being read out has been stored in the memory.