Abstract: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

Abstract: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

Abstract: A local skew detecting circuit for a semiconductor apparatus include a reference delay block located on the center of the semiconductor apparatus, the reference delay block being configured to receive a predetermined signal and generate a reference delay signal by delaying the predetermined signal by a delay time and a first timing detecting block located on one edge of the semiconductor apparatus, the first timing detecting block being configured to receive the predetermined signal, generate a first delay signal by delaying the predetermined signal by the delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: A connector for one or more optical fibers has a ferrule into which the optical fibers are glued directly with their outer cladding. No stripping of the fibers is required any longer before gluing them to the ferrule and thus, the difficulty of the fragility of the stripped fibers is overcome. The fibers are special fiber having a primary coating with smaller tolerances of ±2 microns. The fibers are arranged on a flexible foil which forms an optical overlay for a printed circuit board.

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: Disclosed in a semiconductor device including a substrate, a first transistor, a second transistor, and a first source electrode and a first drain electrode of the first transistor are arranged along a first direction and a second source electrode and a second drain electrode of the second transistor are arranged in a reverse order of the first source electrode and the first drain electrode along the first direction, the first source electrode and the second source electrode are connected by a source connecting wiring, the first drain electrode and the second drain electrode are connected by a drain connecting wiring, a first gate electrode and a second gate electrode are connected by a gate connecting wiring and the source connecting wiring and the drain connecting wiring are provided at positions except a region overlapped with the first gate electrode, the second gate electrode and the gate connecting wiring.

Abstract: A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

Abstract: A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a second delay section delaying the signal by a second delay amount greater than the first delay amount, and a delay amount selector selecting a signal route where the delay amount is a sum of the first delay amount and the second delay amount when the delay amount exceeds a maximum delay amount delayable by the first delay amount section. The delay amount from when a signal is inputted to when the signal is outputted can be set in a wide range, while suppressing the circuit scale.

Abstract: A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

Abstract: A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

Abstract: A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermined delay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device comprising a data input and a clock input. Read data is applied to the interface in response to a read access to the memory. An RDT clock signal, which is derived from an internal clock signal and is in synchronism with the read data, is permanently applied to the interface. The DLL circuit provides a delayed clock signal defining a optimum sampling time for the read data as a signal obtained by comparing the internal clock signal with the RDT clock signal and shifting the obtained signal if at least one of a set-up time or a hold time is violated. The data input of said at least one register device is connected to the interface and the delayed clock signal is applied to the clock input of the at least one register device in order to sample the read data.

Abstract: A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase and a first decrease of the first delay time. A setting circuit operates synchronously with the first clock signal, outputs a second clock signal delayed from the first clock signal by a second delay time adding the first increase and subtracting the first decrease. A second circuit inputs the first output signal and operates synchronously with the second clock signal.

Abstract: A method and a digital processor circuit to process digital delays are provided. The digital processor circuit may comprise circuit memory and a processor module such as a digital signal processor (DSP), a delay line module, a filter module and a sample rate converter module. The circuit memory may comprise a digital delay line memory portion to provide a plurality of digital delay lines; and a cache memory portion to perform a pre-fetch data transfer operation from the main memory to the cache memory portion. The cache memory portion may comprise a plurality of delay caches that are updated with data samples from corresponding delay lines in the main memory. The sizes (e.g., the relative sizes) of the delay line memory portion and the cache memory portion of the circuit memory may be adjustable. The sizes may be dependent upon algorithms executed by the processor module.

Abstract: The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable signal and a second bank enable signal. The present invention has an advantage that there is no problem of substantially reducing a refresh prosecution time for a second portion because a delayed refresh enable signal is being disabled even while the second bank enable signal is being enabled.

Abstract: A frequency divider divides a frequency of a DLL clock CLK_P into two, to generate ZCLK_PD0 and ZCLK_PD1. A delay circuit generates ZCLK_PDD0, ZCLK_PDD1 obtained by delaying ZCLK_PD0, ZCLK_PD1 respectively by Tc (=a backward amount of CLK_P with respect to an external clock+a delay amount of an internal clock with respect to the external clock). A frequency division select instruction circuit generates ZSEL0, ZSEL1 based on an internal clock CLK, and ZCLK_PDD0, PDD1. A ZSEL0 shifter circuit generates ZSEL1_D2 including a clock pulse of ZSEL1. A ZCLK_P #2 select circuit selects a clock pulse of ZCLK_PD0 using ZSEL1_D2.

Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.

Abstract: An optical device and a method for manufacturing the optical device. An optical device having a molded-package structure includes: a lead frame having a ferrule-mounting portion; a ferrule mounted on the ferrule-mounting portion; and a molding resin that encapsulates the lead frame and the ferrule, molding, except that an end of the ferrule protrudes through and outside of the surface of the molding resin. The first groove parallel to a longitudinal axis of the ferrule is located on the ferrule-mounting portion and the ferrule is placed on the first groove. Thus, the ferrule is hardly ever detached from a ferrule-mounting portion, an optical fiber is hardly ever damaged, and an optical coupling is hardly ever obstructed.

Abstract: A single event effect hardening technique for removing glitches in digital logic circuits is disclosed. The noise immune latch circuit includes a first input, a second input, and an output. The noise immune latch circuit includes a first set of two cross-coupled transistors, a second set of two cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set. The first and second sets of isolation transistors are respectively connected to the first and second sets of cross-coupled transistors such that two inversion paths are formed including the two sets of cross-coupled transistors and the two sets of isolation transistors. The noise immune latch circuit changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input.

Abstract: A semiconductor device includes a variable-delay circuit which adjusts a delay of an input clock signal by changing a number of delay elements having the input clock signal passing therethrough so as to generate a delayed clock signal, and a timing-stabilization circuit which changes the number of delay elements by one stage at a time in a first condition and by more than one stage at a time in a second condition to control the delay, thereby stabilizing the delayed clock signal to a desired timing.

Abstract: Disclosed herein is an ATD circuit of the present invention. In order to generate a stable ATD pulse, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means outputs a first output signal having a first pulse width in response to a change in external address signal and outputs, when the external address signal is brought to a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means inputs therein the signal outputted from the pulse width amplifier circuit and waveform-shapes the output signal so as to output an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal outputted from the first circuit means.

Abstract: A method and apparatus for estimating the frequency of a periodic signal and for canceling the interference in a modem signal. Power line noise may interfere with electronic signals. Since power lines may be either 50 Hz or 60 Hz, depending on the country, frequency estimation of the periodic power line noise is necessary. Modem signals are received and autocorrelated in order to identify the periodic characteristics of the signal over time. Once the frequency is identified, the power line noise is modeled based on creating a circular buffer. Initially, the circular buffer is composed of scaled samples of one cycle of the fundamental frequency of the power line noise. Thereafter, samples are received, scaled, and combined with previous buffer values in order to update the buffer. In this manner, the buffer models the power line noise, so that the power line noise may be removed from the system.

Abstract: A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

Abstract: An all-optical circulating shift register encodes a received optical clock signal with a value derived from an encoded optical signal received at a control port thereof. A data input to the shift register is used to modify an encoded optical signal. The resulting encoded clock signal, appearing at an output port, is coupled back to the control port. The shift register uses the encoded clock signal at the control port to encode a subsequently-received clock signal. In one embodiment, the optical shift register is implemented using a Sagnac switch having a feedback path coupled between an output port and a control port of the Sagnac switch.

Abstract: A coherent optical RF memory has an input circuit for receiving RF input signals having wideband frequency content. An electronically tuned frequency selector selects from the RF input at least one desired RF signal having a desired frequency content for storing in memory. A first transducer responsive to the frequency selector converts the at least one desired RF signal into an optical signal representative of the RF signal. The optical signal is stored in an optical storage device. A second transducer responsive to the optical storage device converts the stored optical signal back to an RF signal, forming a recirculating loop. The desired signal is automatically self-equalized as it recirculates in the loop in order to avoid oscillation while maintaining signal coherency. The desired signal may be used for jamming or deception in electronic warfare (EW) or electronic intelligence (ELINT) systems.

Abstract: An optical latch includes first and second optical switches arranged in series. An input signal is received in the first optical switch and is passed through to the second optical switch. The second optical switch latches-up to this received signal. Then the first optical switch is disabled to isolate the second optical switch from inputs to the first optical switch. Feedback lines from the output of the second optical switch to the input of the second optical switch ensure that the second optical switch remains latched. Switching signals are provided at appropriate timing to ensure correct operation of the optical latch.

Abstract: A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.

Abstract: An optical shift register constructed from at least two optical memory cells connected in cascade, each memory cell having an optical combiner, a 1.times.2 optical switch, a clock, and an optical amplifier, all connected by optical fibers. Each memory cell in the sequence is connected to the next sequential cell by an optical fiber from its output port to the input port of the next sequential cell. The input port of the first optical memory cell serves as the input to the shift register. The output port of the last sequential optical memory cell serves as the output port of the shift register. Each cell is controlled by a clock, all clocks operating at the same rate, but each out of phase with the clock in the next sequential cell. Control signals are provided by said clocks to shift optical pulses from one cell to the next for the enter-shift-exit cycle of the shift register.

Abstract: A fiber optic recirculating memory comprises a splice-free length of optical fiber which forms a loop that is optically closed by means of a fiber optic coupler. The coupler couples an optical signal input pulse to the loop for circulation therein, and outputs a portion of the signal pulse on each circulation to provide a series of output pulses. A pump source is included to pump the fiber loop with a pump signal having sufficient intensity to cause stimulated Raman scattering in the fiber loop, and thereby cause amplification of the circulating signal pulse. The fiber characteristics, coupler characteristics, and pump power are selected to yield a Raman gain which compensates for the total round-trip losses in the fiber loop, so as to provide an output pulse train of constant amplitude pulses. The invention may be implemented utilizing either a standard coupler or a multiplexing coupler.

Abstract: A sequential-access memory of an auto-refreshing type has an increased storage capacity. The sequential-access memory has at least two dynamic-type memory cell arrays serially connected to one another to form a loop. Each array comprises N rows by M columns of memory cells each having a read selection line and a write selection line. The read selection line of each memory cell of each row is connected to the write selection line of the memory cell of the same row which comes next to the each memory cell to form an address selection line. The address selection lines of each memory cell array are activated one after another to effect a sequential access to the memory cell array. Data read form each memory cell array is fed through a delay circuit to the memory cell array which comes next to the each memory cell array. A logic circuit for subjecting data outputted from one memory array may be additionally provided to feed data representative of the result of the predetermined operation to the next memory array.

Abstract: A matrix data transposer is disclosed which allows data stored in a matrix format to be transposed at high speed using parallel processing techniques. In one embodiment, the data are passed through a time delay means which delays each bit of a word a different amount. The time delayed data are then passed through a distribution means which operates to shift the data in position from rows to columns. The shifted data are then passed through a second time delay means to restore the data to its original timing, the end result being the data transposed so that what was originally one row of the data matrix is now one column of the matrix. A second embodiment achieves the same result using only one time delay means and two distribution means.

Abstract: A fiber optic recirculating memory is disclosed which utilizes a single splice-free single mode optical fiber coupled to itself to form a loop which acts as a delay line. A single signal supplied as an input to the device will result in a series of output signals identical to the input signal, although at smaller, decreasing amplitudes. In addition to being useful as a recirculating memory device for use in a system where data is generated at a rate faster than it can be accepted by a data processor, the invention may be used as a tap filter to pass a selected fundamental frequency and its harmonics, and to attenuate all other frequencies.

Abstract: A memory device operable at high speed is disclosed. The device comprises selection means coupled to word lines for selecting one of them detection means for detecting a signal appearing in the selected word line, and word line drive means responsive to an output of the detection means for supplying the selected word line with a voltage capable introducing a selection level in it independent on the selection means.

Abstract: The invention provides a random access memory which consists of a plurality of recirculating sub-memories each having a fixed number of cells for volatile information storage and a further cell, also for volatile information storage, which is connected to the output thereof. The cells may be constructed according to LSI technique. Under the control of a circulating counter, each further cell is connected to an output of a rewrite amplifier which is connected in the recirculating loop of a sub-memory. The information of the further cell is accessible at random by a selection device and is regenerated once per cycle of the sub-memory. Thus, an advantageous compromise is obtained between the features of serially operating memories and random access memories, without an expensive additional buffer being required.

Abstract: A signal processor suitable for real time processing of a complex signal having a relatively narrow frequency spectrum is disclosed. Such signal processor includes a so-called delay line time compressor adapted to receive digital signals corresponding to samples of the complex signal into selected stages thereof and to convert such digital signals into a resulting complex signal, analogous to the complex signal being processed, but having a relatively wide frequency spectrum. The signal processor also includes a digitally controlled oscillator in combination with a single side band generator to produce frequency-varying heterodyning signals which, when mixed with the resulting complex signal, permit separation of the frequency components of such resulting signal to permit any further separate processing of each one of such components.