Abstract: A serial magnetic mass storage device and associated data storage method of the kind in which data is encoded in single magnetic domains in nanowires. In the invention, the nanowires are provided with a large number of notches along their length to form domain wall pinning sites. Moreover, the notches are addressed in groups (A, B, C) by heating electrodes. By alternately heating the notches hosting head-to-head and tail-to-tail domain walls in synchrony with alignment and anti-alignment of an operating field (H) along the nanowire the magnetic domains are moved along the nanowire by alternate movement of the head-to-head and tail-to-tail domain walls in caterpillar or worm-like motion in which the domains are incrementally lengthened and shortened by one inter-notch distance as they move along the nanowires under the joint coordinated action of the heating and alternating operating field.

Abstract: Provided is a fuse option device in a semiconductor integrated circuit. In the fuse option device, a pad receives an external fuse program signal, a program signal driving circuit is connected to the pad through a signal line and generates a program activation signal in response to the fuse program signal and an address validity signal. A fuse circuit is electrically programmed in response to the program activation signal, and a pull-down resistor is connected between the signal line and ground.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell. Techniques for determining whether the neighbor memory cell was programmed before or after the given memory cell are disclosed.

Abstract: A power semiconductor device includes an input signal processor circuit to which control signals are input, and power device driving circuits for individually driving power devices based on output signal of the input signal processor circuit. Level shift circuits are individually inserted between the input signal processor circuit and the power device driving circuit on a p-side and between the input signal processor circuit and the power device driving circuit on an n-side to electrically insulate GND lines for the p-side and n-side power device driving circuits and a GND line for the input signal processor circuit.

Abstract: This disclosure relates to a programmable write-once, read-only semiconductor memory array which has an improved current source for each bit line and an improved current sink for each Word line. This programmable write-once, read-only semiconductor memory array utilizes a SCR (PNPN or NPNP) on the end of each Word line of the array to function as a current sink to minimize voltage drop on the Word line and a SCR (PNPN or NPNP) on each Bit line of the array for current sourcing purposes. This disclosure also relates to an integrated SCR (PNPN or NPNP) for use with a plurality of connected semiconductor devices to provide either a current sourcing or current sinking or drawing function for the plurality of connected semiconductor devices.