Abstract: A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described.

Abstract: A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described.

Abstract: In the memory module, a buffer is disposed on one of at least two circuit boards in the memory module. The buffer is for buffering signals for memory chips on at least two circuit boards in the memory module.

Abstract: A magnetic random access memory includes a plurality of multi-layered memory structures that are formed within a single memory unit and connected in one of a series and a parallel configuration. Each of the plurality of multi-layered memory structures has a resistance that varies based on a magnetization direction of a ferromagnetic layer. A transistor is operatively coupled to each of the plurality of multi-layered memory structures to perform one of a memory read and a memory write operation based on a conduction state of the transistor.

Abstract: A method of programming a programmable resistance element. The programmable resistance element may be programmed to a BLOWN state. After being programmed to the BLOWN state, the element can no longer be programmed to its low resistance state. The method of programming allows the programmable resistance element to be used as a fuse.

Abstract: The present invention provides a memory cell array structure comprising: a plurality of cell array blocks aligned in matrix in both the row and column directions, and each of the cell array blocks including a plurality of magnetic memory cells; a plurality of main word lines being connected through sub-word switching devices to the same number of sub-word lines as a first number of the cell array blocks aligned in the row direction, and each of the sub-word lines being connected to at least one of the magnetic memory cells; and a plurality of main bit lines being connected through sub-bit switching devices to the same number of sub-bit lines as a second number of the cell array blocks aligned in the column direction, and each of the sub-bit lines being connected to at least one of the magnetic memory cells.

Abstract: A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

Abstract: A magnetic random access memory or the like has a plurality of magnetic storage elements laminated on a single transistor, resulting in a reduction in the number of necessary components and a considerable enhancement in the degree of integration of the memory.

Abstract: The invention described herein defines a system and a method for selectively controlling the sensitivity of a region of a magnetoresistive element to an incident magnetic field, by applying an external magnetic field to the magnetoresistive element. A number of applications to non-volatile data storage are described, as is a magnetic sweep element based on a FET structure. Finally, the storage media and recording modes (in-plane vs. perpendicular) best suited to the proposed applications are analyzed, and the desired or optimal characteristics of the proposed devices are discussed.

Abstract: A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.