Abstract: A time-to-digital converter (TDC) circuit generates a digital output indicating a time, known as a phase difference, from a phase of the generated signal to a corresponding phase of a reference signal. The digital output is used by the digitally controlled oscillator (DCO) to correct for the phase/frequency difference to synchronize the generated signal with the reference signal. In an aspect, an adaptive TDC circuit generates a first digital indication in a coarse mode when the offset time is above a threshold and generates a second digital indication in a fine mode when the offset time is below the threshold. The first digital indication and the second digital indication each comprise a same number of bits, and the first digital indication is normalized to the second digital indication for the digital output of the adaptive TDC circuit. A fractional bit may be employed to compensate for a quantization error.

Abstract: In a method for operating a device comprising an internal clock generator and an internal clock and being connected to a network, the internal clock is incremented by the internal clock generator. Moreover, the internal clock is synchronized with a network frequency of the network.

Abstract: A first light beam transmits from a first location to a region of interest at a time t1a and reflects off at least one object disposed in the region of interest, producing a first reflected light beam. A time of flight (ToF) counter is incremented until the reflected first light beam is received back at the first location, whereupon ToF counter stops at time t1b. A second light beam transmits from the first location to the region of interest at time t2a subsequent to time t1b and reflects off the least one object to produce a second reflected light beam. ToF counter is decremented, starting from first count value, until the reflected second light beam is received back at the first location, whereupon ToF counter stops at time t2b. A real-time velocity of the object is computed based at least in part on t1a, t1b, t2a, and t2b.

Abstract: A waveform capture device (WCD) is a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD may be implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It may be calibrated via a dynamic phase-shifting (DPS) method that requires substantially less data and resources than conventional techniques.

Abstract: A toy vehicle track system of the present application includes electrical connections between the track pieces that allow a central hub, referred to herein as a “portal piece,” to communicate with any track pieces included in the track system. In order to ensure that the portal piece can quickly and accurately identify track configurations that are built, the toy vehicle track system implements a communications protocol that supports communications between any two pieces of track. Based on these communications, the portal piece can determine an orientation, a track type, and a position of any track pieces attached, whether directly or indirectly, to the portal piece. The portal piece can then transmit this information to an electronic device executing an application associated with the track system to allow for digital play on a digital version of the track configuration (among other digital play modes).

Abstract: Method for a runtime measurement of a signal between two events. A phase shift between the signal on the occurrence of a first event and the signal on the occurrence of a second event is determined, and to an arrangement for performing the method has the underlying object of providing a runtime measurement of a signal between a first event and a second event that can be carried out with a high accuracy, at a high speed, and with a low computational effort. A modulation signal is generated whose phase position is determined as a first signature for the occurrence of the signal in the first event. The phase position of the modulation signal is determined as a second signature for the occurrence of the signal in the second event; and in that the runtime is determined as a difference of the phase positions of the first and second signatures.

Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.

Abstract: An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.

Abstract: Provided are methods and systems for testing time parameters of an adaptor and systems. The method includes the following. After a testing system is coupled with an adaptor, a clock signal is received from the adaptor, where the clock signal is indicative of the transmission time of the instruction. A first valid interrupt of the clock signal, a square wave corresponding to the first valid interrupt, and a next valid interrupt of the first valid interrupt are acquired. A first falling edge and a first rising edge of the first valid interrupt, a second falling edge of the square wave, and a third falling edge of the next valid interrupt are acquired. A test result time parameters of the adaptor is generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.

Abstract: The invention relates to a processing, i.e. storing and analyzing, of measurement data. In order to store the measurement data, respective data units or data sets are created for sampling points, a plurality of measurement data temporally adjacent to the sampling-point measurement datum being stored within the data unit. A time interval between time values of the sampling-point measurement data of two consecutive data units at least is set approximately to a multiple of a sampling time interval, i.e. of a reciprocal of the measurement-value recording rate or sampling rate. The method according to the invention reduces the provision of data units because an individual data unit contains, in addition to a sampling-point measurement date, further measurement data temporally adjacent to the sampling-point measurement date.

Abstract: A circuit system comprises a processor, a first clock with a first frequency, a second clock with a second frequency, such second frequency being higher than said first frequency and a clock calibration module. The clock calibration module comprises a plurality of counters configured to count cycles of the second clock when triggered. Each of the plurality of counters is configured to be triggered at successive cycles of the first clock. Each of the plurality of counters is configured, after a predetermined number of cycles of the first clock, to output a count of elapsed second clock cycles and the processor is configured to determine, using the counts outputted by the plurality of counters, a ratio between the first frequency and the second frequency.

Abstract: Disclosed herein is a method and apparatus for determining time of arrival of incident photons. The time of arrival may be determined with high time accuracy based on the times a voltage across a capacitor being charged by charge carriers generated from the incident photons at which the voltage reaches a plurality of thresholds, respectively, and the stable value of the voltage.

Abstract: A detection-system for a vehicle to detect the presence of one or more object relative to the vehicle comprises a module-housing, a radar sensor component located within the module-housing for emitting a radar beam and receiving reflected signals in a detection mode. The radar sensor component comprises means for emitting a defrost beam in a defrost mode; the defrost beam overlapping the radar beam. The detection-system further comprises an absorber material located in the field of view of the defrost beam to absorb the energy of the defrost beam and to warm up in view to provide a defrosting effect.

Abstract: A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

Abstract: A digital synthesizer includes a ramp generator that generates a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, that receives the FCW signal and outputs a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator that compares a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

Abstract: An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided.

Abstract: A time measurement device measures a time interval between input timings of first and second pulsed target signals. The device includes: a processor; a number-of-periods detector that detects, by using a clock signal with a predetermined clock frequency and a predetermined clock period, the time interval in units of the clock period; and a phase detection unit including a band-pass filter. The band-pass filter receives at least one of the first and second target signals as a filtering target signal and extracts a signal component of the clock frequency from the filtering target signal. The phase detection unit detects a phase difference between the extracted signal and the clock signal. The processor derives, by using a result detected by the number-of-periods detector and the detected phase difference, the time interval at a resolution finer than the clock period.

Abstract: Improved signal-to-noise performance of projected capacitance touch screens and panels is provided by an integrated circuit regulated high voltage source and high voltage/current drivers coupled to a plurality of projected capacitive touch elements that are controlled by a microcontroller. The single integrated circuit high voltage generator/driver may comprise a voltage boost circuit, a voltage reference, power-on-reset (POR), soft start, a plurality of voltage level shifters and a serial interface for coupling to the microcontroller that may control all functions related to using the projected capacitance touch screens and panels.

Abstract: A force sensing touch sensor comprises a substrate having a plurality of conductive electrode rows and a plurality of conductive electrode columns substantially perpendicular to and over the plurality of conductive electrode rows on a surface of the substrate, and a force sensor at each corner of the substrate. When a touch is applied to the surface of the touch sensor, the capacitance value will change of a capacitor formed by an intersection of an electrode row and column proximate to the location of the touch to the surface of the touch sensor. These force sensors detect total and proportional force on the touch sensor substrate. This force information is then combined with the touch location(s) previously determined, and the individual touch force(s) can then be interpolated with sufficient resolution for three dimensional (3D) gesturing applications.

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract: To establish an initial/resting position of a permanent magnet rotor, all motor stator windings are stimulated (voltage applied thereto) in sequence, the time it takes for current in the stimulated stator winding to rise to a specific current value is measured for each stator winding and these time measurement results processed. From the measured time results rotor position to within 60 degrees is determined and the position sector is known prior to starting/rotating the motor. Once the rotor position is known, the next commutation point in a six step sequence is known before actually starting/rotating the motor. Position measurement winding stimulation may be interleaved with commutation pulses, or the unexcited stator winding may be stimulated between commutation pulses to the other two excited stator, wherein one of the two stator windings remains connected to the power and provides a current return path to the unexcited but stimulated stator winding.

Abstract: A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.

Abstract: A projected capacitive touch and force sensor capable of detecting multiple touches thereto and forces thereof is coupled with a digital device having multi-touch and force decoding capabilities. Once a touch has been established, a force thereof may be assigned to the touch based upon the magnitude of change of capacitance values determined during scans of the projected capacitive touch and force sensor. The touch forces applied to the touch sensor from the associated tracked touch points may be utilized in further determining three dimensional gesturing, e.g., X, Y and Z positions and forces, respectively.

Abstract: Improved signal-to-noise performance of projected capacitance touch screens and panels is provided by an integrated circuit regulated high voltage source and high voltage/current drivers coupled to a plurality of projected capacitive touch elements that are controlled by a microcontroller. The single integrated circuit high voltage generator/driver may comprise a voltage boost circuit, a voltage reference, power-on-reset (POR), soft start, a plurality of voltage level shifters and a serial interface for coupling to the microcontroller that may control all functions related to using the projected capacitance touch screens and panels.

Abstract: A system and method are provided for converting voltage-to-time-to-digital signals. The method periodically samples a continuous analog input and discharges the sampled analog input at a predetermined rate to supply a continuous analog ramp signal. The ramp signal is converted into an n-bit coded digital word representing the q most significant bits (MSBs) of a k-bit binary word, where q is an integer greater than 0, n is an integer greater than 1, and k is an integer greater than q. At least one bit of the coded digital word is supplied at a time representing the p least significant bits (LSBs) of the k-bit binary word. The coded digital word is converted into a single-bit pulse signal containing timing information representing the p LSBs of the k-bit binary word at an output, and the timing information is converted into the p LSBs of the k-bit binary word.

Abstract: A touch sensor capable of detecting multiple touches thereto is coupled with a digital device having multi-touch decoding capabilities. These multi-touch decoding capabilities comprise touch data acquisition, touch identification, touch tracking and processed touch data output to a device associated with the touch sensor. Touch identification comprises touch location(s) peak detection, touch location(s) nudging and touch location(s) interpolation. Touch data acquisition locates potential touches on the touch sensor. Peak detection identifies where potential touch locations are on the touch sensor. Once a potential touch location(s) has been identified, touch location nudging examines each adjacent location thereto and interpolation examines the adjacent touch location values to generate a higher resolution location of the touch. Touch tracking compares time sequential “frames” of touch identification data and then determines which touches are associated between frames for further processing, e.g.

Abstract: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.

Abstract: A circuit for determination of a resistance of an array of capacitive elements includes a reference ring oscillator circuit, the reference ring oscillator circuit being loaded with low-loss capacitive elements; an array test ring oscillator circuit, the array test ring oscillator circuit being loaded with the array of capacitive elements; and a resistance determination module, the resistance determination module configured to determine the resistance of the array of capacitive elements based on data from the reference ring oscillator circuit and the array test ring oscillator circuit.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: Systems and methods for calibrating real time clock are provided. A representative receiver includes a GPS device comprising a real time clock (RTC) circuitry that generates RTC clock signals and a temperature compensated crystal oscillator (TCXO) that generates TCXO clock signals. A ratio counter circuitry receives both the RTC clock signals and the TCXO clock signals and determines a frequency ratio by comparing the RTC clock signals and the TCXO clock signals. A computing device receives the frequency ratio and estimates a current RTC frequency based on the received frequency ratio. The computing device is configured to calibrate an estimated RTC time being maintained at the RTC circuitry based on an estimated RTC frequency from a prior estimation, the current RTC frequency and an elapsed time of the RTC circuitry.

Abstract: An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node.

Abstract: A novel and useful apparatus and related method for on-chip measurement of the clock to output delay of a latch within an integrated circuit. The delay measurement mechanism enables measuring the time delay from the transition of the clock input to the data output of a latch. The output delay of the on-chip latch is measured by making the latch delay part of a ring oscillator and measuring its frequency of oscillation. A latch based delay stage is used to construct the ring oscillator in which a delayed short pulse derived from the input edge is used as the trigger for the latch. The latched ring oscillator mechanism of the invention can be used to measure the clock to output (C2Q) delay of on-chip latch devices.

Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.

Abstract: A device is disclosed for measuring a plurality of time intervals.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

Abstract: A pulse width measurement circuit generates a time difference signal that corresponds to the pulse width of the input pulse signal PULSE. A delay circuit delays the input pulse signal PULSE by a predetermined amount, and outputs a start signal. An inverter inverts the input pulse signal PULSE, and outputs a stop signal. A time measurement circuit measures the time difference between a positive edge in the start signal and a positive edge in the stop signal, and outputs a time difference signal that corresponds to the time difference.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.

Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.

Abstract: An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tuner, a sampling module, a counter, wherein the delay pulse generator generated a delayed pulse from the second clock, the oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the second frequency, the sampling module samples the delayed pulse at the first frequency, the counter generates a digital counter value by counting a number of sampling by the sampling module, and a time width of the delayed pulse can be calculated by the digital counter value. The second oscillator can be a tunable ring oscillator with one or more coarse tune stages and one or more fine-tune stages.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: In one aspect, a method of radar altimeter operation, the altimeter including a high frequency counter coupled to a processor is described. The method comprises providing a continuous wave to the high frequency counter upon receipt of a transmit pulse, counting the cycles of the continuous wave, discontinuing counting of the continuous wave cycles upon receipt of a return pulse, outputting a count from the high frequency counter to the processor, and operating the processor to convert the count to an altitude.

Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.

Abstract: A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

Abstract: Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.

Abstract: A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage.

Abstract: An electric counter circuit (30, 40, 80) comprises a clock generator (1, 54, 111, 120, 130) for generating a plurality of clock signals (21-24, 121-125, 131-134) and a sampling device (32, 81) for sampling the clock signals (21-24, 121-125, 131-134) at a first moment in time when a first characteristic signal section (LE) of a digital signal (DS) appears. Furthermore, the circuit (30, 40, 80) comprises a calculation device (33) for calculating the time between the first moment and a second moment which is later than the first moment. This calculation is based on the clock signals (21-24, 121-125, 131-134) at the first moment and based on the clock signals (21-24, 121-125, 131-134) at the second moment. The clock signals (21-24, 121-125, 131-134) each have the same cycle duration (T) and are phase-shifted with respect to each other.

Abstract: A digital time converter with an embodiment including a coarse measuring circuit and a fine measuring circuit. The fine measuring circuit allows an accurate determination of the temporal position of an event inside a period of the time base, by interpolation or averaging of sinusoids in quadrature, sampled coincidentally with a burst of impulses generated by the converter's triggering circuit.

Abstract: A semiconductor circuit device includes an oscillation circuit, an output circuit that receives a signal output from an oscillation circuit and outputs an oscillation signal, a temperature sensing element, a characteristic adjustment circuit that adjusts characteristics of the oscillation circuit on the basis of a signal output from the temperature sensing element, and a first connection terminal that is electrically connected to the output circuit and via which the oscillation signal is output, in which a distance between the output circuit and the first connection terminal is shorter than a distance between the temperature sensing element and the first connection terminal in a plan view.