Solid State Oscillating Circuit Type Patents (Class 368/156)
  • Patent number: 9727767
    Abstract: Embodiments of a method for clock synchronization in a radio frequency identification (RFID) equipped device, an RFID equipped device, and a hand-held communications device are described. In one embodiment, a method for clock synchronization in an RFID equipped device involves measuring a difference between a field clock frequency generated from an external clock and an internal clock frequency generated from an internal clock and generating outgoing bits in the RFID equipped device in response to the measured difference. Generating the outgoing bits involves adjusting the bit length of at least one of the outgoing bits in response to the measured difference. Other embodiments are also described.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 8, 2017
    Assignee: NXP B.V.
    Inventors: Klemens Breitfuss, Peter Thueringer
  • Patent number: 9519273
    Abstract: An electronic timepiece has a display device that displays display information, a drive mechanism that drives the display device, a crown that can perform a rotary operation, and a control device that corrects the display information displayed on the display device by the rotary operation of the crown. The control device has a single correction mode and a continuous correction mode which are selected by the rotary operation of the crown. In the single correction mode, a single correction signal is output to the drive mechanism so that the display device is corrected as much as a single correction quantity. In the continuous correction mode, a continuous correction signal is output to the drive mechanism so that the display device is corrected as much as a continuous correction quantity. The continuous correction quantity is set depending on types of the display information to be corrected in the continuous correction mode.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: December 13, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Hirokazu Nishijima
  • Patent number: 9497364
    Abstract: The camera module according to the present disclosure can improve reliability by mounting a posture sensor on a PCB and promoting a bending prevention of the PCB.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 15, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Nae Seong Kim, Hack Ho Kim
  • Patent number: 8963647
    Abstract: A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprised of polysilicon encased by an insulating material; creating lattice imperfections at boundary of the polysilicon to cause leakage from the floating-gate transistor; measuring current read out from the floating-gate transistor at a time subsequent to the initial time; and determining an amount of time between the initial time and the subsequent time using the measured current.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: February 24, 2015
    Assignee: Board of Trustees of Michigan State University
    Inventor: Shantanu Chakrabartty
  • Patent number: 8816779
    Abstract: A device for an atomic clock, including: a laser source (102) generating a laser beam; a quarter-wave plate (105) modifying the linear polarization of the laser beam into a circular polarization and vice versa; a gas cell (106) placed on the laser beam having a circular polarization; a mirror (107) sending the laser beam back toward the gas cell; a first photodetector (108a); means (103, 101a, 107) for diverting the reflected beam of the laser source (102), and a second photodetector (109) placed behind the mirror (107), the mirror being semitransparent and allowing a portion of the laser beam to pass therethrough, the second photodetector (109) being used for controlling the optical frequency of the laser and/or for controlling the temperature of the cell (106).
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 26, 2014
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechnique S.A.
    Inventors: Steve Lecomte, Jacques Haesler
  • Publication number: 20140204720
    Abstract: There are provided a constant voltage circuit that features low current consumption and stable operation, and an analog electronic clock provided with the constant voltage circuit. The constant voltage circuit includes a differential amplifier circuit which is turned on/off by a predetermined signal and which controls the voltage of a gate of an output transistor on the basis of a reference voltage and a feedback voltage that are received, a switch circuit which is connected to an output terminal of the differential amplifier circuit and which is turned on/off by a predetermined signal, and a voltage holding circuit which is connected between the gate of the output transistor and a power supply terminal and which has a resistor and a capacitor connected in series. An analog electronic clock provided with the foregoing constant voltage circuit that supplies a voltage to at least an oscillation circuit and a frequency division circuit.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 24, 2014
    Inventors: Kotaro WATANABE, Makoto MITANI
  • Patent number: 8559276
    Abstract: The system for timing a sports competition includes a main timing device having a first time base, and a secondary timing device having a second time base (5). The two timing devices are capable of operating in parallel when the timing system is enabled. The two timing devices are arranged such that the second time base (5) is synchronized by using a reference timer signal (CLKref) generated by the first time base. The second time base (5) includes a phase lock loop (10, 11, 12, 13, 14, 17) for adapting the frequency of the second timer signal (CLK_T2) according to the frequency of the reference timer signal (CLKref).
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 15, 2013
    Assignee: Swiss Timing
    Inventor: Fabien Blondeau
  • Patent number: 8391105
    Abstract: A real time clock circuit is provided that has an onboard oscillator continuously providing an internal clock frequency, which is digitally synchronized to a more accurate reference clock frequency. An exemplary real time clock inhibits synchronization of the internal clock frequency when the reference clock is unavailable or if the reference clock's frequency is outside of a defined accuracy range.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: March 5, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Luke Raymond
  • Patent number: 8379492
    Abstract: A timepiece includes a casing, a display, a timepiece core unit, and a current processing circuitry. The current processing circuitry includes a rectifying circuitry, an oscillating circuitry, and an output circuitry. The rectifying circuitry is adapted for electrically connected with an AC power source, and arranged to rectify the AC. The oscillating circuitry is electrically connected with the rectifying circuitry, and is arranged to transform the DC outputted from the rectifying circuitry back into AC having a predetermined voltage and a frequency. The output circuitry is electrically connected with the oscillating circuitry, and is arranged to rectifying the AC output from the oscillating circuitry into a DC pulses output, wherein the DC output from the output circuitry is electrically transmitted to the timepiece circuitry for triggering an operation thereof so as to allow the signal generator to generate accurate time signal to display the current time by the display.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: February 19, 2013
    Assignee: Shenzhen Great Power Enterprise Co., Limited
    Inventor: QiXiang Feng
  • Patent number: 8201991
    Abstract: In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: June 19, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shinichi Kouzuma
  • Patent number: 8130596
    Abstract: The electronic circuit (1) controls the operation of the peripheral members of a watch. The circuit (1) includes a processor (2) connected to a non-volatile memory (3), which contains instructions to be carried out, peripheral member controllers (4) for interacting with peripheral members of the watch and connecting means (6a, 6b, 7). These connecting means (6a, 6b, 7) are arranged to enable the peripheral member controllers (4), the non-volatile memory and the processor (2) to communicate data relating to the operation of said watch to each other. This electronic circuit (1) further includes initializing means (8) able to act on the peripheral member controllers (4) to initialize said controllers so that they can execute operations independently of the processor (2) and/or the non-volatile memory (3).
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: March 6, 2012
    Assignee: EM Microelectronic-Marin S.A.
    Inventor: Yves Godat
  • Patent number: 8009520
    Abstract: A polarization gain medium such as an emitting laser diode provides the optical pumping. An atomic vapor cell is positioned in the laser cavity providing spontaneous push-pull optical pumping inside the laser cavity. This causes the laser beam to be modulated at hyperfine-resonance frequency. A clock signal is obtained from electrical modulation across the laser diode.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: August 30, 2011
    Assignee: Princeton University
    Inventors: Yuan-Yu Jau, Kiyoshi Ishikawa, William Happer
  • Patent number: 7729205
    Abstract: A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is generated during a second period of a known duration. The duration of the first period is calculated based on the first count and the second count. A solid-state, thin-film battery is able to be used by virtue of low-current characteristics of the system, enabling extended shelf life for fuzing systems.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: June 1, 2010
    Assignee: Action Manufacturing Company
    Inventors: Jonathan C. Siebott, Richard A. Frantz
  • Patent number: 7697377
    Abstract: A timepiece comprises an atomic oscillator for generating and outputting a reference clock signal, and a timepiece module that operates based on the reference clock signal, wherein the atomic oscillator and the timepiece module are disposed separately so as to be thermally separated. The timepiece also comprises a crystal oscillator for generating and outputting a first oscillation signal, an atomic oscillator for generating and outputting a second oscillation signal with a higher precision than the first oscillation signal, a timepiece module that operates based on the first oscillation signal and the second oscillation signal, and a thermal separator for thermally separating the atomic oscillator from the crystal oscillator and the timepiece module. A portable timepiece and electronic device can thereby be configured so that the effects of heat generation can be reduced and power consumption can be reduced even in cases in which the atomic oscillator is used as a reference oscillator.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: April 13, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Kazunari Agesawa, Kiyoto Takeda
  • Patent number: 7580493
    Abstract: One embodiment of a method of generating a clock signal and synchronizing the generated clock signal with a digital data stream comprises generating a clock signal using an oscillator, identifying a transition in a portion of the data stream, and synchronizing a transition of the clock signal with the identified transition in the data stream by changing a state of the oscillator using control circuitry in response to the identification of the transition in the data stream, wherein the clock signal is synchronized with the data stream for both situations where the oscillator operates at a frequency greater than the data rate and where the oscillator operates a frequency less than the data rate. Other methods and systems are also provided.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: August 25, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Robert John Castle
  • Patent number: 7486757
    Abstract: An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock to a first set of M voltage-controlled delay cells within a feedback loop, and further including an identical set of M voltage-controlled delay cells outside of the feedback loop for delaying the undivided clock and for outputting M multiphase clocks. An optical driver circuit of an optical driving system and a method for implementing a write-strategy for preventing “overlapping” of marks written on adjacent grooves on an optical disc. The circuit and method produce multiple write-strategy waveforms (channels) switching at a high resolution (e.g., T/32) in the Gigahertz frequency range.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-young Kim, Yong-sub Kim
  • Patent number: 7476865
    Abstract: A signal source for use as a frequency source or time keeping signal source includes a radioactive emission source generating a substantially periodic signal corresponding to a radioactive material's disintegration rate. A radioactive emission detector generates a radioactive emission detection signal and, to stabilize the detected periodic signal, a dead time controlling attenuator blanks or shuts off the radioactive emission detection signal for a selected dead time interval in response to each detected radioactive emission (i.e., a detected signal pulse or signal component) generated by the source. The dead time controlling attenuator output provides a long-term and short-term a stable periodic signal.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: January 13, 2009
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Amit Lal, Hui Li, Hang Guo, Shankar Radhakrishnan
  • Publication number: 20080271470
    Abstract: A timer is provided. The timer includes a rotatable electrically non-conducting ratchet gear, an electrically conducting pawl mechanism, and an electronic drive circuit. The ratchet gear has a plurality of teeth. The electrically conducting pawl mechanism includes a pawl configured to engage one of the plurality of teeth on the ratchet gear. The an electronic drive circuit is electrically coupled to the pawl mechanism. The electronic drive circuit passes a current through the pawl mechanism such that the pawl advances the ratchet gear by one tooth pitch.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 6, 2008
    Inventors: Jason Cheetham, Andrew J. Palmer
  • Patent number: 7411867
    Abstract: Apparatus and method for producing a composite clock signal with optimized stability characteristics from individual clocks which have different stabilities or variances. The composite clock signal includes weighted individual clock signals. In a first (PPN) case, an optimum composite clock is a scale-factor-weighted linear combination of clock signals. In another (non-PPN) case, the optimum stable composite clock is the output of a linear filter of the input clocks signals. Both the phases and frequencies of the individual clocks over time are estimated.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: August 12, 2008
    Assignee: Lockheed Martin Corporation
    Inventor: Stephen R. McReynolds
  • Patent number: 7339854
    Abstract: This clock generator comprises an oscillator for generating an alternating current pilot signal and a pulse formatting circuit which is intended to convert the pilot signal from the oscillator into a pulse clock signal having a duty factor of at least approximately 50%. According to one implementation, a series of at least two inverters is provided, the input of the first inverter being controlled by the alternating current pilot signal and the output of the second inverter supplying the clock signal. A power supply means may also be provided to supply the inverters with a regulated power supply voltage dependent on the signals appearing at the outputs of the inverters.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: March 4, 2008
    Assignee: CSEM Centre Suisse d'Electronique et de Microtechique SA, Recherche et Developpement
    Inventor: David Ruffieux
  • Patent number: 7272078
    Abstract: A representative measurement indicating a relative oscillation speed of a reference clock during a representative calibration period is ascertained. Multiple calibration periods are defined including first and second calibration periods. The first calibration period begins at a first start time, wherein a first time offset value is equal to a difference between the first start time and a transition point of the reference clock signal within the first calibration period. The second calibration period begins at a second start time, wherein a second time offset value is equal to a difference between the second start time and a transition point of the reference clock signal within the second calibration period. The first and second time offset values are different from one another. Measurements are generated by, for each one of the calibration periods, measuring the speed of the reference clock. The measurements are then averaged.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: September 18, 2007
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Jacobus Cornelis Haartsen
  • Patent number: 6958953
    Abstract: Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: October 25, 2005
    Assignee: International Business Machines Corporation
    Inventors: Eric E. Retter, John M. Sutton
  • Patent number: 6958951
    Abstract: In an ensemble oscillator system including multiple free-running oscillators, a voltage controlled oscillator having a frequency responsive to a control signal, and a differencer unit that measures time differences between the oscillators, an adaptive Kalman Filter Processor (AKFP) generates the control signal responsive to the time differences. The AKFP uses oscillator noise models to model noise/errors of the ensemble system oscillators, including random noise parameters, and adaptively estimates the errors and the random noise parameters to derive the control signal.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: October 25, 2005
    Assignee: The Johns Hopkins University
    Inventor: Dennis J. Duven
  • Patent number: 6956793
    Abstract: A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k?1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k?1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k?1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k?1.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventor: Hung C. Ngo
  • Patent number: 6888780
    Abstract: The present invention provides a method and system to simultaneously use the microwave and Zeeman end resonances associated with the same sublevel of maximum (or minimum) azimuthal quantum number m to lock both the atomic clock frequency and the magnetic field to definite values. This eliminates the concern about the field dependence of the end-resonance frequency. In an embodiment of the system of the present invention, alkali metal vapor is pumped with circularly-polarized D1 laser light that is intensity-modulated at appropriate resonance frequencies, thereby providing coherent population trapping (CPT) resonances. In another embodiment, pumping with constant-intensity circularly-polarized D1 laser light enhances magnetic resonances that are excited by alternating magnetic fields oscillating at appropriate resonance frequencies.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: May 3, 2005
    Assignee: Princeton University
    Inventors: William Happer, Nicholas N. Kuzma
  • Publication number: 20040008587
    Abstract: A method and system for accurate timing in a low current system useful in fuzing applications generates a first count of oscillations of an oscillator of unknown frequency during a first period of unknown duration. A second count of oscillations of the oscillator is generated during a second period of a known duration. The duration of the first period is calculated based on the first count and the second count. A solid-state, thin-film battery is able to be used by virtue of low-current characteristics of the system, enabling extended shelf life for fuzing systems.
    Type: Application
    Filed: July 11, 2002
    Publication date: January 15, 2004
    Inventors: Jonathan C. Siebott, Richard A. Frantz
  • Publication number: 20030112710
    Abstract: A variety of techniques for low cost reduction of thermal drift in electronic components. These techniques include structures for increasing the thermal mass of an electronic component and for insulating an electronic component from thermal drift caused by air flow as well as structures for thermally isolating an electronic component from heat flow on a circuit board.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 19, 2003
    Inventors: John C. Eidson, Stanley P. Woods, Hans Sitte
  • Patent number: 6567346
    Abstract: An absolute time scale clock includes a radioactive isotope and a computer. The computer includes a processor that determines an indication of the current absolute time and a memory that stores a decay constant of the radioactive isotope, a reference time, and an amount of the isotope at the reference time. A energy supply that provides power to the computer. The absolute time scale clock further includes a detector positioned to respond to emissions from the radioactive isotope. The detector generates an indication of the number of emissions over a time interval that varies with the decay rate of the isotope. The processor is responsive to the indication from the detector, the decay constant, the reference time, and the reference amount to determine the indication of current absolute time.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: May 20, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas J. Aton, Shivaling S. Mahant-Shetti
  • Patent number: 6542440
    Abstract: When the stem of an electronic watch such as one using a quartz oscillator circuit is pulled out, a switch operates so that the hands stop while the oscillation continues, thereby reducing the current consumption. The watch may be stored in this condition and, to achieve an even further power savings, a counting circuit is provided counts and, when a given amount of time has elapsed after the stem is pulled out, a signal is output, so as to stop both oscillation and frequency dividing. Additionally, a pull-down resistance connected to the switch is made by two transistors having a large and a small resistance values, with the above-noted signal being used to cause conduction through only the transistor with the large resistance value when in the power-saving condition, so that current in that part is small.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: April 1, 2003
    Assignee: Citizen Watch Co., Ltd.
    Inventor: Hiroyuki Kihara
  • Patent number: 6529447
    Abstract: An apparatus comprising a first circuit and a timing circuit. The first circuit may be configured to generate an output clock signal that may compensate for oscillation build-up and stabilization time after a power up. The timer circuit may be configured to provide timing in response to the output clock signal.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: March 4, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: K. S. Anil, Thomas K. Mathew, Pradeep Mishra, Rajat Gupta
  • Patent number: 6229765
    Abstract: An electronic sunrise-dependent timepiece, comprising an oscillator circuit for generating clock pulses at a predetermined frequency and a clock circuit coupled to the oscillator circuit for generating minutes and hours and calendar data. An offset correction circuit coupled to the clock circuit and being responsive to a current value of calendar data adds a respective offset to the minutes and hours data so as to generate a sunrise-dependent time of day for display on a suitable display device.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: May 8, 2001
    Assignee: RM-IC Telepathy Ltd.
    Inventor: Moshe Rabi
  • Patent number: 6141296
    Abstract: A time-of-day clock assembly 10 having an oscillator 14 which generates resonant signals used to selectively update a time-of-day register 27. The assembly 10 increments register 27 at intervals of time which are temporarily modified in order to correct for fractional and calibration type errors.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: October 31, 2000
    Assignee: Ford Motor Company
    Inventor: Paul Michael Progar
  • Patent number: 6124765
    Abstract: An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a support layer, a fixed layer positioned on a support layer, remaining portions of a sacrificial layer positioned only on portions of the fixed layer, and an oscillating layer positioned on the remaining portions of the sacrificial layer, overlying the fixed layer in spaced relation therefrom, and extending lengthwise generally transverse to a predetermined direction for defining a released beam for oscillating at a predetermined frequency. The spaced relation is preferably formed by removal of unwanted portions of the sacrificial layer.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: September 26, 2000
    Assignee: STMicroelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Melvin Joseph DeSilva, Syama Sundar Sunkara
  • Patent number: 6069850
    Abstract: A method and apparatus for driving a battery-backed up clock while a computer system is powered-down. The present invention uses an auxiliary power supply, VAUX, to power a microprocessor bus oscillator. The microprocessor bus oscillator is typically a high frequency, highly accurate oscillator. The microprocessor bus oscillator continues to run while the computer system is powered down, but is connected to a wall outlet. Thus, it can be used to synthesize an accurate time base to drive a battery-backed up clock input. A microcontroller, PAL, or other such circuit can be used to convert the high frequency signal from the microprocessor bus oscillator to a frequency suitable for the battery-backed up clock. Thus, a single oscillator is used to keep time for normal operations. Only when the system is moved, or when main power fails, is a battery backed-up crystal oscillator used to keep time. This minimizes the occurrence of timing errors, due to the system being turned off and back on.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: May 30, 2000
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Robert Christopher Dixon, Khuong Huu Pham
  • Patent number: 6008720
    Abstract: A timer alarm device is supported on an ear as an earring by pinching an earlobe of the ear with an arm and a clip. Spring force to pinch the earlobe is produced by permitting a spring provided on the clip to run on a corner of a flat part. A timer circuit, a piezoelectric buzzer, and a battery cell, etc., are accomodated on a head part provided on the upper part of the arm. Since the piezoelectric buzzer for outputting an alarm sound is located in the vicinity of an earhole, a user can hear a greater sound even with a smaller sound volume and hence attention of the user can be securely called. Since functions and component parts are limited to eliminate the need of setting and confirmation that rely upon eyes, even a visually handicapped user can conveniently use the device.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: December 28, 1999
    Assignee: Honda Tsushin Kogyo Co., Ltd.
    Inventors: Kanji Hongu, Yoshiaki Sakamoto
  • Patent number: 5943297
    Abstract: A computer date and time clock including an incrementing binary 32 bit register, used to main elapsed date and time in seconds, and an external 1 Hz clock signal, provided by an oscillator, that increments the register. The oscillator and register are both powered by a battery, to make them independent of computer system power. On computer systems having a 32 bit bus, the register can be read or written with a single I/O cycle on the system bus. Operating system software typically performs time calculations using elapsed seconds since a fixed date and time, thus the register count can represent a number of seconds since the fixed date and time. The 1 Hz clock signal is derived from a higher frequency oscillator using a divider circuit, and a reset circuit within the date and time clock clears the divider circuit each time data is stored in the register.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: August 24, 1999
    Assignee: Hewlett-Packard Co.
    Inventor: Thomas H. Baker
  • Patent number: 5910930
    Abstract: Method and apparatus for dynamic control of power management circuitry in a microprocessor. A clock and power management subsystem within the microprocessor contains clock generation and control logic and a powered-down mode register. The register is controlled by register control logic in the microprocessor and determines the powered-down mode of the various hardware units that make up the microprocessor. The clock generation and control logic also receives a powered-down mode enable signal from each of the hardware units. The hardware unit receive a re-power-up signal which, when activated and deactivated, can cause the hardware units to de-activate and activate, respectively, the powered-down mode enable signal.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: June 8, 1999
    Assignee: International Business Machines Corporation
    Inventors: James N. Dieffenderfer, George Filip Diniz, Thomas Andrew Sartorius
  • Patent number: 5812497
    Abstract: A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: September 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Yahata
  • Patent number: 5706256
    Abstract: A method for selecting fundamental clock frequencies in order to achieve electromagnetic compatibility in electronic products which employ a plurality of clocks. The method require first selecting an ideal frequency for each clock in the product. Then, and until the goal of avoiding coinciding harmonics is complete, the method includes the steps of computing all harmonics of all clock frequencies chosen, determining a minimum difference tolerable in the chosen frequencies and their harmonics for sufficient minimization of electromagnetic interference, and determining if the harmonics of the chosen frequencies coincide impermissibly within the frequency range. If there exists coincidence of harmonics within the predetermined minimum range, then the fundamental frequency of at least one of the clocks corresponding to an interfering harmonic must be adjusted to eliminate the interference.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: January 6, 1998
    Assignee: Johnson & Johnson Medical Inc.
    Inventors: Rush W. Hood, Jr., Michael B. Duich
  • Patent number: 5644271
    Abstract: A temperature compensation system includes a first oscillator to generate a number of pulses which vary from a desired frequency as a function of temperature of the first oscillator. The system also includes a second oscillator to generate digital pulses at a corrective frequency which is greater than the desired frequency. A sensor provides an temperature signal for the first oscillator. A digital memory has a digital error table addressable by a signal corresponding to the temperature signal to provide a number of pulse errors corresponding to temperature error for each of the number of pulses. Each pulse error is a function of the corrective frequency and a temperature versus frequency characteristic of the first oscillator. An accumulator receives each pulse error to generate a cumulative error corresponding to one of the number of pulses. A variable delay device counts a quantity of corrective pulses from second oscillator to provide a delayed output pulse in accordance with the desired frequency.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: July 1, 1997
    Assignee: Mehta Tech, Inc.
    Inventors: Ivan Petrov Mollov, Robert Eugene Havens
  • Patent number: 5640373
    Abstract: A secure time keeping peripheral device is for synchronizing a time reference clock signal to a system clock signal and is especially suited for use in low-power processor applications. Time reference circuitry adjusts a time reference counter held therein responsive to transitions of the time reference clock signal. At least one system time register is connected to the time reference circuitry to receive the time reference counter responsive to transitions of a synchronizing signal. Synchronizing signal generating circuitry is connected to receive the system clock signal and to provide the synchronizing signal, synchronous to the system clock signal, when an externally provided enable signal is asserted to the synchronizing signal generating circuitry. Since the system time register circuitry is only sampled when the externally provided enable signal is asserted (e.g.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: June 17, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Timothy Don Davis
  • Patent number: 5617375
    Abstract: An apparatus for and method of efficiently providing a modular dayclock within a data processing system. This is accomplished by dividing the dayclock hardware into a number of dayclock modules configured to operate in a bit serial fashion. This allows the dayclock to accommodate a variety of dayclock word widths by simply varying the number of dayclock modules provided. Further, since the dayclock may operate serially, rather than in parallel fashion, the number of dayclock module I/O's and board route channels may be substantially reduced. Finally, all control logic may be provided directly in the dayclock modules, thereby eliminating the need for a central dayclock controller.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: April 1, 1997
    Assignee: Unisys Corporation
    Inventors: Mitchell A. Bauman, James L. Federici
  • Patent number: 5615177
    Abstract: A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Yahata
  • Patent number: 5555225
    Abstract: A microcomputer and a clock generator included therein which comprises a first memory and a second memory for storing a signal from CPU, the second memory make it ready for writing when the content of the memory in the first memory is in accord with a predetermined signal, and provides a clock oscillation stop signal for suspending clock oscillation to a clock oscillator when the content of memory in the second memory is in accord with a predetermined signal.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: September 10, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoto Hayashi, Kazuo Nakamura
  • Patent number: 5502689
    Abstract: A clock generator and interrupt bypass circuit for use in reducing the power consumption of the electrical system in which they are implemented. The clock generator provides module clock signals for sequencing modules within the same electrical system, and is capable of generating those module clock signals when in an active mode, and of not generating those module clock signals when in a stand-by mode. The clock generator is further capable of providing a delay of a predetermined length from a request to enter shut-down mode to actual entry into shut-down mode, allowing time to prepare the electrical system for shut-down mode. The interrupt bypass circuit provides a means of leaving shut-down mode in the event that the relevant interrupt requests have been masked.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: March 26, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph W. Peterson, Alan F. Hendrickson, Dale E. Gulick, Dean Grumlose
  • Patent number: 5469409
    Abstract: Timing signals are transmitted from reference transmitters through antenna/receivers (antenna preamplifier nodes) to collector nodes (C-Nodes) and to a central computer. The times of arrival of the signals at the various C-Nodes are measured by the C-Nodes, relative to each C-Node's clock. The time of arrival signals at each C-Node must be based upon a common time reference to be useful for positioning. Therefore, the central computer determines the offsets of clocks relative to a selected reference C-Node clock. The time of arrival signals are then calibrated against one another and used to adjust the time of arrival signals so that all time-of-arrivals are relative to the same reference and can be used for position determination and the clocks of the collection nodes are effectively synchronized.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: November 21, 1995
    Assignee: Motorola, Inc.
    Inventors: Neal R. Anderson, Bart J. Erickson, Keith Leung
  • Patent number: 5412624
    Abstract: A system and method for controlling time-critical functions by dynamically adjusting the interrupt frequency of a microprocessor. Interrupts are generated at a predetermined frequency. Time-critical functions are then performed in response to the interrupts. The interval is adjusted based on timing data from a substantially accurate source. Where the interval is measured in terms of clock pulses, a non-integer number of pulses per interval is attained by varying the number of pulses per interval so that the average over a number of intervals is equal to the non-integer number of pulses per interval. The interval is further adjusted using a selected damping coefficient to eliminate an underdamped condition.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: May 2, 1995
    Assignee: ABB Power T & D Company, Inc.
    Inventor: Thomas M. Yocom
  • Patent number: 5357491
    Abstract: A clock stoppage detector and a selector selection determining circuit are provided on each of a plurality of circuit boards. If any abnormality is detected in the clock selected in accordance with selector control information supplied from a clock selection controller provided common to the plurality of circuit boards, the selector selection determining circuit changes the selection independently of the selection control information. The selector selection determining circuit also performs clock selection independently when failure occurs to the clock selection controller.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: October 18, 1994
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Yamasaki
  • Patent number: 5315566
    Abstract: An improved system for providing ensemble time from an ensemble of oscillators is provided. The improved system provides an ensemble time definition whose large number of possible solutions for an ensemble time are constrained to a limited number of solutions. In one embodiment, a substantially infinite number of solutions is constrained to a single solution.
    Type: Grant
    Filed: June 22, 1993
    Date of Patent: May 24, 1994
    Assignee: Timing Solutions Corporation
    Inventor: Samuel R. Stein
  • Patent number: 5301171
    Abstract: A system for operating a pair of microprocessors with independent system clocks while at the same time providing synchronization by a common interrupt signal, and in which the system clocks are cross-monitored to thereby provide Fail-Safe operation.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: April 5, 1994
    Assignee: Honeywell Inc.
    Inventors: Brian A. Blow, Mark E. Wright