Abstract: In a temperature gradient adjustor for a temperature-compensated electronic watch, the temperature gradient adjusting range can be widened without any drop in the temperature gradient adjusting resolution of a temperature sensitive oscillator by adding a roughly temperature gradient adjusting variable frequency divider for variably dividing the frequency of the output of a temperature sensitive oscillator and by operating the temperature gradient adjustor at a value which is prepared by adding a constant numerical value to temperature gradient adjusting numerical information.A constant voltage supplying to a temperature sensitive oscillator can be finely adjusted from external side so as to optimize a linearity of frequency versus temperature characteristic.

Abstract: Rate change in a quartz crystal timepiece due, for example, to aging of a capacitance used for correcting the frequency-temperature characteristic of the crystal oscillator of the timepiece, is corrected by dividing the oscillator output signal to provide a minimum rate adjustment unit signal and a rate adjustment timing signal. A rate adjustment step width signal consisting of a number of minumum rate adjustment unit signals is predetermined for all of the timepieces in a production run. The number controls the repeated counting of unit signals to produce a series of step width signals. The rate adjustment required for correct timekeeping is determined as an integral number of step width signals. The latter number is set into a second counter in the timepiece to generate a rate adjustment signal. The rate adjustment signal controls the duty cycle of a switch which adds reactance to the crystal oscillator circuit to effect the rate change.

Abstract: A fundamental interval of time is derived from a clock signal of an inherent frequency emanating from an untrimmed crystal oscillator. Firmware and hardware of the time-of-day clock system are used to control and modify the time interval between interrupt signals generated upon the occurrence of a specified count of clock cycles of the clock signals emanating from the crystal oscillator.

Abstract: A card reader located in proximity to the central point of the secured area having a crystal controlled time base clock. Entry is granted when the proper information is entered to the card reader through a keypad or identification card. The clock is adjusted under software control according to a selected offset signal. The card reader is operable to provide access control of a secured area according to a schedule operable relative to the card reader clock without external reference signals.

Abstract: An apparatus and method that provides an auxiliary timing source for electronic clocks, normally powered by alternating current (ac). The apparatus and method includes calibrating an inexpensive resistor-capacitor oscillator, powered by a battery. The oscillator is calibrated during normal ac operation by comparing a digital timing pulse derived from the oscillator and a digital timing pulse derived from the alternating current. When a power failure occurs, the calibrated oscillator provides an inexpensive and accurate auxiliary timing source. The apparatus and method may also include a non-volatile solid-state storage medium for storing the time of day and a set of timing instructions in the event that the battery becomes drained.

Abstract: Variations, due to aging, of resonant frequency characteristics of electromechanical resonators are compensated by an oscillator including the resonantor. An indication of the amount of time that the oscillator is operating addresses a table of values indicative of the manner in which the oscillator changes frequency as the resonator ages. From the table of values a signal having a value indicative of a correction factor for the resonator aging is derived. The frequency of the oscillator is controlled in response to the value of the correction factor. The table of values is stored in a re-programmable memory. The values stored in the memory are corrected by comparing the oscillator frequency with a standard frequency.

Abstract: To compensate for frequency variation in the quartz oscillator 4, 6 due to temperature variation, a second quartz oscillator 12, 14 forming a thermal sensor is employed. The beat frequency fB (circuit 16) which is counted in the counter 26 for a period of time T.sub.1 gives a measurement corresponding to temperature. The number which is thus counted is raised to its square and by means of the comparator 30 taken away from the pulses counted by the divider 8 with a periodicity T.sub.T. The system may be used to provide temperature compensation for a time keeping quartz time base.

Abstract: Time sharing of a processor in a timepiece allows for performance without interference of a plurality of functions including timekeeping and supplemental functions. An electronic timepiece includes an oscillator for producing a time-standard high frequency signal, temperature detecting means, the processing unit, a display means and at least one dedicated memory for compensating for the effect of temperature on the frequency of the oscillator. In addition, memories are provided for compensating for the aging characteristics of the oscillator and the temperature-detecting means. Manually-actuatable input switches provide for carrying out changes in the temperature-compensating data as the oscillator and the temperature-detecting means age. These switches also make it possible to use the circuitry for calculation. Preferably, the frequency generated by the oscillator is an integer multiple of 10 Hz and dividers are provided for dividing the frequency down to 0.

Abstract: In a circuit arrangement for adjusting a pulse frequency of a quartz-controlled clock or watch there are present a pulse generator, a multi-stage frequency divider arranged behind said pulse generator and in front of a counter, as well as adjustable means for adding clock pulses in front of at least one predeterminable frequency divider stage during a counting cycle, and adjustable means for subtracting a clock pulse between a frequency divider stage of higher frequency and a frequency divider stage of lower frequency in a counting cycle. The higher-frequency frequency divider stages are developed as fixed, pre-settable counters, and between the pre-settable counter and the next following frequency divider stage the adjustable means for subtracting a clock pulse are arranged. In this way the current consumption of the circuit arrangement can be kept small since its elements oscillate only with a relatively low frequency.

Abstract: A multi-mode electronic timepiece includes a case body on which an annular dial is mounted for angular stepwise displacement. A circuit board is mounted within the case body and includes a plurality of angularly spaced-apart switch terminal patterns connected to circuitry for generating different mode signals depending on which of the switch terminal patterns are actuated. A plurality of switches are disposed adjacent respective ones of the switch terminal patterns and each switch includes a movable rod movable between first and second positions to actuate or not actuate its respective switch terminal pattern. The underside of the annular dial is provided with a plurality of angularly spaced-apart camming portions which are suitably located to cam the switch rods in response to manual angular stepwise displacement of the dial to actuate selected ones of the switches to accordingly actuate selected ones of the switch terminal patterns and produce a corresponding mode signal.

Abstract: A timekeeping signal source for an electronic timepiece produces a highly accurate timekeeping signal which is stable in frequency with respect to both temperature variations and long-term drift. The timekeeping signal is produced by phase lock control using a high frequency reference signal from a crystal-controlled high-frequency oscillator. Phase lock control can be performed continuously or on an intermittent basis, in order to reduce power consumption. In addition, the timekeeping rate can be adjusted with a resolution within one period of the high frequency reference signal, by variation of a numeric value stored in digital memory means.

Abstract: Electronic clocks with analog time displays and a vibrating quartz crystal (1) as a time standard, as well as electronic frequency dividers (6, 7). The display elements are driven by an electronically controlled motor (SM), said motor comprising a power winding (87) and a control winding (68). The control and regulating circuit for the electronically controlled motor (SM) is so designed that only one rpm above the rated rpm is controllably adjustable and, when the frequency of the clock varies, correcting signals are supplied to the AC drive pulses in power winding (87) through a bistable flip-flop (50), said flip-flop being subjected to real pulses derived from frequency dividers (6,7) and pulses derived from motor (SM), a NOR element (58) connected to the output of flip-flop (50) and an additional frequency divider (59), a field effect transistor (88), and a resistor (89).

Abstract: An electronic timepiece comprising a rate correction circuit for modifying the number of time base pulses received by the frequency divider during a predetermined period of time by a predetermined number of correction pulses. The rate correction circuit is arranged to divide said period of time into a given number of sub-periods and to distribute correction pulses substantially and equally over these sub-periods.

Abstract: A method and apparatus for correcting errors in an electronic digital timepiece that includes an oscillator which has a 2.sup.n frequency output, an n-stage frequency divider for reducing the oscillator output frequency to a time keeping frequency, and means for displaying the count of the time keeping frequency. The error E in the time of the timepiece for an arbitrary period of time T is determined. A computer computes a new adjustment value N+(2.sup.n-m +N)E/T where N is the preceding adjustment value and m is a nonnegative integer less than n. Then the 2.sup.n-m divisor of the first n-m stages of the n-stage frequency divider is adjusted in an amount equal to the new adjustment value. In first and second embodiments of the invention the timepiece is synchronized with a time standard at the beginning of the period of time T.

Abstract: An electronic wristwatch wherein a timing rate adjustment signal, representative of the amount of timing rate adjustment being effected and/or needed to be effected, is depicted. The electronic wristwatch includes a divider circuit for receiving a high frequency time standard signal from a quartz crystal oscillator circuit and for producing a low frequency timekeeping signal in response thereto. An adjustment circuit is coupled to the divider circuit for adjusting the frequency of the timekeeping signal by a predetermined amount. A converter circuit is adapted to be selectively coupled to the divider circuit to receive the adjusted low frequency timekeeping signal and, in response thereto, to produce a timing rate adjustment signal representative of the amount of adjustment applied in the low frequency timekeeping signal, and to produce a signal representative of the unadjusted oscillator frequency.

Abstract: In order to determine the adjustment precision .DELTA.T of a timepiece provided with an oscillator (1) and an adjustable frequency divider chain (3-18; 18-20) on which an adjustment unit (15) acts, initially the real period TQ of the oscillator is measured with the adjustment unit disconnected following a first actuation of a time setting circuit (21). A second actuation of said circuit then effects running of the display at a rate n times above the normal and the adjustment unit is connected. Following a time T/n representing the adjustment cycle the period TQ is measured as corrected by the amount n.DELTA.T, thus TQ+n.DELTA.T. The first measured value obtained is subtracted from the second thus giving n.DELTA.T which when divided by n gives the adjustment precision .DELTA.T.

Abstract: An absolute digital clock system which is capable of counting absolute time despite the disruptive effects of a nuclear event, or other disturbance, on the electronic circuitry of the system. The clock system of the invention includes a master quartz crystal oscillator stage, and a string of counter stages connected thereto each including a binary counter for counting down from the frequency of the preceding stage to a lower frequency, and each including a crystal oscillator phase-locked with the binary counter and producing a signal at the lower frequency.

Abstract: An electronic timepiece comprising means to appreciably increase the number of distinctive information which can be introduced and, if necessary memorized, for a given number of terminals intended for that purpose, information needed for the adjustment of the frequency. The integrated circuit of the timepiece is provided with a first group of m terminals and it comprises an introduction circuit having inputs reserved to introduce the desired information, these inputs being connected to a second group of n terminals of the integrated circuit. The introduction circuit has also control inputs and each of the n terminals of the second group is capable to be connected, by a connection external to the integrated circuit, with one of the m terminals of the first group. The introduction circuit is arranged in such a way as to deliver to its outputs, at least periodically, one distinctive information for each of the m.sup.n possible combinations of the mentioned connections.

Abstract: A quartz crystal wristwatch is temperature compensated by applying additional pulses to the divider circuit. The number and frequency of application of the additional pulses is stored in memory and based upon mean temperature data for the worn wristwatch on an hourly or monthly basis. The oscillator itself uses little or no temperature compensation.

Abstract: An electronic timepiece comprising a fundamental frequency oscillator, a plurality of frequency divider stages, a timekeeping mechanism and display, includes circuitry for resetting and setting selective stages of the divider and thereby adding or subtracting timing pulses which are delivered to the timekeeping mechanism. A non-volatile memory stores data which terminates whether a divider stage is to be set or reset. Additionally, a plurality of circuit elements are selectively inserted to modify the circuit of the oscillator and to provide frequency adjustment. External contacts are provided for the inputting of data to memory and for measuring timing rate against an external standard.

Abstract: An electronic timepiece includes a frequency supply for providing a relatively high frequency time base signal, a frequency converter responsive to the time base signal to provide a relatively low frequency time unit signal, and timekeeping means responsive to the time unit signal to provide current time information. The current time information is corrected and displayed. A calculation command signal is generated and enables a circuit means to produce, in response to the time unit signal, a frequency error signal indicative of an error in the frequency of the time unit signal. A gain/loss adjustment signal is generated in response to the frequency error signal, and a frequency adjusting circuit is provided for adjusting the frequency of the time unit signal in response to the gain/loss adjustment signal.

Abstract: A method and apparatus for adjusting the frequency of a piezoelectric crystal oscillator. The effective frequency of the oscillator is adjusted (trimmed) by periodically inhibiting pulses to the divider stage.The pulse inhibit circuit includes a nonvolatile programmable read-only-memory (ROM) to store binary complement information corresponding to the number of oscillator pulses to be suppressed.A counter is periodically preset with the binary complement information and the count advances in response to oscillator pulses. The difference count between the complement number and the counter's maximum count controls the number of pulses periodically suppressed.

Abstract: A method and apparatus for adjusting the frequency of piezoelectric crystal oscillator. The effective frequency of the oscillator is adjusted (trimmed) by periodically inhibiting pulses to the divider stage.The pulse inhibit circuit includes a nonvolatile programmable read-only-memory (ROM) to store binary complement information corresponding to the number of oscillator pulses to be suppressed.A counter is periodically preset with the binary complement information and the count advances in response to oscillator pulses. The difference count between the complement number and the counter's maximum count controls the number of pulses periodically suppressed.During manufacture/assembly of the timepiece, the ROM is programmed to contain the desired complement information.

Abstract: A semiconductor temperature compensation circuit for an electronic timepiece is provided. The temperature compensation circuit is characterized by a temperature detection circuit comprised of MOS transistors, at least two of which have distinct conductive coefficients for producing signals representative of variations in ambient temperature and a temperature signal converting means including MOS transistors for converting the temperature dependent signal into a temperature compensation value for effecting timing rate adjustment in an electronic timepiece. The temperature detection circuit and the temperature signal converter circuit are both formed of elements that can be monolithically integrated into the same substrate.

Abstract: An electronic timepiece adapted to perform time correction in response to a train of time correction pulses transmitted from another electronic timepiece. The electronic timepiece comprises a detecting means to detect the train of time correction pulses; a writing-in signal generator circuit to generate writing-in signals in synchronism with a synchronizing signal contained in the train of time correction pulses, and a writing-in gate circuit means to perform writing-in of the train of time correction pulses into a timekeeping circuit of the timepiece as new current time data in response to the writing-in signals.

Abstract: In an electronic timepiece, a system for producing a unit time signal with a high degree of frequency stability, composed of a low frequency oscillator, a high frequency oscillator of a high degree of frequency stability which is activated only during periodic short intervals, and means for producing a timebase signal which is an exact integral submultiple in frequency of the high frequency oscillator signal, by modifying the output signal from the low frequency oscillator on the basis of periodically recurring phase coincidence between the high and low frequency oscillator signals. Information on this phase variation is stored in digital form, and is utilized to correct the low frequency signal during periods when the high frequency oscillator is inactivated.

Abstract: A system for correcting the accuracy of a reference signal in an electronic timepiece comprises an electronic timepiece including a reference signal frequency correction means for increasing or decreasing the reference signal frequency in a digital fashion with the use of a low frequency signal, and a quartz tester arrangement for measuring the accuracy of the reference signal frequency. The quartz tester arrangement indicates the displacement of the reference signal frequency from the standard signal frequency with the use of five lamps, each of which is selected to be enabled in accordance with the detected value of the displacement. The reference signal frequency correction means in the electronic timepiece includes five manually operable switches corresponding to said five lamps and functions to increase or decrease the reference signal frequency in a digital fashion in response to the closing of the switches corresponding to the enabled lamps.

Abstract: A clock system is disclosed having two identical clocks not synchronized with each other. Each of the clocks includes a circuit for selecting the output of one of the clocks as the present system output. Further, each clock includes logic for detecting errors in the operation of itself, and of the other. When an error is detected in the operation of the clock selected to be the present system output, a switchover sequence control switches the output signal of the nonselected clock to become the new system output. The switchover sequence control includes a feature which ensures that the interval between pulses in the system output is greater than a predetermined period in order to minimize detrimental effects on circuitry utilizing the clock system output.

Abstract: An electronic timepiece having a high frequency oscillator with a high level of frequency stability and an electronically controlled low frequency oscillator. The phase of a high frequency signal from the high frequency oscillator is compared with a signal from the low frequency oscillator, and a digital signal is produced in accordance with the phase difference. The digital signal alternately controls the frequency of the low frequency signal to be slightly greater than an exact submultiple of that of the high frequency signal and slightly less that an exact submultiple of the high frequency signal, so that with respect to a relatively long time interval the frequency of the low frequency signal is an exact submultiple of that of the high frequency signal, the low frequency signal being thereby utilizable as a timebase signal for the timepiece.

Abstract: An electronic timepiece displaying both the time and the temperature. A tsducer which may take two positions is provided to reach this result: the first position incorporates the transducer within the timepiece and allowing the correction of the frequency drift of the time base which determines the time the second position projecting the transducer out of the timepiece case in order to measure, for example, the temperature of the ambient air. There is also provided an automatic switching system which adapts the transducer to the frequency correction or to the temperature measurement depending on the position of said transducer.

Abstract: A frequency adjusting circuit for digitally adjusting the frequency of a time reference signal consisting of a series of pulses is disclosed. The circuit function to adjust the frequency of said series of pulses by subtracting or adding a given number of pulses from or to said series of pulses for a time set beforehand every time upon receipt of a predetermined number of pulses of said time reference signal.

Abstract: A time adjusting device for an electronic timepiece utilizes a manually rotatable mechanism which generates pulses corresponding in frequency and number with the speed and extent of rotation thereof. Each pulse which is generated is thereafter converted into a plurality of pulses. A manually actuatable switch applies either the normal periodic time pulses to a time counter or the plurality of pulses to the time counter upon actuation to adjust the time count therein.

Abstract: Time adjusting means for electronic timepiece which detects change in the generation condition of pulses generated in response to a manual operation speed and generates a predetermined number of pulses in accordance with the detection output as the time-adjusting pulses. The time adjusting means enables a rapid time adjustment of an electronic timepiece at a high speed. When the manual operation speed exceeds a predetermined speed, the time adjusting means stops the time-adjusting pulse so as to prevent erroneous operation.

Abstract: An integrated circuit pulse generator which may be externally digitally conditioned to provide an output signal at a frequency falling within a predetermined range of signal frequencies corresponding to a specified frequency tolerance includes a fixed frequency oscillator having an external frequency determining crystal which provides electrical pulses at a fixed frequency that is within a given range of frequencies above a nominal frequency. A pulse inhibit means coupled to the fixed frequency oscillator includes a plurality of programmable input terminals and cyclically inhibits selectable numbers of the electrical pulses responsive to selective actuation of the programmable input terminals to controllably transform the fixed frequency in delta amounts to an output signal frequency within the predetermined range of frequencies.