Abstract: A data communication system includes a plurality of mutually-disjoint sets of switches, each set including multiple mutually-disjoint subsets of the switches in the set. Local links interconnect the switches within each of the subsets in a fully-connected topology, while none of the switches in any given subset are connected in a single hop to any of the switches in any other subset within the same set. Global links interconnect the sets of the switches, each global link connecting one switch in one of the sets to another switch in another one of the sets, such that each of the subsets in any given set of the switches is connected in a single hop by at least one global link to at least one of the subsets of every other set of the switches.

Abstract: Dynamic fabric systems and methods are disclosed for providing connections between endpoints of a communication network. An exemplary dynamic fabric system can include backplane lanes, a dynamic fabric device, and a control device. The dynamic fabric device can include local fabric lanes and a network interface device configurable to communicatively connect the local fabric lanes to a network. The dynamic fabric device can also include a local switch configurable forward messages to backplane lanes and an interconnect configurable to statically connect local fabric lanes and corresponding backplane lanes. The dynamic fabric device can also include a controller configurable to create or break these static connections. The control device can provide instructions to the dynamic fabric device to create or break the static connections based on changes in the number of active dynamic fabric devices installed in the dynamic fabric system.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: An aspect of module mirroring during an non-disruptive upgrade includes creating a mirrored set of management processes for a storage cluster that is subject to an upgrade a new software version, interconnecting components of the mirrored set and an original set of the management processes while the storage cluster is actively managed by an original set of management processes, and performing a handover between the management processes of the storage cluster.

Abstract: A method for processing packet data in a service provider environment includes, by a network-enabled data processing device within a server computer of the service provider environment, receiving packet data comprising header information and payload information. The header information is separated from the payload information. The separated header information is forwarded to a processor of the server computer for processing, without forwarding at least a portion of the payload information. At least one address of a storage location is received from the processor. The at least one address is associated with a logical-to-physical address mapping based on the header information. The payload information is stored in the storage location based on the at least one address.

Abstract: A method of encoding audio channels includes receiving two or more channels at an encoder and identifying a target channel and a reference channel. The target channel and the reference channel are identified from the two or more channels based on a mismatch value. The method also includes generating a modified target channel by temporally adjusting the target channel based on the mismatch value. The mismatch value is indicative of an amount of temporal mismatch between the target channel and the reference channel. The method also includes determining a temporal correlation value indicative of a temporal correlation between a first signal associated with the reference channel and a second signal associated with the modified target channel. The method also includes comparing the temporal correlation value to a threshold. The method further includes generating missing target samples based on the comparison, a coder type, or both.

Abstract: A bump-in-the-wire time code signal decoder and debugger apparatus includes a controller structured and configured to: receive an encoded time code signal, decode the encoded time code signal, and produce a parsed signal based on the decoding of the encoded time code signal. The apparatus also includes a communications interface coupled to the controller, wherein the communications interface is structured to receive the parsed signal and generate an output signal based on the parsed signal.

Abstract: An apparatus includes an input port group, which includes multiple input slots, and multiple input ports are provided in each input slot. An input allocation matrix includes multiple first optical switches, and an input port of the first optical switch is connected to an input port of the input slot. A cross-connect matrix includes multiple second optical switches, and an output port of the first optical switch is connected to an input port of the second optical switch. An output allocation matrix includes multiple third optical switches, and an input port of the third optical switch is connected to an output port of the second optical switch. An output port group includes multiple output slots, multiple output ports are provided in each output slot, and an output port of the output slot is connected to an output port of the third optical switch.

Abstract: Systems and methods for systematic hybrid network scheduling for multiple traffic classes with host timing and phase constraints are provided. In certain embodiments, a method of scheduling communications in a network comprises scheduling transmission of virtual links pertaining to a first traffic class on a global schedule to coordinate transmission of the virtual links pertaining to the first traffic class across all transmitting end stations on the global schedule; and scheduling transmission of each virtual link pertaining to a second traffic class on a local schedule of the respective transmitting end station from which each respective virtual link pertaining to the second traffic class is transmitted such that transmission of each virtual link pertaining to the second traffic class is coordinated only at the respective end station from which each respective virtual link pertaining to the second traffic class is transmitted.

Abstract: An engine system may include a specified number of injectors and an engine control unit (ECU) having pins to which the injectors may be coupled. The ECU may include a controller implemented in hardware, software, or combination of both, and capable of switching between different multiplexing configurations, where each multiplexing configuration includes a specified number of individual injectors coupled across corresponding pairs of pins. The controller may select one multiplexing configuration from the number of specified multiplexing configurations without requiring any hardware adjustments to be made to the injectors and/or pins. The controller may also operate the individual injectors through the corresponding pairs of pins in an active multiplexing configuration selected by the controller.

Abstract: In one embodiment, a method of photonic frame scheduling includes receiving, by a photonic switching fabric from a top of rack (TOR) switch, a frame request requesting a time slot for switching an optical frame to an output port of a photonic switch of the photonic switching fabric and determining whether the output port of the photonic switch is available during the time slot, and generating a contention signal including a grant or a rejection, in accordance with the determining. Also, the method includes assigning the time slot to the TOR switch for the output port of the photonic switch, when the contention signal includes the grant, transmitting, by the photonic switching fabric to the TOR switch, the contention signal and receiving, by the photonic switching fabric from the TOR switch, the optical frame during the time slot, when the contention signal includes the grant.

Abstract: One wireless telecommunications system includes a Mobile Central Office (MCO) for capacity sharing. The MCO is communicatively coupled to a plurality of wireless base stations, each being operable to handle a session from a wireless device and to handoff the session to another base station when the wireless device moves into a range of the other base station. The MCO is operable to detect capacity on a base station to which it is coupled, to request capacity for the base station from a remotely located master scheduling system, to acquire at least a portion of the requested capacity from a base station of another MCO based on the request to the master scheduling system, to handle another session of another wireless device via the acquired capacity, and to release the acquired capacity to the master scheduling system when the first base station has completed use of the acquired capacity.

Abstract: A network device may include first logic configured to count data units passing through the network device and to produce a counter value. The network device may include second logic configured to receive the counter value when an indicator is present, and to store the counter value. The network device may include third logic configured to sample the second logic, to receive the counter value, and to operate on the counter value to produce a result.

Abstract: The subject matter disclosed herein relates to communication between a client and a server in a communications network. In one particular example, a server is selected from a plurality of servers to provide a resource and/or a service to a client.

Abstract: A network apparatus, for processing a network signal and outputting an output signal, includes an asynchronous signal processing module, a sampling rate converter and a synchronous signal processing module. The asynchronous signal processing module operates in an asynchronous domain, and is utilized for receiving and processing the network signal to generate a first processed signal. The sampling rate converter is coupled to the asynchronous signal processing module, and is utilized for performing sampling rate conversion on the first processed signal to generate the output signal. A first operating frequency of the asynchronous signal processing module is different from a second operating frequency of the synchronous signal processing module.

Abstract: The present invention relates to a method and apparatus for reducing the resource utilization of the switching fabric in a SONET/SDH multiplexer by switching data on a TU level instead of byte or column level.

Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Abstract: A base station allocates, when receiving a first code included in a predetermined code group from a first mobile station, a wireless resource in a first communication region corresponding to the first code, to the first mobile station, and allocates, when receiving a second code not included in the predetermined code group from a second mobile station, a wireless resource in a second communication region corresponding to the second code, to the second mobile station.

Abstract: A transmission apparatus stores frame data of a first frame in a second frame having a bit rate different from that of the first frame through regulation of the amount of stuffs to be stored in the second frame. The transmission apparatus includes: a storage unit storing the first-frame frame data; a first control unit controlling a timing of writing the first-frame frame data in the storage unit based on first stuff information indicating the amount of stuffs contained in the first frame; an arithmetic and logic unit obtaining second stuff information indicating the amount of stuffs to be contained in the second frame based on a bit rate ratio between the first frame and the second frame; and a second control unit controlling a timing of reading out the first-frame frame data stored in the storage unit based on the second stuff information.

Abstract: Aggregation Switches connected via a virtual fabric link (VFL) are each active and each coupled to a multi-chassis link aggregate group (MC-LAG), which is assigned to a multi-chassis link aggregate group virtual local area network (MC-LAG VLAN). A virtual Internet Protocol (IP) interface is allocated to the MC-LAG VLAN and configured on both Aggregation Switches.

Abstract: A wireless base station device includes a wireless unit for performing wireless communications with a mobile station; a reception memory unit for storing therein reception spectrum spread data as reception data; a baseband reception unit for processing and decoding the reception data stored in the reception memory unit; a common downlink channel reception unit for receiving a downlink signal of other base station devices; a frame protocol processing unit for converting a transmission channel format; a baseband transmission unit for outputting encoded data; a spread processing unit for outputting spread-modulated data to the wireless unit; and a call controller for controlling an allocation of processing resources. Parameters including a spreading code and a transmission power required for installing the wireless base station device are automatically set by operating the common downlink channel reception unit to detect notification information and signal levels of neighboring base station devices.

Abstract: Systems and methodologies are described that provide support for signal acquisition in wireless communication systems that utilize half-duplex communication in the presence of asynchronous sectors. Forward link and reverse link superframes can be structured such that a given frame position in a superframe alternates between forward link communication and reverse link communication for a particular half-duplex interlace. More particularly, an odd number of frames can be grouped into respective forward link and reverse link superframes, from which frames can be assigned to a first half-duplex interlace and a second half-duplex interlace in an alternating fashion. By varying the communication link used by a half-duplex interlace at a given frame location, terminals operating on a single half-duplex interlace can detect asynchronously operating sectors irrespective of the transmission timeline of such sectors.

Abstract: A communication system (100) transmits data packets from a sender (120A) to a receiver (130A) using hybrid automatic repeat request processes. The sender redundantly encodes each packet, divides the packet into subpackets, and sends the subpackets to the receiver in a time-interlaced manner. When the receiver returns a positive acknowledgement of a subpacket using an acknowledgement channel, the sender terminates transmission of the subpackets. The sender interprets the signals on the acknowledgement channel using a metric resulting from correlation of the signals with positive and negative acknowledgement symbols. The sender interprets low correlation of the acknowledgement channel signal with both positive and negative acknowledgement symbols as a preamble miss, and terminates transmission of the subpackets. After termination, the packet may be rescheduled for transmission.

Abstract: A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Abstract: A packet communication device for communicating a packet to be transferred in constant cycle, comprising one of a logic inversion section configured to invert a logical value with respect to at least one bit included in a first string of bits included in a first packet; and a register section configured to store another string of bits having a logical value different from a given logical value of the first string of bits; and a selector section configured to select one of the first string of bits and a second string of bits that is output from one of the logic inversion section and the register section to designate any one of a plurality of devices, wherein the packet communication is performed when a selected string of bits selected by the selector section conforms to a setting value of a receiving side.

Abstract: A packet relay apparatus for suppressing a burst transfer of packets being relayed to improve the quality and reliability of packet communication. In the packet relay apparatus, an arrival time measurement block measures the arrival time of an input packet to generate arrival time information; a packet classification block classifies the packet as an output-interval-control packet, which requires output interval control, or a non-output-interval-control packet, which does not require output interval control, to generate classification information; a packet distribution block receives the packet which has been processed and switched and places the packet in an appropriate queue according to the classification information; and a schedule management block performs relay output control in accordance with the arrival time information such that the output intervals of output-interval-control packets become equal to the input intervals obtained when the packets were input to the apparatus.

Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.

Abstract: An improved method and system for removing operating restrictions associated with a predetermined subscriber identity module (SIM) from a wireless device. A user is allowed to securely log onto a Web site that contains support information on subscription plans, billing, termination, penalties, and device-to-SIM unlocking. After satisfying any outstanding contract terms and payment of termination or device unlock fees, the user initiates a device-to-SIM unlock procedure. A client application on the wireless device securely transfers subscription, system, and SIM information to a device-to-SIM unlock system which uses the information to generate appropriate unlock codes. The unlock codes are then securely transferred to the client application, which processes them to remove operating restrictions associated with the predetermined SIM from the device and allow it to thereafter implement a plurality of SIMs.

Abstract: A method for processing overheads in an optical communication system and a signal processing device are disclosed. The method includes: in a receiving direction, conduct an O/E and S/P conversion for the received optical signal, extract overheads necessary for overheads processing; transmit the overheads in serial; conduct an S/P conversion of the overheads, add fixed reserved overheads, and revert the parallel overheads for overheads processing; in a transmitting direction, generate parallel overheads, extract overheads necessary for overheads processing; transmit the overheads in serial; conduct an S/P conversion of the overheads, revert the overheads, synthesize the overheads with the payload data before the P/S and E/O conversion, and generate and transmit the optical signal. In accordance with the disclosed method and device, a serial bus is employed to transmit overheads, which reduces the number of buses on the motherboard and lowers the complexity of system design.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: The invention provides methods and systems for channel estimation. A method comprises receiving a plurality of signal frames, comprising at least a first zone and a second zone, from a plurality of base stations in the wireless communication system. Two or more first delay profiles corresponding to two or more base stations are determined using the first zone. The method further comprising detecting at least one aliased tap in a time domain channel response of the second zone using the two or more first delay profiles. Another method comprises receiving a signal frame, comprising at least a preamble symbol and a data part, from a base station. A first delay profile corresponding to the preamble symbol is determined and a second delay profile corresponding to the data part is obtained. The first delay profile is analyzed in conjunction with the second delay profile to detect one or more aliased taps in a time domain channel response of the data part. The detected one or more aliased taps are nulled/rectified.

Abstract: A method, core node, ingress edge node, and egress edge node for matching a bit rate of data input into an optical burst switching network with that of data output from the optical burst switching network are provided. The method includes calculating a difference between a frequency of optical data received on a node and a natural frequency of the node; including the calculated difference into control information; and transmitting the control information. The core node includes a calculator to calculate a difference between frequency of optical data and the natural frequency of the optical data; and a controller to add the difference and a difference included in control information, and output the added difference. The ingress edge node includes a data processor; and a controller. The egress edge node includes an ingress edge node clock recovery phase lock loop; a de-mapper; and a storage unit.

Abstract: A transit memory assembly of a rotator-based switching node is logically partitioned into two sections, one operated as a common-memory switch fabric and the other as a time-shared space-switch fabric. The composition of data received at input ports of the switching node determines adaptive capacity division between the two sections. Based on an indication of traffic type, a controller of at least one input port selects one of the two sections. The space-switch section enables scalability to a high transport capacity while the common-memory section enables scalability to a high processing throughput. The switching node includes rotators and a bank of transit-memory devices that facilitate the incorporation of any mixture of periodic, aperiodic, contention-free exclusive-access, concurrent-access, and multicast switching.

Abstract: A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.

Abstract: A system for supplying streaming media or other media sources to clients, where said system minimizes the lag time perceived by the user during negotiation between media sources by outputting the media content remaining in the buffer while the system is negotiating connection and buffering information from a second media source.

Abstract: An apparatus and method for adjusting a receiving time point of burst data in an optical burst switching network is provided. The method includes comparing a reference time point of a node with a time slot boundary of the burst data; and adjusting the time slot boundary of the burst data in accordance with the reference time point. The apparatus includes a sync detection section which is configured to detect a difference between a time slot boundary of the burst data and a reference time point; and a sync control section which is configured to control shifting and re-aligning the received burst data with the reference time point according to the difference detected by the sync detection section.

Abstract: A packet-oriented cross-connect system is provided. Included is a first channel interface configured to receive a first data packet stream and transfer the first data packet during a first set of time slots to a channel connection employing time-division multiplexing. A second channel interface is configured to receive the first data packet stream from the channel connection. A third channel interface is configured to receive a second data packet stream and transfer the second data packet stream during a second set of time slots over the channel connection. Also, a fourth channel interface is configured to receive the second data packet stream from the channel connection. A test device is also included which is coupled to the channel connection and configured to receive and analyze a portion of the first data packet stream and a portion of the second data packet stream.

Abstract: The invention relates to a cluster coupler in a time triggered network for connecting clusters operating on the same protocol. Further, it relates to a network having a plurality of clusters, which are coupled via a cluster coupler. It also relates to a method for communicating between different clusters.

Abstract: A high capacity switching node comprises a lattice structure of low-latency switch units and a plurality of balanced connectors interfacing electronic edge nodes to diagonal subsets of said switch units. The edge nodes may be collocated with the switch units or remotely located. The switch units may be bufferless, having optical switch-fabrics for example, thus requiring a compound vacancy-matching process. Using switch units each of dimension 64×64, a fast switching node having a dimension of the order of 10,000×10,000 can be constructed. With a typical wavelength-channel capacity of 10 Gb/s, the fast-switching node would scale to a capacity of 100 terabits per second, which is orders of magnitude higher than the capacity of known fast optical switches. A fast-switching optical switch of such scalability significantly reduces network complexity and cost.

Abstract: A method of improving frequency diversity of a signal that includes a plurality of orthogonal frequency division multiplexing (OFDM) symbols comprises receiving an input data sequence, mapping the input data sequence to a transmission data sequence, wherein the mapping includes performing a mapping operation and generating an OFDM symbol using the transmission data sequence. An orthogonal frequency division multiplexing (OFDM) transmitter comprises an interface configured to receive an input data sequence, and a processor configured to perform a mapping operation, to map the input data sequence to a transmission data sequence wherein the mapping includes performing the mapping operation, and to generate an OFDM symbol using the transmission data sequence.

Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract: A high capacity distributed switching system comprises electronic edge nodes connected to a balanced bufferless switch which may be electronic or optical. The balanced bufferless switch comprises a balanced connector and a switch fabric. The balanced connector comprises an array of temporally cyclic rotator units having graduated rotation shifts and each having a prime number of output ports. The switch fabric may be a mesh interconnection of switch modules. Due to the use of the balanced connector, establishing a path through the switch fabric requires at most a second-order time-slot matching process for a high proportion of connection requests with a much reduced need for a third-order time-slot matching process required in a conventional mesh structure.

Abstract: A method and apparatus for flexible sharing of bandwidth in switches with input buffering by dividing time into a plurality of frames of time slots, wherein each frame has a specified integer value of time slots. Counters associated with the input-output queues of the switches are loaded with a negotiated integer value once per frame. The inputs sequentially select available outputs to which the inputs send packets in specified future time slots. Priority is given to input-output queues with counters having positive values. The selection of outputs by the inputs is done using a pipeline technique and a schedule is calculated within multiple time slots. The counters for selected queues are then decremented by 1.

Abstract: The invention provides apparatus methods for avoiding channel collisions in Wireless Regional Area Networks (WRAN), A medium access controller (MAC) for switching a base station (BS) of a WRAN from a first channel to a second channel at a time t is provided. The MAC includes a switch time delay circuit for delaying said switching with respect to time t by a random delay time.

Abstract: An integrated circuit comprises a plurality of data processing circuits (10) and a communication network (12) coupled between the data processing circuits (10). The communication network (12) comprises connections (122) and router circuits (120) coupled between the connections (122). Memory is provided to store definitions for respective data streams, of respective paths along the connections (122), for controlling the router circuits (120) to transmit each data item from each respective data stream along the respective path programmed for that respective data stream. Initially initial paths for a set of original data streams are defined and started. Subsequently an additional data stream can be added. If so a new path is selected in combination with future paths for the original data streams.

Abstract: A service option overlay for a CDMA wireless communication in which multiple allocatable subchannels are defined on a reverse link by assigning different code phases of a given long pseudonoise (PN) code to each subchannel. The instantaneous bandwidth needs of each on-line subscriber unit are then met by dynamically allocating additional channel capacity on an as needed basis for each network layer connection. The system efficiently provides a relatively large number of virtual physical connections between the subscriber units and the base stations on the reverse link for extended idle periods such as when computers connected to the subscriber units are powered on, but not presently actively sending or receiving data. These maintenance subchannels permit the base station and the subscriber units to remain in phase and time synchronizm by monitoring power, carrier-to-interference (C/I), or signal-to-noise (SNR) ratios. The power levels over the subchannels is regulated to minimize interference.

Abstract: A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data stream carrying tributary payloads from an external input link that are capable of being individually switched in space and time. A write controller causes input columns of the input data stream to be written to a common buffer according to a write pointer. In parallel, a read controller causes the input columns to be read from the common buffer to output columns of an output data stream according to a read pointer. For each of the output columns, the read pointer selects an input column from a limited portion of the buffer that contains a set of the input columns that are capable of being switched in time to the corresponding output column according to a communication protocol.

Abstract: In accordance with at least one embodiment, fixed TDM slot/frame structure and statistical multiplexing are combined. A TDM slot, which is fixed (in size and position) is reserved for a variable bit rate service such that the bit rate of the TDM slot/channel is below the average rate of the service. Such a reserved TDM slot may be referred to as a service specific slot. Since the service specific slot is reserved with a bit rate below the average rate of the service, additional capacity is reserved from a rate matching slot, which may be common for multiple services. In this rate matching slot, the capacity may be shared between services according to any suitable strategy for allotting services to portions of the rate matching slot, including, but not limited to, a statistical multiplexing algorithm.

Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.