Abstract: An efficient distributed architecture for forwarding packets. The packet to be forwarded arrives in an ingress port, is processed by an ingress forwarding engine, transferred to an egress forwarding engine, and then transmitted via an egress port. An address-based lookup at the ingress forwarding engine identifies the correct egress forwarding engine and also identifies a translation index specifying the forwarding equivalence class (e.g., combination of address prefix and mask) of the packet. The egress forwarding engine then uses the translation index as a memory pointer to recover adjacency information with which to rewrite the packet header. The egress forwarding engine may maintain its adjacency information entirely locally without the need to share the information or propagate updates to ingress forwarding engines. This approach results in a scalable and highly efficient packet forwarding architecture.

Abstract: A multi-probe lookup table includes an indication of the congestion level of each addressable location. A key can be stored in one of a plurality of indexed locations in the lookup table. Thrashing is reduced by inserting keys into the lookup table based on the distribution of keys already stored in the lookup table. Insert operations for all keys sharing an indexed location are recorded by modifying a swap count indicating the congestion level of the indexed location each time a key is inserted in one of the indexed locations.

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: A look-up table (LUT)-based arbitration (LTA) system and methodology for use in a network switch element. Input control signals generated by ingress and egress entities associated with a cross-connect matrix of the network switch element are encoded into address information that is used for interrogating a storage structure. Pre-computed arbitration results based on a select arbiter scheme are stored into fields associated with the storage structure. When a particular input combination is applied with respect to an arbitration iteration, a selected arbitration result is obtained by querying the appropriate field, which is then decoded into a corresponding selected entity for the arbitration iteration.

Abstract: An apparatus and a method for controlling memory in a base station modem supporting multi-users including a memory divided into logical blocks for supporting the multi-users, and a controller for allocating the memory blocks dynamically in hardware. This allows non-continuous memory allocation and the size of memory can be increased or reduced during operation through the dynamic allocation structure of the memory.

Abstract: An in-order state queue holds store tags as in-order information about store instructions. A temporal store cache, which uses store addresses as indexes, holds store tags and store values. A first retrieving unit retrieves store tags preceding a load tag. A second retrieving unit compares the store tag read from the temporal store cache according to the address for the load instruction with the store tag from the first retrieving unit and, when they coincide with each other, outputs a hit signal.

Abstract: A multiplexing apparatus multiplexes two or more data streams and output to an arbitrarily selected circuit, and includes a time division switch for multiplexing inputted data and outputting the multiplexed data to a selected circuit, and a memory unit which stores real control data for controlling actual connection operations of the time division switch and virtual control data for controlling virtual connection operations.

Abstract: An apparatus and method for generating a comparand in a content addressable memory array. The apparatus includes a content addressable memory (CAM) array and translation circuitry to receive translation information indicative of translation of a bit group from an initial position in input data to a different position in a comparand transmitted to the CAM array. The translation circuitry includes a switch circuit, one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the initial position and the position in the comparand. The apparatus also includes program circuitry to provide a bit level programming interface with the translation circuitry. The apparatus may also include a programming bit register to store programming information in the form of a binary pattern where each bit represents a bit group of the input data.

Abstract: Each packet normally consists of a preamble, start-of-frame delimiter and data. The preamble has nibbles each having a particular format. A header substituted for preamble nibbles by an individual one of the originating devices in a plurality, and an individual one of the ports in such originating device, indicates such originating device and such port. Such port in such originating device sends such modified packet to others of the originating devices and to an observing station. The header format is such that the last nibble in the header and the remaining preamble portion will not be confused with any two (2) nibbles in the header. A particular one of the originating devices indicated in the data converts the header back to the preamble format and transmits the converted packet to a receiving station. The observing station records the individual originating device, and the individual port in such device, indicated in the header.

Abstract: A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.

Abstract: An interconnection device (300) with a number of links (306, 308, 310, 312 and 314), each link having a number of link input ports (302), link output ports (304) and storage registers (316). An input selection switch (402) is coupled to a selected link input port to receive an input data token. The storage registers (316) may be used to store input data tokens. A storage access switch (404) is coupled to the input selection switch (402) and to the storage registers (316) and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch (406) receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.

Abstract: A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals.

Abstract: A method for managing a content addressable memory (CAM) look-up table using the longest prefix matching (LPM) is provided. The method includes providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers stores the next higher address of data having the highest address in each band of data; and making a space in which data is to be added in the CAM look-up table by moving data having the addresses stored in the pair of pointers provided per each band of data that has a shorter prefix length than the prefix length of the data to be added, when data is added to the CAM look-up table. According to the method, it is possible to easily and efficiently add new data into the look-up table of the CAM.

Abstract: A method is disclosed for generating a PCM code set for encoding data by a PCM encoder in a data transmission system having a digital modem with a PCM encoder, a digital signal transmission path, an analogue signal transmission path with a central office line interface portion, and an analogue modem. The method includes the step of determining a minimum signal level distance between adjacent PCM codes of the PCM code set, the minimum signal level distance enabling discrimination by the analogue modem. Then a line interface attenuation of the central office line interface portion is determined. Finally, the PCM code set on the basis of a power limit computed by adding the line interface attenuation to a central office line interface power limit is generated. The invention further relates to an analogue modem to be operated in such a data transmission system.

Abstract: A header substituted for preamble nibbles by an individual one of the originating devices in a plurality, and an individual one of the ports in such originating device, indicates such originating device and such port. Such port in such originating device sends such modified packet to others of the originating devices and to an observing station. The header format is such that the last nibble in the header and the remaining preamble portion will not be confused with any two (2) nibbles in the header. A particular one of the originating devices indicated in the data converts the header back to the preamble format and transmits the converted packet to a receiving station. The observing station records the individual originating device, and the individual port in such device, indicated in the header. Each packet includes at its end a trailer formed from a plurality of nibbles and indicating whether or not a collision has occurred between such packet and a packet from another one of the originating devices.

Abstract: The invention provides a method and system for routing information lookup for packets using a routing protocol such as IP. Routing information which has been determined responsive to the packet header, which includes a destination address, a source address, and an input interface for the packet. Routing lookup is performed in response to at least one set of selected routing information, using a lookup table which includes tags both for the routing information and for a bitmask length (thus indicating the generality or scope of the routing information for the routing lookup). The lookup table is structured so that addresses having the most common bitmask length are addressed first, but that more specific addresses are still considered when they are present. It has been discovered that most internet addresses can be found by reference to 24-bit or 21-bit IP addresses, after which 16-bit, 12-bit, and finally 32-bit IP addresses are considered.

Abstract: The present invention provides a method of assigning a unique device identification to an electronic device coupled into a communication architecture. Once coupled into the communication architecture a piece of globally unique identifying data is retrieved and utilized to generate a device identification which identification is then assigned to the device.

Abstract: An apparatus and a method are provided for switching an information signal from a selected input to a selected output of a telecommunications switch. The method includes the steps of digitally sampling the information signal at the selected input of the telecommunication switch and writing the sampled information signal into a predetermined location of a data frame within a circulating data loop at a first station of the circulating data loop. The method further includes the steps of capturing the sampled information signal at a second station of the circulating data loop and transferring the captured information signal to the selected output of the telecommunications switch.

Abstract: A switch module for time switching telecommunications data includes an input circuit for selecting data samples from a time slot in an input frame of data samples. The selected data samples are arranged into groups of uniform size, each group consisting of at least two data samples. The groups of selected data samples are stored in an orderly manner, in each of as many storage entities as there are data samples in each group. Thereafter in accordance with a predefined sequence peculiar to each of the storage entities, the data samples are simultaneously read out, group by group. An output circuit selects data samples into a selected group of data samples from among each of the readouts of each of the storage entities and transmits each selected group into an output frame of data samples. Hence a sequence of the data samples appears switched in the output frame with respect to the sequence of the data samples as they were stored from the input frame.

Abstract: A two-way data communication device such as a data ready cellular telephone, a two-way pager, or a telephone communicates via a two-way data communication network with a server computer on a computer network that has an interface to the two-way data communication network, i.e, is coupled to the two-way data communication network. For example, the computer network can be a corporate wide area network, a corporate local area network, the Internet, or any combination of computer networks. The two-way data communication device utilizes a client module to transmit message including a resource selector chosen by the user to a server on a server computer on the computer network. The server processes the message and transmits a response over the two-way data communication network to the client module. The client module interprets the response and presents the response to the user via a structured user interface.