Abstract: A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

Abstract: The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.

Abstract: A method and apparatus for the distribution of electronic media content for distribution to employees of a subscriber. The system includes an electronic display for displaying selected electronic media content that may be selected, modified and/or generated by the subscriber. The system allows for dramatically increased subscriber control of the media content presented as well as for increased security for any confidential media content to be presented on the customer display. The system further provides for individual control of multiple displays that may be located in differing geographic locations while at the same time providing for ease of information management.

Abstract: A networking device such as a router may include, in one embodiment, a database storing a plurality of link state entries, and a cache operatively coupled with the database, the cache storing entries relating to the link state entries of the database. The networking device may also include a module for sending, over a network, packets including link state data, the module operatively coupled with the cache. In one example, the module accesses the cache to create one or more packets including link state data. Embodiments of the invention may be used for forming CSNP packets (complete sequence number packets) without the need for having to repeatedly walking a link state database in order to form the CNSP packets.

Abstract: It is disclosed a method comprising prioritizing a plurality of queuing entities with respect to each other, receiving a data stream consisting of a plurality of data packets, marking each of the plurality of data packets with one out of a plurality of identifiers based on a predetermined requirement, the plurality of identifiers corresponding to the plurality of queuing entities, enforcing each one of the plurality of data packets based on the respective identifier, comprising detecting the identifier in each one of the plurality of marked data packets, and queuing, responsive to the detecting, the data packets into one of the plurality of prioritized queuing entities, scheduling, in each of the plurality of prioritized queuing entities, the respective queued data packets, and transmitting the scheduled data packets in each of the plurality of prioritized queuing entities according to the priority of the respective queuing entity.

Abstract: Methods and devices are provided for controlling congestion in a network such as a Fibre Channel network. According to some implementations, a node within a network fabric detects congestion caused by an edge device outside of the fabric and notifies the edge device of the congestion. The edge device applies a congestion reaction mechanism in response to the notification. In some implementations, the congestion reaction mechanism is applied on a per-exchange basis, in order to mitigate congestion caused by a particular operation.

Abstract: A network switching device that prevents its shared buffer from suffering a blocking problem, while achieving a higher memory use efficiency in buffering variable-length packets. Every received packet is divided into one or more fixed-length data blocks and supplied to the buffer. Under the control of a buffer controller, a transmit queue is created to store up to a fixed number of data blocks for each different destination network, and the data blocks written in the buffer are registered with a transmit queue corresponding to a given destination. The linkage between data blocks in each packet, as well as the linkage between packets in each transmit queue, is managed as a linked list structure based on the locations of data blocks in the buffer.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A switching network forms part of a digital cross-connect for connecting data frames between requested inputs and outputs, and includes an input stage, an intermediate stage, and an output stage, each of which consists of a plurality of switching matrices. Each input stage switching matrix has a link to each intermediate stage switching matrix, and each intermediate stage switching matrix has a link to each output stage switching matrix. Individual time-slots of incoming data frames are independently routed through the switching matrices, reducing the possibility of blocking taking place.

Abstract: A system determines when to send out a partial data unit or when to complete a data unit before sending it. The system may identify a data unit, determine whether the data unit is a partial data unit, increase a partial count when the data unit is the partial data unit, determine whether the partial count is greater than a threshold, and fill a subsequent data unit with data to form a complete data unit when the partial count is greater than the threshold. The system may, alternatively or additionally, determine a schedule of flush events for a queue, identify whether the queue includes information associated with a partial data unit, identify whether the queue should be flushed based on the schedule of flush events and whether the queue includes information associated with the partial data unit, wait for additional data when the queue should not be flushed, and send out the partial data unit when the queue should be flushed.

Abstract: A task obtained by a communications processor is decomposed into one or more requests that form a request group. The requests of the request group are sent to main memory and responses to those requests are expected. There may be requests for a plurality of request groups being processed concurrently. However, responses to the request groups are to be returned to the communications processor in the order in which the request groups were sent from the communications processor. To ensure this ordering, dependencies between the request groups are tracked by hardware coupled to the communications processor.

Abstract: A network device includes a memory and a packet forwarding engine. The memory stores a multicast list table, tag descriptor data and layer 2 (L2) encapsulation data. The packet forwarding engine receives a first pointer to an entry in the multicast list table, the entry including a second pointer to the tag descriptor data. The packet forwarding engine utilizes the second pointer to retrieve the tag descriptor data, the tag descriptor data including a third pointer to the encapsulation data. The packet forwarding engine constructs a packet header utilizing the retrieved encapsulation data and appends the packet header to a packet payload for forwarding out of the packet forwarding engine.

Abstract: To avoid under-run conditions that result in corrupt packets at I/O interfaces, a FIFO buffer controller monitors key aspects of the contents of FIFO buffers of I/O interfaces. The FIFO buffer controller initiates transmission of data from the FIFO buffer when at least one complete packet is stored in the FIFO buffer or when the size of a partial packet stored therein is large enough so that the remainder of the packet would normally be received by the FIFO buffer before the stored part can be transmitted from the FIFO buffer; thereby avoiding an under-run error condition.

Abstract: In a packet switched network, network data can be recorded for measurement by transmitting a measurement packet across the network to store path records as it travels from an originating measurement device to a destination device. Some of the network devices located along the path traversed by the measurement packet are capable of recognizing that the measurement packet no longer has any further storage capacity for path records. The network device then copies or clones the measurement packet and erases the path record data from the original measurement packet. The original measurement packet then continues on its path to the destination address collecting further path records on the way, while the cloned packet is returned to the measurement host for processing of the path records when all cloned packets and the original measurement packet return to the measurement host.

Abstract: Packet flow rate control techniques are enhanced by the interactive and early invocation of packet queuing to control short flows of packets and to eliminate undershoot and overshoot of a targeted flow rate. Packet queuing involves the scheduled release of packets in accordance with flow policies (priorities) to achieve a pre-selected outgoing target flow rate. The combination of controlled packet queuing and packet flow rate control with appropriate mechanisms for favoring one over the other improves the efficiency of data transmission.

Abstract: An apparatus and method for dynamic assignment of classes of traffic to a priority queue. Bandwidth consumption by one or more types of packet traffic received in the packet forwarding device is monitored to determine whether the bandwidth consumption exceeds a threshold. If the bandwidth consumption exceeds the threshold, assignment of at least one type of packet traffic of the one or more types of packet traffic is changed from a queue having a first priority to a queue having a second priority.

Abstract: The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.

Abstract: Approaches are disclosed for switching transport protocol connection keys. A first node sends a keychange request message to a second node, causing the second node to accept subsequent messages digitally signed with a first or second key. The second node sends an acknowledgment message to the first node, causing the first node to accept subsequent messages digitally signed with the first or second key. The first node receives a new message digitally signed with the second key from the second node and determines that there are no remaining messages to be received digitally signed with the first key. In response thereto, the first node only accepts messages digitally signed with the second key and sends a message signed with the second key to the second node, causing the second node to only accept messages digitally signed with the second key.

Abstract: In one aspect of the present invention, a network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, an Ethernet MAC, and a USB controller to provide high performance and robust operation.

Abstract: A distributed switching system comprising a call controller, multiple source modules, and multiple destination modules provides circuit switching functionality without using a centralized circuit switch. When a source module of the multiple source modules receives inbound data, the source module broadcasts the data to each destination module of the multiple destination modules via an inbound time slot of multiple inbound time slots. The call controller selects a destination module of the multiple destination modules to process the data and informs the selected destination module of the inbound time slot. The selected destination module then receives the broadcast via the inbound time slot and processes the broadcast data. The distributed switching system further provides for a transfer of data in an outbound direction by allocating an outbound time slot in which the selected destination module embeds tagged data for receipt and forwarding by the source module.

Abstract: A communication control terminal apparatus employs one CPU to control two or more communication procedures, without adversely affecting each other. The communication control terminal apparatus includes a storage unit for storing information by using predetermined codes, a codec unit for coding and decoding the information, and communication control units for transmitting the information. A communication code obtained by the codec unit through conversion is transmitted via the communication control units. An execution time for the codec unit is changed in accordance with types of the communication procedures performed by the communication control units.

Abstract: Systems and methods are disclosed for differentiated handling of VoIP call control messages according to their importance and functionality, thus providing to VoIP infrastructures a level of robust call control similar to that in PSTN networks. SIP messages are classified by their type or content, and resources of a VoIP call control server are allocated to the SIP messages according to a policy. The scheme also provides overload protection and prioritized handling of certain kinds of requests in VoIP call control servers.

Abstract: In a packet repeater of a wireless base station, a packet analyzer receives uplink packets from mobile terminals and stores data indicating quality of each wireless link between the base station and each mobile terminal in a memory. A packet sorter receives downlink packets from a network and stores the received packets into buffers according to the destinations of downlink packets and their service classes. According to the data stored in the memory, packets in the buffers are into a first group of queues in which quality of service is not satisfied and a second group of queues in which quality of service is satisfied. A packet scheduler sequentially transmits all packets from the first-group queues to mobile terminals, and reorders the second-group queues in a descending order of their qualities of wireless links and sequentially transmits all packets from the reordered queues to the mobile terminals.

Abstract: In various exemplary embodiments, a method for the distribution of content within a network of constrained capacity uses distributed content storage nodes functioning to achieve optimal service quality and maximum service session capacity. The method, which functions in unicast, broadcast, switched broadcast, and multicast mode networks, uses predictions of the utility of particular content items to download or record the highest utility items to distributed content stores during periods and in modes that will not increase demand peaks. These predictions of utility may be based on, for example, the number of potential users, the likelihood of their use, and the value to the service provider. The method uses signaling between network nodes to identify the best source for particular content items based on which nodes hold that content and the nature of network constraints.

Abstract: A multi-grained network includes edge modules that switch high-variance multi-rate data traffic, and independent core modules that switch paths having different granularities. The core may include core modules that switch fixed-size data blocks, core modules that switch channels or bands of channels, core modules that switch entire links, and core modules that cross-connect channels or links. To simplify the control functions, the core modules operate independently from each other. Direct link, band or channel connections may be established for selected ingress-egress edge module pairs, if traffic volumes warrant. The use of graded granularity in the core simplifies the control function and reduces network cost.

Abstract: In one embodiment of the present invention, a system for memory interleaving in a high-speed switching environment includes multiple memory units that each include one or more memory devices. The system also includes multiple port modules. Each port module can receive a packet communicated from a component of a communications network, write the received packet to one or more of the memory units, and read a packet from one or more of the memory units for communication to the component of the communications network. The system also includes an interconnection network including a hierarchical structure that includes one or more switching stages.

Abstract: A communications chip having a plurality of ports. Each port is provided with an interface for attachment to an external communications facility to exchange data traffic. There is also a switching matrix for routing data traffic on the chip between the ports. The chip further includes a plurality of logic analyzers. Each logic analyzer is associated with a corresponding one of the ports. Each logic analyzers is operable to monitor data traffic passing through its corresponding port and to trigger on one or more predetermined conditions relating to the monitored data traffic. The chip further includes a control interface to allow reconfiguration of the predetermined conditions for at least one of the logic analyzers.

Abstract: The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.

Abstract: An interface adapter for a packet network includes a first plurality of execution engines, coupled to a host interface so as to read from a memory work items corresponding to messages to be sent over the network, and to generate gather entries defining packets to be transmitted over the network responsive to the work items. A scheduling processor assigns the work items to the execution engines for generation of the gather entries. Switching circuitry couples the execution engines to a plurality of gather engines, which generate the packets responsive to the gather entries.

Abstract: A trace information queueing system receives a plurality of trace information signals and transmits them through a common connector. The multiple trace information signals may be multiplexed. Each edge of a clock signal may be used to enable transmission of different trace information signals. Alternatively, separate clocks signals may be provided for each trace information signal. A programmable logic device may be used to both multiplex the trace information signals and produce the clock signals necessary to enable their transmission.

Abstract: To reduce the load on a host for controlling a data doubling. Between a host and two disk subsystems, there is connected a data doubling device. This data doubling device behaves as if it were a unit disk subsystem for the host. The data doubling device doubles a data I/O instruction from the host and issues the doubled data I/O instruction to two disk subsystems. In case either of the disk subsystems becomes faulty, the data doubling device sends the data I/O instruction from the host only to the normal disk subsystem. After the fault recovery, the data doubling device performs a data copy between the disk subsystems.

Abstract: Methods and systems for hybrid layer 2 address learning are disclosed. In one method, a packet with a layer 2 source address is received. Next, it is determined whether to implement hardware-based learning or software-based learning based on a classification of the received packet. In response to determining that software-based learning is required, the source address and corresponding forwarding information in the packet are learned using software. In response to determining that hardware-based learning is required, the source address and corresponding forwarding information are learned using hardware.

Abstract: A polyphase circulating switch includes switch modules interconnected through a multiplicity of rotators preferably arranged in complementary groups of opposite rotation directions. A polyphase circulating switch having a low switching delay is derived from a multi-rotator circulating switch by providing programmable rotators having adjustable relative rotator-cycle phases. A low delay high-capacity switch may also be constructed from prior-art medium-capacity rotator space switches with mutually phase-shifted rotation cycles. A network comprising several constellations of switch modules distributed over a wide geographic area, where the switch modules of each constellation are interconnected through a rotator assembly, is also disclosed. A rotator assembly may comprise an array of rotators and a master controller for data-transfer scheduling and time-coordination.

Abstract: A Universal Serial Bus (USB) device uses a same elasticity buffer for buffering packets for multiple different ports and only necessary packet detection circuitry is associated with the individual ports. A collision detection circuit is further included corresponding with information received from the packet detection circuitry. This simplified universal elasticity buffer architecture reduces the complexity and cost of the USB device.

Abstract: A system for reducing clock speed and power consumption in a network chip is provided. The system can have a core that transmits and receives signals at a first clock speed. A receive buffer can be in communication with the core and be configured to transmit the signals to the core at the first clock speed. A transmit buffer can be in communication with the core and configured to receive signals from the core at the first clock speed. A sync can be configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync can be in communication with the transmit buffer and the receive buffer.

Abstract: System for reordering sequenced based packets in a switching network. The system includes time stamp logic that operates to associate a receive time indicator with each received data packet. The system also includes Enqueue logic that operates to compute an expiration time for each received packet based on the receive time indicator, and stores the expiration time and the sequence identifier for each received packet into a table. Dequeue logic operates to read the table to determine the received data packets to output in an output stream so that the received data packets are output in a selected order. The Dequeue logic also operates to determine a true expiration time for one or more unreceived data packets, and if the true expiration time for a selected unreceived data packet is reached, the Dequeue logic operates to omit the selected unreceived data packet from the output stream.

Abstract: A methods, apparatus and computer memory are provided for packet scheduling. A processor polls queues in a round robin fashion and schedules for transmission onto a link a packet in each queue with no deficit before scheduling for transmission onto the link a packet in each queue with a deficit. A credit is allocated to each queue with the deficit based on a proportional weight, until each queue with the deficit has a credit.

Abstract: A method and system for routing fiber channel frames using a fiber channel switch element is provided. The switch element includes, a hashing module whose output is used to select the column from a look up table to route frames. The method includes, indexing a look up table using domain, area, virtual storage area network identifier, a hashing module output and/or AL_PA values; selecting a column from the look up table based on a column select signal; and routing a frame if a route is valid. The hashing module takes a fiber channel header to generate a pseudo random value used for selecting a column from the look up table. The hashing module uses same field values in an exchange to generate the pseudo random value. A hash function is used on a frame's OX_ID, D_ID, S_ID, and/or RX_ID to route fiber channel frames.

Abstract: A method and apparatus to perform frame coalescing are described.

Abstract: A technique shares a port (e.g., a physical port) among a plurality of virtual bridges on a switch in a computer network. According to the novel technique, two or more virtual bridges are established on the switch, and are each assigned respective sets of Virtual Local Area Networks (VLANs). Each virtual bridge has a virtual interface corresponding to the physical port (a “shared trunk”), the virtual bridges regarding the virtual interfaces as though they were physical ports. Control messages transmitted by the virtual bridges on the virtual interfaces are sent over the physical port and to each other virtual interface of the port (the shared trunk), such as, e.g., by a virtual hub of the shared trunk. Also, control messages received on the physical port are sent over each virtual interface to each virtual bridge (e.g., by the virtual hub).

Abstract: A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

Abstract: Methods and apparatus are provided for self-organized caching in a content delivery network. One or more requested content items are cached at a node in a content delivery network. The disclosed method determines if the content item is stored in a local cache; and, if the content item is not stored in a local cache, the following steps are performed: requesting the content item from another node; and storing the content item in the local cache it one or more predefined capacity criteria are satisfied. The content delivery network can be a hierarchical network or a non-hierarchical network. The predefined capacity criteria can evaluate a popularity index of the content item relative to other items stored in the local cache.

Abstract: A network device has a network interface to allow the device to send and receive traffic across a network. The device also has a cable connection to allow the device to exchange data with at least one cable modem and a processor to associate a cable interface and cable service identifier with a cable modem; receive a packet from the cable modem; and insert a layer 2 network identifier, the identifier comprising two service provider VLAN (SP-VLAN) tags, into the packet. The processor in the network device identifies a virtual trunk interface based on the outer SP-VLAN tag and identifies the virtual private network based on the inner SP-VLAN tag.

Abstract: A method and apparatus to limit the throughput rate on a packet-by-packet basis. Each packet of an input flow is mapped to an entry in a flow table for each output queue. The mapping is based on a subset of the packet's header data, giving an approximation of per-flow management. Each entry contains a credit value. On packet reception, the credit value is compared to zero; if there are no credits, the packet is dropped. Otherwise, the size of the packet is compared to the credit value. If sufficient credits exist (i.e., size is less than or equal to credits), the credit value is decremented by the size of the packet in cells and the packet is processed. If the size of the packet exceeds the available credits, the credit value is set to zero and the packet is dropped. A periodic task adds credits to each flow table entry up to a predetermined maximum.

Abstract: A MAC unit is provided that processes the flow of data between a higher protocol-layer unit and a physical-layer control unit of a network communications component. The MAC unit includes a first processor that receives high-level data units from the higher protocol-layer unit and generates outgoing MAC protocol-data units therefrom. The MAC unit also includes a second processor that receives outgoing MAC protocol-data units generated by the first processor and generates outgoing FEC blocks therefrom for outputting to the input port of the physical-layer control unit. In addition the MAC unit includes a MAC-PDU reception buffer accessible by the first and second processors, the second processor storing incoming MAC protocol-data units in the MAC-PDU reception buffer, and the first processor reading incoming MAC protocol-data units from the MAC-PDU reception buffer.

Abstract: A method of replicating multicast datagrams in a network device is disclosed. The method includes the steps of determining by a memory management unit whether a scheduled outgoing datagram stored in a main memory is a multicast (MC) packet. When the scheduled outgoing datagram type is the MC datagram, the method also includes performing a lookup of a replicate count table to determine a copy count value and writing the copy count value to a copy count register, awaiting a ready signal from an egress port of the network switch and sending the outgoing datagram to the egress port from the main memory along with the copy count value. The method also includes changing the copy count value in the copy count register, modifying a VLAN identifier of the outgoing datagram if necessary based on the copy count value and forwarding the outgoing datagram from the egress port.

Abstract: An apparatus for interfacing with a cell delay variation buffer and a re-assembly memory buffer includes a header and sequence number processing module that can interface with the cell delay variation buffer and a re-assembly processing module that can interface with the re-assembly memory buffer. The header and sequence number processing module causes payloads from the cells to be stored in annotated form in the cell delay variation buffer and then extracted. Payload information from the extracted annotated payload can be passed to the re-assembly processing module which causes it to be stored in the re-assembly memory buffer and extracted therefrom as needed. By splitting the cell delay variation and re-assembly buffer functions, less expensive commodity memory can be used for the cell delay variation buffer function.

Abstract: An aggregation switch apparatus for broadband subscribers is disclosed. The apparatus includes: an upstream input buffering unit for buffering packets from more than one subscriber link; a scheduling unit for aggregating the packets to more than one upstream link and scheduling a transfer order; a rate match buffering unit for buffering a transfer rate difference between an output of the upstream input buffering unit and an output of more than one upstream link; a downstream destination identifying unit for identifying a destination of more than one subscriber link of the packets; a broadcasting unit for transferring the packets to terminals of the broadcasting unit; a packet selecting unit for selecting a corresponding packet by identifying a destination port of more than one subscriber link of the packets; and a downstream output buffering unit for buffering the packets outputted from the packet selecting unit to said more than one subscriber link.

Abstract: In general, in one aspect, the disclosure describes a method includes accessing data of an egress packet belonging to a flow, storing data associating the flow with at least one queue based on a source of the data of the egress packet. The method also includes accessing an ingress packet belonging to the flow, performing a lookup of the at least one queue associated with the flow, and enqueueing data of the ingress packet to the at least one queue associated with the flow.

Abstract: Methods and apparatus are disclosed using a random indication to map items to paths and to recirculate or delay the sending of a particular item when a destination over its mapped path is unreachable, including, but not limited to the context of sending of packets across multiple paths in a packet switching system. In one implementation, a set of items is buffered, with the set of items including a first and second sets of items. The items in the first set of items are forwarded over a set of paths in a first configuration. The set of paths is reconfigured into a second configuration, and the items in the second set of items are forwarded over the set of paths in the second configuration. In one implementation, a recirculation buffer is used to hold items not immediately sent. In one implementation, the paths are reconfigured in a random fashion.