Abstract: A phase locked loop device may include: a frequency modulating circuit configured to output a reference signal obtained by multiplying a frequency of an input signal by a predetermined ratio based on the input signal; a sigma-delta modulator configured to output division ratio information on one of a plurality of division rates at a number of times proportional to a frequency of the reference signal; and a phase locked loop (PLL) circuit configured to determine whether to activate based on a command signal, and, when activated, perform a phase-locking operation based on a fractional division based on the reference signal and the division ratio information.

Abstract: A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.

Abstract: An automatic frequency calibration method and a small cell using the same are provided. The automatic frequency calibration method comprises the following steps. A set of at least one broadcasting message in a surrounding environment is received. Whether part of the at least one broadcasting message is transmitted from at least one first type base station is determined. If part of the at least one broadcasting message is transmitted from the first type base station, then a frequency of the small cell is calibrated according to one of the at least one first type base station whose signal strength is maximum among all of the at least one first type base station. If all of the at least one broadcasting message are not transmitted from the first type base station, the frequency of the small cell is calibrated according to at least one second type base station.

Abstract: A clock recovery circuit includes: a phase comparison circuit to compare a data signal and a recovered clock; a charge pump circuit to output a current based on a phase difference signal; a loop filter to convert the current into a control voltage; an oscillation circuit to generate a first sine-wave clock having a frequency corresponding to the control voltage and a second sine-wave clock having a phase obtained by shifting a phase of the first sine-wave clock by 90 degrees; and a clock selector to select, as the recovered clock, the first sine-wave clock or the second sine-wave clock, a selected clock having a voltage difference between a voltage at a transition of the data signal and a center of an amplitude is larger than a voltage difference between a voltage of a non-selected clock at the time and a center of an amplitude of the non-selected clock.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first mode of operation in which the frequency divider is configured to operate in dependence on a first division control signal such that the resultant oscillating output signal has a first frequency and first phase, a second mode of operation in which the frequency divider is configured to operate in dependence on a second division control signal such that the resultant oscillating output signal has a second frequency and second phase, the first division control signal being generated independently of the oscillating output signal such that the first phase is maintained when the phase-locked

Abstract: An isolation interface circuit is disclosed. The isolation interface circuit comprising a transmitting circuit and a receiving circuit. The transmitting circuit configured to receive a first serial interface signal and a second serial interface signal for generating a differential polarity pulse signal. The receiving circuit configured to receive the differential polarity pulse signal for generating the first serial interface signal and the second serial interface signal. The differential polarity pulse signal are generated in response to the first serial interface signal and the second serial interface signal. The first serial interface signal and the second serial interface signal are generated in accordance with the differential polarity pulse signal. In a period, only one of the transmitting circuit and the receiving circuit can be enabled.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: A system and method for low-cost, fault tolerant, EMI robust data communications, particularly for an EV environment.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract: An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made.

Abstract: A distributed antenna system includes a master unit including a downlink RF input operable to receive an RF input signal from a downlink port of a base station, a first optical port, and a second optical port. The distributed antenna system also includes a first remote unit coupled to the first optical port. The first remote unit comprises a downlink antenna port and a first uplink antenna port and a second remote unit coupled to the second optical port of the master unit. The second remote unit comprises a downlink antenna port and a second uplink antenna port. The master unit is operable to transmit a first RF signal associated with the first RF uplink signal to a first uplink port of the base station and transmit a second RF signal associated with the second RF uplink signal to a second uplink port of the base station.

Abstract: A system and method for low-cost, fault tolerant, EMI robust data communications, particularly for an EV environment.

Abstract: Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: Provided is an electronic system capable of dynamically switching a communication speed among a plurality of electronic devices connected in series. A first communication device and a second communication device are connected in series to a host controller. After controlling the communication speed of the second communication device to be a communication speed defined in advance, the host controller controls the communication speed of the first communication device to be the same communication speed as the communication speed of the second communication device.

Abstract: A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.

Abstract: A repeater environment is provided to deploy a feedback cancellation loop that is adaptively coupled with an antenna array such that a selected metric can be derived by deploying a one or more of selected metrics (e.g., composite metrics) 5 comprising a selected filter bank operative to process the signal on a bin by bin basis and the derived metric can be applied to the antenna array and feedback cancellation loop combination to improve signal integrity and amplification, beam forming operations, and pilot control and overhead channel control operations. In an illustrative implementation, an exemplary repeater environment comprises, a 10 transmitter, a receiver, an equalized feedback cancellation loop circuitry comprising a filter bank, the cancellation loop being operatively coupled to an antenna array. In the illustrative implementation, the feedback cancellation loop can receive signals as input from a cooperating antenna array and provide output signals such as a feedback leakage signal to a cooperating.

Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: A repeater environment is provided to operatively deploy a feedback cancellation loop that performs closed loop calculations for weights used by a feedback equalizer to improve signal integrity and amplification. In an illustrative implementation, an exemplary repeater environment comprises a transmitter, a receiver, an equalized feedback cancellation loop circuitry operative to perform one or more closed form calculations for equalizer weights. In the illustrative implementation, the feedback cancellation loop can comprise a calculation module operative to perform one or more closed form weight calculations using linear algebraic techniques as part of feedback signal cancel operations for use by the N tap feedback equalizer canceller.

Abstract: A circuit and method for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device detect an end of packet from an input data stream to initialize a counter, identify a token packet in the data stream to detect a start of frame token packet for the counter to carry out clock counting on the clock signal to thereby obtain a count value, and compare the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: In described embodiments, a receiver includes a clock and data recovery (CDR) module with a voltage control oscillator (VCO) and a Sigma-Delta modulator in an integral loop control of the VCO. Providing finer resolution by the Sigma-Delta modulator reduces quantization noise in the integral control loop when compared to a loop without a Sigma-Delta modulator in the integral loop. Sigma-Delta modulation within the integral loop control of a VCO-based CDR reduces effective quantization of the VCO integral word control, allowing the proportional loop control compensation to i) reduce effective quantization of the VCO integral word control and, ii) enhance receiver jitter tolerance in presence of periodic-jitter, serial data whose frequency is offset from the nominal rate and serial data whose nominal frequency is modulated by a spread spectrum clock.

Abstract: A source device counts a clock CLKpixel for pixel data using a transmitting counter, adds a counted value Csource(t) of the transmitting counter at a timing of transmitting a video packet Pvideo to the sink device to a header part of the video packet Pvideo as a time stamp value Csource(t), and transmits the video packet Pvideo to the sink device. The sink device receives the video packet Pvideo, extracts the time stamp value Csource(t) from the header part of the video packet Pvideo, generates a fixed reference clock CLKref based on the counted value Csource(t) of the transmitting counter using a first PLL, circuit, and generates the clock CLKpixel for the pixel data of the source device based on the reference clock CLKref using a second PLL circuit.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: A lock detection circuit and method are disclosed for phase locked loop (PLL) systems. The lock detection circuit primarily includes a delay unit and an asserting logic unit. The delay unit receives the phase error signal of the PLL and produces a present phase error signal, and then accordingly generates at least one delayed phase error signal. The asserting logic unit generates an unlock indicating signal (UNLOCK) according to the present phase error signal and the delayed phase error signal. A phase lock indicating signal will be asserted if the unlock indicating signal is not asserted within a predetermined number of counting pulses.

Abstract: A receiver having an intermediate frequency error correction circuit includes a mixer having a source input, a local oscillator input, and an IF output, an adjustable frequency local oscillator having an output coupled to the local oscillator input of the mixer, an IF filter having an input coupled to the IF output of the mixer and an IF filtered output, where the IF filter has an IF filter frequency response, and control circuitry coupled to the local oscillator such that the frequency of the local oscillator can be varied to at least: partially correct an IF frequency error.

Abstract: The invention describes a field bus system, in particular a field bus system (10), comprising at least one clocked transmitter (16) and one clocked receiver (17) for transmitting data signals to another field bus device (30) or for receiving data signals from the other field bus device (30). To allow interfering emissions to be reduced, a spread spectrum clock (40) is provided which supplies a local spread spectrum clock signal (SST1). The spread spectrum clock signal is sent to the transmitter (16) and the receiver (17) to allow data signals (DO1, DI1) to be transmitted and received synchronously with the local spread spectrum clock signal.

Abstract: In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed.

Abstract: A feedback signal cancellation apparatus includes a first RF receiver configured to down-convert a received RF signal to a predetermined frequency band, a subtractor configured to subtract a replica of a feedback signal from the down-converted signal, a transmission signal generator configured to generate a repeater output signal using a feedback cancelled signal, a RF transmitter configured to transmit the repeater output signal, a second RF receiver configured to down-convert a RF signal outputted from the RF transmitter to a predetermined frequency band, a reference signal generator configured to receive the RF signal and generate a reference signal having no DC pilot, and a replica generator configured to generate a filter coefficient using correlation between the feedback cancelled signal and the reference signal and to generate a replica of the feedback signal using the generated filter coefficient and the down-converted signal of the second RF receiver.

Abstract: A method may include performing a logical exclusive OR and a logical inverse exclusive or on an input reference signal and an output signal to generate an XOR signal and an XNOR signal, respectively. The method may also include generating a switch control signal indicative of whether a first phase of the input reference signal leads or lags a second phase of the output signal. The method may additionally include: (i) transmitting the XOR signal to an output of a switch if the first phase leads the second phase; and (ii) transmitting the XNOR signal to the output of the switch if the first phase lags the second phase. The method may further include generating a phase detector output signal indicative of a phase difference between the second phase based on a signal present on the output of the switch.

Abstract: A phase locked loop (PLL) circuit includes a first signal detector having a first input terminal configured to receive a varying first input signal, a second input terminal configured to receive a feedback signal that corresponds to the center of the input frequency, and an output terminal configured to provide an output signal corresponding to a phase difference between the first input and feedback signals. A delay estimator has an input terminal configured to receive the output signal from the first phase detector and in response thereto, output a phase difference estimation signal. A variable delay circuit has an input terminal configured to receive the phase difference estimation signal and in response thereto, phase shift the second input signal.

Abstract: A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

Abstract: A method and apparatus for performing time synchronization is provided. The method/apparatus includes, at a radio subsystem: receiving, from a digital subsystem, a first signal via the link, where the link not dedicated to timing synchronization; determining a time difference between the first signal and a second signal; converting the time difference to a time error, sending, via the link, the time error or time difference to the digital subsystem. The method further includes, at the digital subsystem, inputting the time error, received from the radio subsystem, to a phased locked loop (PLL) in order to adjust an oscillator frequency so as to reduce the amount of the time error and thus synchronizing the radio access network with the second signal received at the radio subsystem, without the need for an additional connection between the digital and radio subsystems.

Abstract: Disclosed is a circuit and method to program the starting phase of the spread spectrum of a clock output. The circuit includes a plurality of phase locked loop (PLL) circuits for generating a plurality of spread spectrum waveforms. The circuit also includes a spread control circuit for controlling each of the plurality of PLL circuits in accordance with a plurality of respective spread profiles. The spread profiles are configured to vary a starting phase of each spread spectrum waveform such that a total energy of each spread spectrum waveform is out of phase with other spread spectrum waveforms.

Abstract: Disclosed herein is a phase-locked loop circuit including: a voltage controlled oscillator; a variable frequency divider circuit for frequency-dividing an oscillating signal of the voltage controlled oscillator into a 1/N (N is an integer) frequency; a phase comparator circuit for comparing phases of a frequency-divided signal and a reference signal of a reference frequency with each other; a charge pump circuit for outputting a charge pump current changed in pulse width; a loop filter for being supplied with the charge pump current and outputting a direct-current voltage changed in level; and a control circuit for calculating a value of the charge pump current as a function of the oscillating frequency of the voltage controlled oscillator and a coefficient for setting a phase locked loop band, and setting the value of the charge pump current in the charge pump circuit.

Abstract: A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.

Abstract: Systems and methods are provided for automatically setting up an initial configuration of a wireless repeater and managing one or more wireless repeaters in a wireless local area network.

Abstract: A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.

Abstract: A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.

Abstract: A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

Abstract: A radio over fiber link apparatus for transmitting/receiving radio frequency up/downlink signals in a TDD mobile communication system. The radio over fiber link apparatus includes a center site for receiving radio frequency signals from an access point of the mobile communication system. The center site has a first electro-optic converter for converting the radio frequency signals into optical signals, bias control of the first electro-optic converter being performed based on the switching of TDD signals; and a remote for transmitting the radio frequency signals to a mobile communication terminal through an antenna. The remote site has a first photoelectric converter for converting the optical signals transmitted through an optical fiber from the center site into radio frequency signals.

Abstract: In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.

Abstract: A demodulation section 13 receives a TDMA-TDD based phase-modulated burst signal of mobile communications and demodulates the burst signal by a synchronous detection system (or a quasi-synchronous detection system). The demodulation section 13 includes a frequency deviation compensation section and a carrier recovery section each having a loop filter 14 with three or more stages of time constants. The time constants are switched by a selector switch 15 based on a control signal from a demodulation control section 16. This achieves quick pull-in and jitter after convergence is minimized, thereby allowing highly efficient performance of frequency deviation compensation, etc. that is required for synchronous detection (or quasi-synchronous detection) without increasing the size of circuit.

Abstract: A clock and data recovery circuit including a phase synchronization loop including an oscillator, the oscillation frequency of which is variably controlled, the phase synchronization loop performing phase-synchronization of a clock signal output from the oscillator with an input data signal. The circuit also includes a discriminator circuit, responsive to a clock signal for discrimination, for discriminating the input data signal and outputting the discriminated signal. The circuit further includes a phase detector circuit for detecting the phase difference between an output data signal, discriminated and output by the discriminator circuit, and the input data signal. The circuit also includes a phase shift circuit for shifting the phase of the clock signal, output from the oscillator, based on a comparison result output from the phase detector circuit. The clock signal, which is output from the phase shift circuit, is supplied as the clock signal for discrimination to the discriminator circuit.

Abstract: A single sideband mixer circuit includes a voltage controlled oscillator operable a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1±f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1±f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1±f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr.

Abstract: In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed.

Abstract: Disclosed are a method and system for generating switching a timing signal for separating a transmitting and receiving signal in an optical repeater of a mobile telecommunication network by using a Time Division Duplex (hereinafter, referred to as “TDD”) scheme and an Orthogonal Frequency Division Multiplexing (hereinafter, referred to as “OFDM”) modulation scheme, which transmits a part of a RF signal extracted from a coupler included in a remote of an optical repeater to a switching timing signal generating circuit, locates a frame start position of a RF signal by correlating a reference signal generated in a switching timing signal generating circuit with a RF signal extracted from a coupler, and is capable of transmitting a RF signal by distinguishing between a downlink signal and a uplink signal by using a switching timing signal in a switch when calculating a starting point of a downlink signal and a uplink signal included in an RF signal on the basis of a frame starting location, generating a switching

Abstract: A circuit for detecting attacks by contacting an integrated circuit chip comprising means for applying a random signal to a first terminal of at least one conductive path formed in at least one first metallization level of the chip, means for comparing the applied signal with a signal present on a second terminal of the path, and means for delaying the comparison time with respect to the application time, of a duration longer than or equal to the propagation delay through the first path.