Phase Error Or Phase Jitter Patents (Class 375/226)
  • Patent number: 10411929
    Abstract: Provided are a preamble symbol receiving method and a receiving device, characterized in that: the received preamble symbol contains a time-domain symbol which is generated from a single three-segment structure by a transmitting end according to a predefined generation rule, the single three-segment structure containing: a time-domain main body signal, a prefix generated based on the entirety or a portion of the time-domain main body signal, and a postfix or a hyper prefix generated based on the entirety or a portion of the time-domain main body signal. Therefore, using the entirety or a portion of a certain length of a time-domain main body signal as a prefix, it is possible to implement coherent detection, which solves the issues of performance degradation with non-coherent detection and differential decoding failure under complex frequency selective fading channels.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Shanghai National Engineering Research Center of Digital Television Co., Ltd.
    Inventors: Ge Huang, Hongliang Xu, Guanbin Xing, Wenjun Zhang, Yunfeng Guan, Dazhi He
  • Patent number: 10402291
    Abstract: A checking device for a data preparation unit, including a preparation element for preparing sensor data for a data transmission; and a comparator for comparing the sensor data with the prepared sensor data; a fault of the data preparation unit being detected in the event that the prepared sensor data do not match the sensor data.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: September 3, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Matthias Kalisch, Ali Abbas Husaini, Christian Pfahler
  • Patent number: 10348412
    Abstract: An apparatus comprises an optical signal generator configured to provide a first radiation comprising a first nominal carrier frequency and a second nominal carrier frequency, and provide a second radiation comprising a third nominal carrier frequency and a fourth nominal carrier frequency; an optical to electrical converter coupled to the optical signal generator and configured to: generate a first electrical current based on the first radiation and the second radiation without the second radiation passing through the Device under Test (DUT); and generate a second electrical current based on the first radiation and the second radiation after the second radiation passes through the DUT; and a data processor configured to determine a transfer function of the DUT at the third nominal carrier frequency and the fourth nominal carrier frequency based on the first electrical current and the second electrical current.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 9, 2019
    Assignee: Nanjing University of Aeronautics and Astronautics
    Inventors: Min Xue, Yuqing Heng, Shilong Pan
  • Patent number: 10326538
    Abstract: Embodiments herein describe calibrating a plurality of radio heads having a plurality of wireless antennas. In one embodiment, the plurality of radio heads communicate a calibration signal in a round robin fashion such that each of the radio heads communicates a respective calibration signal to the remaining radio heads. The received calibration signals are then used to calibrate the radio heads. In one embodiment, a controller coupled with the plurality of radio heads calibrates the radio heads. The calibrated radio heads then communicate to one or more client devices.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 18, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Mithat C. Dogan, Jiunming Huang, Brian D. Hart, Matthew A. Silverman
  • Patent number: 10284361
    Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: May 7, 2019
    Assignee: MEDIATEK INC.
    Inventors: Li-Hung Chiueh, Tse-Hsien Yeh, Chen-Yu Hsiao
  • Patent number: 10281523
    Abstract: Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 7, 2019
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Naim Ben-Hamida, Chris Kurowski
  • Patent number: 10237765
    Abstract: A measuring instrument for detecting a source of passive intermodulation (PIM) includes a signal source, a reference signal source, and a first transmitter module and a second transmitter module each configured to receive a signal from the signal source and a reference signal from the reference signal source and generate a tone at a first frequency and a second frequency, respectively. The measuring instrument further includes a receiver and a receiver module configured to receive the signal from the signal source and a harmonic of the test signal generated by a source of PIM to generate a sample signal at the fixed frequency of the reference signal. The receiver is configured to determine a shift in phase between the reference signal and the sample signal. The receiver determines an estimate of distance to the source of PIM using determinations of the shift in phase as the signal source is swept.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 19, 2019
    Inventor: Donald Anthony Bradley
  • Patent number: 10218546
    Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 26, 2019
    Assignee: Cable Television Laboratories, Inc.
    Inventor: Thomas H. Williams
  • Patent number: 10103807
    Abstract: Disclosed are embodiments of an apparatus and method relating to an optical signal to noise ratio detection circuit, adopting an optical switch, a tunable optical filter, a photoelectric conversion module, a pilot-tone modulation signal conditioning module and a control module. After the photoelectric conversion module converts a to-be-detected optical signal to a voltage signal, the pilot-tone modulation signal conditioning module respectively amplifies an AC signal and a DC signal in the voltage signal, correspondingly converts the AC signal and the DC signal to two-way digital signals, determines a modulation depth of the pilot-tone modulation signal and a modulation depth of an ASE noise according to the two-way digital signals, and calculates an optical signal to noise ratio of the optical signal.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 16, 2018
    Inventor: Yadong Gong
  • Patent number: 10057049
    Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 21, 2018
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 9979498
    Abstract: The broadcast-signal transmitter according to one embodiment of the present invention includes: an encoder for encoding physical layer pipe (PLP) data, including a base layer and an enhancement layer of a broadcasting service, and signaling information through a SISO, and/or MIMO technique; a frame builder for generating a transmission frame, which includes a preamble having the encoded signaling information and the PLP data and an OFDM generator for modulating and transmitting a broadcast signal including the transmission frame.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 22, 2018
    Inventors: Woosuk Ko, Seoyoung Back, Sangchul Moon
  • Patent number: 9971975
    Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 15, 2018
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9959096
    Abstract: A method for generating random numbers on multiprocessor systems and a multiprocessor system for generating true random numbers, using the method, generate truly random numbers with high entropy in a multiprocessor system with little additional effort to chip area and power dissipation. The method includes the steps of: measuring a phase error signal of a clock generator circuit of a first and a second processing unit respectively, forwarding the phase error signal of the respective clock generator circuit of the first and second processing unit to a true random network, combining the phase error signal of the clock generator circuit of the first processing unit and the phase error signal of the clock generator circuit of the second processing unit in the true random network to random bit streams, picking-up a random bit stream of the true random network, passing the respective random bit stream back to a random generator of the respective processing unit for outputting true random.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: May 1, 2018
    Inventors: Sebastian Hoeppner, Felix Neumaerker, Andreas Dixius
  • Patent number: 9909907
    Abstract: A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 6, 2018
    Assignee: Tektronix, Inc.
    Inventors: Jan P. Peeters Weem, Klaus M. Engenhardt, Laszlo J. Dobos
  • Patent number: 9876697
    Abstract: A jitter measuring setup (10) comprises a signal generator (14), a sample-and-hold circuit (15), and the inventive all stochastic jitter measuring device (1) comprising signal acquisition means (2) and calculation means (3). The input signal of the sample-and-hold circuit (15) is generated by the signal generator (14). Furthermore, the output signal of the sample-and-hold circuit (15), respectively the input signal of the measuring device (1), is comprised of a superposition of the sampled input signal of the sample-and-hold circuit (15) and a cyclostationary random process.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 23, 2018
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Thomas Schweiger
  • Patent number: 9813282
    Abstract: A sampling phase difference compensation apparatus includes a signal generator, a signal analyzer and a compensator. The signal generator generates a first signal and a second signal, and outputs the first and second signals to a first path in a first time interval and a second path in a second time interval, respectively. The signal analyzer receives a transmitted first signal from the first path and a transmitted second signal from the second path, and performs a predetermined calculation on the transmitted first and second signals to determine a phase difference relationship, which is associated with a frequency-dependent phase difference and a sampling phase difference, between the transmitted first and second signals. The transmitted first signal is associated with the first signal, and the transmitted second signal is associated with the second signal. The compensator performs a phase difference compensation according to the phase difference relationship.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 7, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Po-Hung Liu, Tzu-Yi Yang, Teng-Han Tsai, Tai-Lai Tung
  • Patent number: 9805787
    Abstract: A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 31, 2017
    Inventor: Kyung-soo Ha
  • Patent number: 9791492
    Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 17, 2017
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Jaeha Kim, Brian Liebowitz
  • Patent number: 9767921
    Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Dong Pan
  • Patent number: 9740580
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for enhancing margin in a serial data transfer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 22, 2017
    Inventors: Mohammad Mobin, Bruce A. Wilson, Haitao Xia
  • Patent number: 9672884
    Abstract: A semiconductor device includes a division period signal generation circuit and a clock sampling circuit. The division period signal generation circuit generates a division period signal which is enabled in synchronization with a write period that is set according to a write command and latency information. The clock sampling circuit samples an internal strobe signal to output a sampling clock signal in response to the division period signal and the internal strobe signal during a sampling period. The sampling period is set to be longer than the write period.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 9672089
    Abstract: A system and method for calculating a bit error rate for a mask is described. For each time during the time duration of the mask, the minimum and maximum voltages of the mask at that time are determined. The maximum bit error rate can be calculated for each time by integrating between those voltages. The maximum bit error rate for all times during the time duration of the mask can be selected as the maximum bit error rate for the mask.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: June 6, 2017
    Assignee: TEKTRONIX, INC.
    Inventor: Richard J. Poulo
  • Patent number: 9571266
    Abstract: This invention relates to methods and systems for estimating skew based on, for example, the IEEE 1588 Precision Time Protocol (PTP). These methods and systems can allow the clock skew between a master clock (server) and slave clock (client) exchanging PTP messages over a packet network to be estimated. In one embodiment, the slave employs a digital phase-locked loop (DPLL) driven by timestamps supplied from a master clock. The slave is able to process the timestamp information embedded in PTP Sync and Follow_Up messages in order to lock its frequency to that of the master clock. In certain embodiments a frequency locked DPLL and a local free-running counter are used to estimate the skew of the local slave oscillator.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 14, 2017
    Assignees: British Telecommunications PLC, Khalifa University of Science Technology, and Research, Emirates Telecommunications Corporation
    Inventors: James Aweya, Ivan Boyd
  • Patent number: 9467211
    Abstract: Frequency-selective phase shifts are applied to signals transmitted from multiple transmission points involved in a coordinated (joint) transmission to a given UE. An eNodeB or other network node controlling the joint transmission artificially induces frequency selectivity between signals received by the UE in joint transmission from different transmission points, so as to ensure an even balance between constructive and destructive combination over frequency. By applying frequency-selective phase shifts (e.g., pseudo-random phase shifts) to the different transmission points that perform joint transmission, the signals from the different transmission points are forced to combine at the UE in a non-coherent manner. As a result, uncertainty in how the signals combine is drastically reduced, since it can be expected that the signals will always combine incoherently. The reduced uncertainty translates to reduced back-off offset in the link adaptation, and thus in an increased throughput.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 11, 2016
    Inventors: David Hammarwall, Svante Bergman
  • Patent number: 9395706
    Abstract: A noise determination device is provided that determines the presence of noise on an input signal with a constant value that is output from an external device. The noise determination device includes a sampling unit that performs three samplings on the input signal, a sampling-interval setting unit that sets an interval between a first one and a second one of the samplings to have a value that is different from an integral multiple of the period of the periodic noise, and sets an interval between the second one and a third one of the samplings to be equal to or larger than an interval that is large enough to fully attenuate the periodic noise, and a noise determination unit that determines that the noise is not superimposed on the input signal only when all values acquired by the first, second, and third samplings match one another.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: July 19, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomoya Furukawa, Kengo Kato
  • Patent number: 9369269
    Abstract: Described are methods, devices and systems for communicating data measurements from a sampling device to a remote master device in a distributed power measurement system using high-speed isochronous data links. The sampling device receives a time-stamp packet from the master device over the isochronous data link, the time-stamp packet containing a sequence number of the time-stamp packet, and the sampling device starts a counter clocked by a local clock signal to determine an offset time since receipt of the time-stamp packet. The sampling device obtains power system data and generates and transmits framed output data to the remote master device over the isochronous data link. The framed output data includes the sequence number, the offset time, and a data payload that includes the power system data.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 14, 2016
    Inventors: Donald Jeffrey Dionne, Jennifer Marie McCann
  • Patent number: 9329967
    Abstract: Method and related systems are described for navigating through information related to the status of one or more layers of a signal, such as a serial or parallel bus. Information may be displayed by selecting fields within a visual depicted on an oscilloscope or similar measuring instrument. By selecting particular fields, and indicators, different aspects of a layer may be analyzed without the need to have extensive knowledge of the operation of the measuring instrument.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 3, 2016
    Assignee: TEKTRONIX, INC.
    Inventors: Keith D. Rule, Walter R. Strand, Keith A. Olson, Michael J. Wadzita, Steve M. Mishler
  • Patent number: 9325554
    Abstract: The present technique relates to a receiving device, a receiving method, and a program for realizing a prompt start of data demodulation. A receiving device of one aspect of the present technique includes: a detecting unit that detects a first preamble signal from a frame signal having a frame structure that contains the first preamble signal indicating a frame partition, a second preamble signal containing control information to be used in processing a data signal, and the data signal, the second preamble signal being transmitted after the first preamble signal; an accumulating unit that accumulates the second preamble signal when the first preamble signal is detected; and a processing unit that processes the data signal based on the control information contained in the second preamble signal accumulated in the accumulating unit, the data signal being contained in the same frame as the second preamble signal accumulated in the accumulating unit.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: April 26, 2016
    Inventors: Takashi Yokokawa, Yuken Goto, Kenichi Kobayashi
  • Patent number: 9307549
    Abstract: To support very high QAM rates, a user equipment (UE) needs extremely good signal-to-noise ratio (SNR). Using a receiver configuration that improves SNR comes at the expense of higher power consumption. However, consuming higher power to support very high QAM rates when poor channel conditions are present is a waste of power. By correlating the modulation and coding scheme used by the UE with the UE channel quality estimate, the UE can modify the receiver configuration to improve SNR only when channel conditions support very high QAM rates.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Udara Charman Fernando, Supratik Bhattacharjee, Valentin Alexandru Gheorghiu, Gene Fong
  • Patent number: 9298875
    Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 29, 2016
    Inventors: Shaojie Xu, Yukit Tang, Pao-Po Hou, Derek C. Tao, Annie-Li-Keow Lum
  • Patent number: 9287979
    Abstract: Methods, systems, and devices are described for modulating and demodulating data on optical signals. During modulation, at least one stream of symbol mapped bits is filtered with at least one pulse shaping filter to reduce a bandwidth of the stream of bits and to pre-compensate for at least one identified non-ideal transmission condition. The filtered bits are modulated onto a waveform in the digital domain, and the modulated filtered bits are transmitted to digital-to-analog converter. The output of the digital-to-analog converter is converted to an optical signal. During demodulation, a received optical signal is sampled at a first sampling rate at an ADC, downsampled to a lower sampling rate for filtering, filtered with at least one discrete pulse-shaping filter, upsampled for equalization and demodulation, and then equalized and demodulated.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: March 15, 2016
    Assignee: ViSat, Inc.
    Inventors: Sameep Dave, Matthew Nimon, Fan Mo, William Thesling
  • Patent number: 9240892
    Abstract: A Method and Apparatus for Reduction of Communications Media Energy Consumption have been disclosed. Media energy consumption can be reduced by mapping a periodic data pattern in data to an alternate data pattern that consumes less energy when the alternate pattern is transmitted on the communications media in place of the original data pattern. The detection of the original selected patterns and the choice of replacement patterns may be made automatically or according to the transmission state (for example, idle or alarm).
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: January 19, 2016
    Inventor: Jeremy Bicknell
  • Patent number: 9203574
    Abstract: A method of UE RSRQ measurement precaution for interference coordination is provided. The UE receives radio signals of a neighbor cell under measurement. The neighbor cell applies a TDM silencing pattern for inter-cell interference coordination (TDM ICIC). The UE determines a measurement pattern that includes multiple subframes. The UE performs RSRQ measurements of the cell over multiple subframes and obtains multiple RSRQ measurement samples. The UE derives RSRQ measurement result by estimating the multiple RSRQ samples and applying a weighted average. RSRQ samples estimated to be more applicable are taken into account to more extent (e.g., applied with more weight), and/or RSRQ samples estimated to be less applicable are taken into account to less extent (e.g., applied with less weight, or discarded with zero weight). With UE precaution, a more predictable RSRQ measurement result is produced.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 1, 2015
    Assignee: MEDIATEK INC.
    Inventors: Per Johan Mikael Johansson, William Plumb, Yih-Shen Chen
  • Patent number: 9160355
    Abstract: A printed circuit board includes a sending element, a plurality of receiving elements, and a control unit. The sending element is configured to generate a sending signal. The receiving elements are configured to receive a control signal respectively. The control unit is coupled to the sending element through a first wire and to the receiving elements through a plurality of second wires. The control unit is provided with a comparison table that stores related information of the second wires. When receiving the sending signal, the control unit generates the control signals according the related information of the second wires. At least one of the control signals is transmitted to the corresponding receiving element, and the rest of the control signals are delayed for a preset time and then transmitted to the rest of the receiving elements.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 13, 2015
    Inventors: Xin-Guo Jin, Hui-Yi Wu, Lian-Yin Zhu
  • Patent number: 9157950
    Abstract: A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark Ferriss, Arun S. Natarajan, Benjamin D. Parker, Alexander V. Rylyakov, Jose A. Tierno, Soner Yaldiz
  • Patent number: 9124332
    Abstract: Embodiments of the present invention provide a method, an apparatus, and a system for interference alignment. The method includes: receiving signals transmitted by transmit ends, where the signals include interference signals and a wanted signal; aligning original constellation diagrams of the interference signals to acquire a first interference aligned constellation diagram; performing, according to the first interference aligned constellation diagram, interference signal demodulation and decoding on the received signals to acquire an interference source bit sequence; performing, according to the interference source bit sequence and the first interference aligned constellation diagram, interference reconstruction and removal to acquire a second interference aligned constellation diagram; and performing, according to the second interference aligned constellation diagram, wanted signal demodulation and decoding on the signal sequence to acquire the wanted signal transmitted by a wanted signal transmit end.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: September 1, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Rui Wang, Yinggang Du, Hong Cheng
  • Patent number: 9118944
    Abstract: A method is provided in one example embodiment and includes receiving video data and gathering statistics associated with the video data. At least some of the video data is broken into slices, each of the slices representing a partition in a video frame within the video data. Each frame is encoded with one or more quality layers based on an outgoing rate and based on a number of central processing unit (CPU) cycles, wherein one or more quality layers of the frames are dropped in the encoding process. In more specific embodiments, the statistics relate to how many bits are used for encoding the quality layers of the video data and how much complexity is required for encoding the quality layers of the video data. After the statistics gathering, adjustments to a network rate are executed.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: August 25, 2015
    Inventors: Jim Chen Chou, Rui Zhang
  • Patent number: 9100758
    Abstract: A sound pressure assessment system determines sounds to be presented by referring to a database retaining data of sounds, each of which is a pure tone. The system presents the determined sound as a first sound, and in a predetermined time after presenting the first sound, presents as a second sound a sound at least having the same frequency and the same sound pressure level as those of the first sound to the user. The system extracts an amount of change from an N1 component in response to the first sound to that in response to the second sound. The N1 components are negative components of an user's event-related potential based on points of presenting the first and second sounds as respective starting points. The system determines whether the sound pressure level of the presented sound is excessive to the user, based on the amount of change.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: August 4, 2015
    Assignee: Panasonic Corporation
    Inventors: Shinobu Adachi, Yumiko Kato, Koji Morikawa, Jun Ozawa, Hiroshi Nittono
  • Patent number: 9088331
    Abstract: The first and second outputs of a signal generation system are coupled to the first and second inputs of a signal digitizing system via respective electrical conductors. A controller directs the generation system to generate a first calibration signal, and the digitizing system responsively captures a first set of vector samples. The conductors are then reconfigured so they connect the first and second outputs of the generation system respectively to the second and first inputs of the digitization system. The controller then directs the generation system to generate a second calibration signal, and the digitizing system responsively captures a second set of vector samples. The controller or other processing agent computes gain and/or phase impairments using the first and second vector sample sets. Digital filter parameters may be computed based on the computed impairment(s), and used to correct the impairment(s) of the generation system and/or the digitizing system.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: July 21, 2015
    Assignee: National Instruments Corporation
    Inventor: Stephen L. Dark
  • Patent number: 9036760
    Abstract: An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 19, 2015
    Inventors: Keita Hayakawa, Hironobu Akita, Hirofumi Yamamoto
  • Patent number: 9031122
    Abstract: A communication device that is configured for reducing phase errors is described. The communication device includes a processor and instructions stored in memory. The communication device calculates a sum channel in the frequency domain, estimates one or more impulse responses and isolates an impulse response for one or more wireless communication devices. The communication device also calculates a phase error for each wireless communication device and reduces the phase error for each wireless communication device.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 12, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Didier Johannes Richard Van Nee
  • Patent number: 9032274
    Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: May 12, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shadi M. Barakat, Bhuvanachandran K. Nair, Paul-Hugo Lamarche
  • Publication number: 20150124861
    Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicants: TeraSquare Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: HyunMin BAE, Joon Yeong LEE, Jin Ho PARK, Tae Ho KIM
  • Patent number: 9025716
    Abstract: An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line being provided for the transmission of a data input signal and a data output signal, the clock line being provided for the transmission of a clock signal, the clock line having a first delay element, and the data line having a second delay element and a third delay element. A method for operating an I2C slave interface is also provided.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 5, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Dorde Cvejanovic
  • Patent number: 9025693
    Abstract: Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventors: John Wang, Vasudevan Parthasarathy
  • Patent number: 9008237
    Abstract: A method for symbol detection includes assigning a received symbol to at least one particular candidate symbol of a set of candidate symbols of a finite candidate symbol alphabet based on a metric between the received symbol and the at least one particular candidate symbol, the metric comprising contributions with respect to channel-based information and contributions with respect to a priori information.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: April 14, 2015
    Assignee: Intel IP Corporation
    Inventors: Franz Eder, Tobias Kurpjuhn, Ernst Martin Witte
  • Patent number: 9008712
    Abstract: A method of handling a plurality of time offsets between a communication device of a wireless communication system and a plurality of transmission points of the wireless communication system is disclosed. The method is utilized in the communication device, and comprises obtaining the plurality of time offsets by using a first reference signal; and transmitting the plurality of time offsets to the plurality of transmission points, respectively; wherein the plurality of transmission points compensate the plurality of time offsets, respectively, when communicating with the communication device.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 14, 2015
    Assignee: Industrial Technology Research Institute
    Inventor: Chung-Lien Ho
  • Patent number: 9001878
    Abstract: Systems, apparatuses and methods are disclosed for estimating a signal travel time, and thus distance between transceivers, in an orthogonal frequency division multiplexing (OFDM) system. The signal travel time is measured between a transmit time (tT) and a receive window time (twindow) adjusted by the phase delay (T?). The phase delay (T?) is determined as a difference between a receive time (tR) and the receive window time (twindow). The receive time (tR) may be determined based on either an amplitude of the received signal at the receive window time (twindow) or when the received signal crosses a positive-negative axis. In synchronous systems, either a one-way time (OWT) or round-trip time (RTT) may be used for estimation. In asynchronous systems, an RTT is used for estimation.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: April 7, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Rayman Wai Pon, Dominic Gerard Farmer
  • Publication number: 20150092828
    Abstract: A system and method consistent with the present disclosure includes determining a jitter tolerance of a particular lane of a communication link corresponding to each of a plurality of equalization coefficients. Further, determining a particular equalization coefficient of the plurality of equalization coefficients that provides a maximum jitter tolerance. Next, using the particular equalization coefficient for the particular lane of the communication link during operation based on determining the particular equalization coefficient which provides the maximum jitter tolerance.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Nathaniel L. Desimone, Theodore Z. Schoenborn, Earl Wight, Duane Heller, Maria F. Pineda
  • Patent number: 8995517
    Abstract: The present invention relates to a device for the location of passive intermodulation faults in a coaxial cable network. The test apparatus (100) according to one embodiment of the present invention utilizes a pair of high-power, frequency-synthesized, unmodulated RF carriers v1(t) (101) and v2(t) (102) are generated inside the HPA module of the apparatus. The power and frequency of v1(t) (101) and v2(t) (102) can be independently set to a range of values, v1(t), v2(t) are combined inside the instrument and then applied to the input of the device under test (DUT). The PIM signals (107,108,109) generated in the DUT are combined to produce the primary PIM signal vIM(t) (103). The apparatus also includes two receivers (110,111, 112,113,114,115) for the detection of vIM(t) 103 and vREF(t) (104). These signals are downconverted to 455 kHz.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: March 31, 2015
    Assignee: Kaelus Pty Ltd
    Inventors: Greg Delforce, Brendan Horsfield