Abstract: A method of optimizing at least one IQMC parameter value for an IQMC includes: generating a set of tested IQMC candidate parameter values by performing an iterative method including selecting a first IQMC candidate parameter value for the at least one parameter of the IQMC; determining, using the first IQMC candidate parameter value, a performance metric value that comprises at least one of (i) an image rejection ratio (IRR) value, (ii) a signal-to-interference-plus-noise ratio (SINR) value, or (iii) a signal-to-image ratio (SImR) value; and determining a second IQMC candidate parameter value that is an update to the first IQMC candidate parameter value. The method of optimizing at least one IQMC parameter value for an IQMC further includes determining an IQMC candidate parameter value of the set of tested IQMC candidate parameter values that optimizes the performance metric.

Abstract: A system is provided to analyze distortion in an electronic or electromechanical device, which may include testing with one or more modulated signals and/or with one or more demodulators. In one embodiment a change in pitch (or frequency) is measured at an output of the device. One or more signals from a demodulator output may be measured for an amplitude, noise, phase, aliasing, spurious signal, and/or frequency modulation effect. In another embodiment a musical signal may be used as a test signal. Providing additional test signals to the device can induce a cross-modulation distortion signal (or time varying cross-modulation distortion signal) from an output of the device. Also utilizing at least one additional filter, filter bank, demodulator and or frequency converter and or frequency multiplier provides extra examination of distortion.

Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.

Abstract: Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.

Abstract: A method includes determining a droop component of a measured parameter of a device under test (DUT). The measured parameter is responsive to an excitation signal having a frequency component, and the droop component is determined responsive to a first value of the parameter at a first time and a second value of the parameter at a second time. The parameter at the first time has a first phase value, and the parameter at the second time has a second phase value. The first phase value is equal to the second phase value. The method also includes correcting a frequency domain representation of the parameter by applying the droop component at a frequency of the representation of the parameter corresponding to the frequency component of the excitation signal.

Abstract: A method and system corrects a content delivery infrastructure. The method of the system includes receiving a request to resolve reported issues for the content delivery infrastructure, collecting content delivery metrics for the content delivery infrastructure, executes a language transformer model on the request and the content delivery metrics to generate a set of possible resolutions with confidence ratings, and implementing an automated solution based on a resolution from the set of possible resolutions, in response to the resolution having a confidence rating above a threshold.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A terminal and method of the terminal in a wireless communication system are provided. The terminal includes at least one transceiver and at least one processor operatively connected to the at least one transceiver. The at least one processor is configured to acquire synchronization information of a first beam which is a serving beam, update the synchronization information based on the first beam or at least one second beam, determine at least one channel quality of the at least one second beam based on the updated synchronization information, and update the serving beam based on the at least one channel quality.

Abstract: The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

Abstract: The disclosure relates to technology for compensating for I/Q imbalance. An apparatus includes I-path circuitry having a first analog filter configured to filter an I-path signal and Q-path circuitry having a second analog filter configured to filter a Q-path signal. An I/Q imbalance compensation circuit of the apparatus is configured to process digital versions of the I-path signal and the Q-path signal to compensate for mismatch between the I-path circuitry and the Q-path circuitry. A first circuit of the apparatus is configured to apply a coarse adjustment to at least one of the first analog filter or the second analog filter to reduce an initial mismatch between the I-path circuitry and the Q-path circuitry. The first circuit is configured to operate the I/Q imbalance compensation circuit to compensate for a residual mismatch between the I-path circuitry and the Q-path circuitry with the coarse adjustment applied.

Abstract: An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

Abstract: A test and measurement instrument for analyzing signals using machine learning. The test and measurement instrument can determine a recovered clock signal based on the digital signal, set window positions for a fast Fourier transform of the digital signal, window the digital signal into a series of windowed waveform data based on the window positions, transform each of the windowed waveform data into a frequency-domain windowed waveform data using a fast Fourier transform, and determine high-order spectrum data of each of the frequency-domain windowed waveform data. The test and measurement instrument includes a neural network configured to receive the high-order spectrum data of the frequency-domain windowed transform data and classify each windowed waveform data based on the high-order spectrum data.

Abstract: A receiving device 100 includes a reception unit 10, a delay signal generation unit 22, a difference calculation unit 23 that calculates a phase difference between the received signal and the delay signal, a variance calculation unit 24 that calculates a variance of the phase difference within a plurality of calculation sections while sliding a set of the plurality of calculation sections which are set corresponding to a cyclic prefix group assigned to a predetermined symbol group included in the received signal, together on the time axis, a symbol detecting unit 25 that detects a position of a symbol in the symbol group on the time axis, based on the position of the minimum peak of the variance on the time axis, and a synchronization timing signal generation unit 29 that generates a synchronization timing signal, based on information on the position of the symbol on the time axis.

Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Abstract: A correlation function having a clear peak is generated even in an environment in which an ambient noise level is high. A correlation function generation apparatus (100) includes a plurality of input signal obtaining units (101), a changing unit (102), a cross-spectrum calculator (103), a variance calculator (104), and a correlation function calculator (105). The input signal obtaining unit (101) obtains a wave generated by a wave source as an input signal. The transformer (102) obtains a plurality of frequency domain signals by transforming a plurality of input signals obtained by the plurality of input signal obtaining units. The cross-spectrum calculator (103) calculates a cross-spectrum based on the plurality of frequency domain signals. The variance calculator (104) calculates the variance of the cross-spectrum. The correlation function calculator (105) calculates and generates a correlation function based on the cross-spectrum and the variance.

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A terminal and method of the terminal in a wireless communication system are provided. The terminal includes at least one transceiver and at least one processor operatively connected to the at least one transceiver. The at least one processor is configured to acquire synchronization information of a first beam which is a serving beam, update the synchronization information based on the first beam or at least one second beam, determine at least one channel quality of the at least one second beam based on the updated synchronization information, and update the serving beam based on the at least one channel quality.

Abstract: A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

Abstract: [Problem] To select an optimal transmission path having a minimum total MTIE value of total MTIE values between a plurality of master apparatuses configured to transmit time information serving as a reference and a specific relay apparatus configured to receive the time information via a plurality of relay apparatuses to achieve time synchronization. [Solution] A time path selection apparatus 30 selects a transmission path employed for time synchronization, on the basis of a MTIE value evaluated in each of relay apparatuses 13 to 16, between master apparatuses 11 and 12 configured to transmit time information serving as a reference and a relay apparatus 15 or 16 at an edge configured to receive the time information via a relay apparatus 13 or 14 to achieve the time synchronization.

Abstract: The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.

Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.

Abstract: The disclosure discloses a phase delay extraction and compensation method in a PGC phase demodulation technology. The sinusoidal phase modulation interference signal is converted into a digital interference signal by an analog-to-digital converter after amplification and filtering, and the digital interference signal is subjected to orthogonal downmixing of first-order, second-order, and fourth-order harmonics simultaneously to obtain three pairs of orthogonal harmonic amplitude signals.

Abstract: In one aspect, an apparatus includes: a buffer to store orthogonal frequency division multiplexing (OFDM) samples of one or more OFDM symbols; a fast Fourier transform (FFT) engine coupled to the buffer, the FFT engine to receive the one or more OFDM samples from the buffer and convert each of the one or more OFDM samples into a plurality of frequency domain sub-carriers; and a timing control circuit coupled to the buffer. The timing control circuit may control timing based at least in part on a difference between a first correlation sum for a first portion of a cyclic prefix of a first one of the one or more OFDM symbols and a second correlation sum for a second portion of the cyclic prefix.

Abstract: Residual noise of a frequency mixer is detected. A reference clock is used to generate a first radio frequency (RF) signal, a second RF signal and a third RF signal. The first RF signal and the second RF signal serve as input to the frequency mixer. The reference clock is used to generate a third RF signal. The reference clock is also used to control timing in a detector device. A second frequency mixer mixes an output of the DUT with the third RF signal to produce an input signal for a detector device. Mixing the output of the DUT with the third RF signal cancels at least some of the phase noise within the output signal of the DUT that results from phase noise in the first RF signal and from phase noise in the second RF signal. The detector device detects residual phase noise existing within the input signal for the detector device.

Abstract: The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.

Abstract: Provided are a preamble symbol generation method and receiving method, and a relevant frequency-domain symbol generation method and a relevant device, characterized in that the method comprises: generating a prefix according to a partial time-domain main body signal truncated from a time-domain main body signal; generating the hyper prefix according to the entirety or a portion of the partial time-domain main body signal; and generating time-domain symbol based on at least one of the cyclic prefix, the time-domain main body signal and the hyper prefix, the preamble symbol containing at least one of the time-domain symbols.

Abstract: The data recovery from sub-carriers (DRSC) of a received OFDM signal, contributes a method and a circuit for utilizing parameters of OFDM sub-carriers comprised in the received OFDM signal or subspaces comprising the OFDM sub-carriers for recovering transmitted data symbols from the received OFDM signal affected by deterministic and random distortions introduced by a transmission link.

Abstract: In a communication device and corresponding methods to determine a phase offset imbalance, an input signal (e.g. oscillator signal) is phase shifted to generate a set of phase-shifted values. The set of phased-shifted values and the input signal are mixed to generate a respective set of mixed signals. The phase offset imbalance (e.g. phase error) is calculated based on the set of mixed signals and a gradient value.

Abstract: In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data.

Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.

Abstract: A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: Provided are a preamble symbol receiving method and a receiving device, characterized in that: the received preamble symbol contains a time-domain symbol which is generated from a single three-segment structure by a transmitting end according to a predefined generation rule, the single three-segment structure containing: a time-domain main body signal, a prefix generated based on the entirety or a portion of the time-domain main body signal, and a postfix or a hyper prefix generated based on the entirety or a portion of the time-domain main body signal. Therefore, using the entirety or a portion of a certain length of a time-domain main body signal as a prefix, it is possible to implement coherent detection, which solves the issues of performance degradation with non-coherent detection and differential decoding failure under complex frequency selective fading channels.

Abstract: A checking device for a data preparation unit, including a preparation element for preparing sensor data for a data transmission; and a comparator for comparing the sensor data with the prepared sensor data; a fault of the data preparation unit being detected in the event that the prepared sensor data do not match the sensor data.

Abstract: An apparatus comprises an optical signal generator configured to provide a first radiation comprising a first nominal carrier frequency and a second nominal carrier frequency, and provide a second radiation comprising a third nominal carrier frequency and a fourth nominal carrier frequency; an optical to electrical converter coupled to the optical signal generator and configured to: generate a first electrical current based on the first radiation and the second radiation without the second radiation passing through the Device under Test (DUT); and generate a second electrical current based on the first radiation and the second radiation after the second radiation passes through the DUT; and a data processor configured to determine a transfer function of the DUT at the third nominal carrier frequency and the fourth nominal carrier frequency based on the first electrical current and the second electrical current.

Abstract: Embodiments herein describe calibrating a plurality of radio heads having a plurality of wireless antennas. In one embodiment, the plurality of radio heads communicate a calibration signal in a round robin fashion such that each of the radio heads communicates a respective calibration signal to the remaining radio heads. The received calibration signals are then used to calibrate the radio heads. In one embodiment, a controller coupled with the plurality of radio heads calibrates the radio heads. The calibrated radio heads then communicate to one or more client devices.

Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

Abstract: Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.

Abstract: A measuring instrument for detecting a source of passive intermodulation (PIM) includes a signal source, a reference signal source, and a first transmitter module and a second transmitter module each configured to receive a signal from the signal source and a reference signal from the reference signal source and generate a tone at a first frequency and a second frequency, respectively. The measuring instrument further includes a receiver and a receiver module configured to receive the signal from the signal source and a harmonic of the test signal generated by a source of PIM to generate a sample signal at the fixed frequency of the reference signal. The receiver is configured to determine a shift in phase between the reference signal and the sample signal. The receiver determines an estimate of distance to the source of PIM using determinations of the shift in phase as the signal source is swept.

Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.

Abstract: Disclosed are embodiments of an apparatus and method relating to an optical signal to noise ratio detection circuit, adopting an optical switch, a tunable optical filter, a photoelectric conversion module, a pilot-tone modulation signal conditioning module and a control module. After the photoelectric conversion module converts a to-be-detected optical signal to a voltage signal, the pilot-tone modulation signal conditioning module respectively amplifies an AC signal and a DC signal in the voltage signal, correspondingly converts the AC signal and the DC signal to two-way digital signals, determines a modulation depth of the pilot-tone modulation signal and a modulation depth of an ASE noise according to the two-way digital signals, and calculates an optical signal to noise ratio of the optical signal.

Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Abstract: The broadcast-signal transmitter according to one embodiment of the present invention includes: an encoder for encoding physical layer pipe (PLP) data, including a base layer and an enhancement layer of a broadcasting service, and signaling information through a SISO, and/or MIMO technique; a frame builder for generating a transmission frame, which includes a preamble having the encoded signaling information and the PLP data and an OFDM generator for modulating and transmitting a broadcast signal including the transmission frame.

Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

Abstract: A method for generating random numbers on multiprocessor systems and a multiprocessor system for generating true random numbers, using the method, generate truly random numbers with high entropy in a multiprocessor system with little additional effort to chip area and power dissipation. The method includes the steps of: measuring a phase error signal of a clock generator circuit of a first and a second processing unit respectively, forwarding the phase error signal of the respective clock generator circuit of the first and second processing unit to a true random network, combining the phase error signal of the clock generator circuit of the first processing unit and the phase error signal of the clock generator circuit of the second processing unit in the true random network to random bit streams, picking-up a random bit stream of the true random network, passing the respective random bit stream back to a random generator of the respective processing unit for outputting true random.

Abstract: A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.

Abstract: A jitter measuring setup (10) comprises a signal generator (14), a sample-and-hold circuit (15), and the inventive all stochastic jitter measuring device (1) comprising signal acquisition means (2) and calculation means (3). The input signal of the sample-and-hold circuit (15) is generated by the signal generator (14). Furthermore, the output signal of the sample-and-hold circuit (15), respectively the input signal of the measuring device (1), is comprised of a superposition of the sampled input signal of the sample-and-hold circuit (15) and a cyclostationary random process.

Abstract: A sampling phase difference compensation apparatus includes a signal generator, a signal analyzer and a compensator. The signal generator generates a first signal and a second signal, and outputs the first and second signals to a first path in a first time interval and a second path in a second time interval, respectively. The signal analyzer receives a transmitted first signal from the first path and a transmitted second signal from the second path, and performs a predetermined calculation on the transmitted first and second signals to determine a phase difference relationship, which is associated with a frequency-dependent phase difference and a sampling phase difference, between the transmitted first and second signals. The transmitted first signal is associated with the first signal, and the transmitted second signal is associated with the second signal. The compensator performs a phase difference compensation according to the phase difference relationship.

Abstract: A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.