Phase Error Or Phase Jitter Patents (Class 375/226)
  • Patent number: 11449697
    Abstract: A test and measurement instrument for analyzing signals using machine learning. The test and measurement instrument can determine a recovered clock signal based on the digital signal, set window positions for a fast Fourier transform of the digital signal, window the digital signal into a series of windowed waveform data based on the window positions, transform each of the windowed waveform data into a frequency-domain windowed waveform data using a fast Fourier transform, and determine high-order spectrum data of each of the frequency-domain windowed waveform data. The test and measurement instrument includes a neural network configured to receive the high-order spectrum data of the frequency-domain windowed transform data and classify each windowed waveform data based on the high-order spectrum data.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 20, 2022
    Assignee: Tektronix, Inc.
    Inventor: John J. Pickerd
  • Patent number: 11362876
    Abstract: A receiving device 100 includes a reception unit 10, a delay signal generation unit 22, a difference calculation unit 23 that calculates a phase difference between the received signal and the delay signal, a variance calculation unit 24 that calculates a variance of the phase difference within a plurality of calculation sections while sliding a set of the plurality of calculation sections which are set corresponding to a cyclic prefix group assigned to a predetermined symbol group included in the received signal, together on the time axis, a symbol detecting unit 25 that detects a position of a symbol in the symbol group on the time axis, based on the position of the minimum peak of the variance on the time axis, and a synchronization timing signal generation unit 29 that generates a synchronization timing signal, based on information on the position of the symbol on the time axis.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: June 14, 2022
    Assignee: ANRITSU CORPORATION
    Inventor: Atsuki Morita
  • Patent number: 11349689
    Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: May 31, 2022
    Assignee: eTopus Technology Inc.
    Inventors: Kai Keung Chan, Danfeng Xu, Yu Kou
  • Patent number: 11336997
    Abstract: A correlation function having a clear peak is generated even in an environment in which an ambient noise level is high. A correlation function generation apparatus (100) includes a plurality of input signal obtaining units (101), a changing unit (102), a cross-spectrum calculator (103), a variance calculator (104), and a correlation function calculator (105). The input signal obtaining unit (101) obtains a wave generated by a wave source as an input signal. The transformer (102) obtains a plurality of frequency domain signals by transforming a plurality of input signals obtained by the plurality of input signal obtaining units. The cross-spectrum calculator (103) calculates a cross-spectrum based on the plurality of frequency domain signals. The variance calculator (104) calculates the variance of the cross-spectrum. The correlation function calculator (105) calculates and generates a correlation function based on the cross-spectrum and the variance.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 17, 2022
    Assignee: NEC CORPORATION
    Inventors: Masanori Kato, Yuzo Senda
  • Patent number: 11327524
    Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: May 10, 2022
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Abhijit M. Abhyankar, Kun-Yung Chang, Frank Lambrecht
  • Patent number: 11259257
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A terminal and method of the terminal in a wireless communication system are provided. The terminal includes at least one transceiver and at least one processor operatively connected to the at least one transceiver. The at least one processor is configured to acquire synchronization information of a first beam which is a serving beam, update the synchronization information based on the first beam or at least one second beam, determine at least one channel quality of the at least one second beam based on the updated synchronization information, and update the serving beam based on the at least one channel quality.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doyoung Jung, Sangkyou Ryou, Ingil Baek, Junhee Jeong
  • Patent number: 11239992
    Abstract: A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: February 1, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Michael Wang, Kyunglok Kim
  • Patent number: 11240141
    Abstract: [Problem] To select an optimal transmission path having a minimum total MTIE value of total MTIE values between a plurality of master apparatuses configured to transmit time information serving as a reference and a specific relay apparatus configured to receive the time information via a plurality of relay apparatuses to achieve time synchronization. [Solution] A time path selection apparatus 30 selects a transmission path employed for time synchronization, on the basis of a MTIE value evaluated in each of relay apparatuses 13 to 16, between master apparatuses 11 and 12 configured to transmit time information serving as a reference and a relay apparatus 15 or 16 at an edge configured to receive the time information via a relay apparatus 13 or 14 to achieve the time synchronization.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 1, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ryuta Sugiyama, Kaoru Arai, Hiroki Sakuma, Takaaki Hisashima, Shunichi Tsuboi, Osamu Kurokawa, Kazuyuki Matsumura
  • Patent number: 11239991
    Abstract: The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: February 1, 2022
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Benjamin P. Smith, Jamal Riani
  • Patent number: 11184202
    Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 23, 2021
    Assignee: Cable Television Laboratories, Inc.
    Inventor: Thomas H. Williams
  • Patent number: 11168975
    Abstract: The disclosure discloses a phase delay extraction and compensation method in a PGC phase demodulation technology. The sinusoidal phase modulation interference signal is converted into a digital interference signal by an analog-to-digital converter after amplification and filtering, and the digital interference signal is subjected to orthogonal downmixing of first-order, second-order, and fourth-order harmonics simultaneously to obtain three pairs of orthogonal harmonic amplitude signals.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 9, 2021
    Assignee: ZHEJIANG SCI-TECH UNIVERSITY
    Inventors: Benyong Chen, Jiandong Xie, Liping Yan
  • Patent number: 11140014
    Abstract: In one aspect, an apparatus includes: a buffer to store orthogonal frequency division multiplexing (OFDM) samples of one or more OFDM symbols; a fast Fourier transform (FFT) engine coupled to the buffer, the FFT engine to receive the one or more OFDM samples from the buffer and convert each of the one or more OFDM samples into a plurality of frequency domain sub-carriers; and a timing control circuit coupled to the buffer. The timing control circuit may control timing based at least in part on a difference between a first correlation sum for a first portion of a cyclic prefix of a first one of the one or more OFDM symbols and a second correlation sum for a second portion of the cyclic prefix.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: October 5, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Alexander Kleinerman
  • Patent number: 11095376
    Abstract: Residual noise of a frequency mixer is detected. A reference clock is used to generate a first radio frequency (RF) signal, a second RF signal and a third RF signal. The first RF signal and the second RF signal serve as input to the frequency mixer. The reference clock is used to generate a third RF signal. The reference clock is also used to control timing in a detector device. A second frequency mixer mixes an output of the DUT with the third RF signal to produce an input signal for a detector device. Mixing the output of the DUT with the third RF signal cancels at least some of the phase noise within the output signal of the DUT that results from phase noise in the first RF signal and from phase noise in the second RF signal. The detector device detects residual phase noise existing within the input signal for the detector device.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Keysight Technologies, Inc.
    Inventors: Junichi Iwai, Joel . P Dunsmore, Koji Murata
  • Patent number: 10992303
    Abstract: The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: April 27, 2021
    Assignee: The Regents of the University of California
    Inventors: Hao Wang, Omeed Momeni
  • Patent number: 10958494
    Abstract: Provided are a preamble symbol generation method and receiving method, and a relevant frequency-domain symbol generation method and a relevant device, characterized in that the method comprises: generating a prefix according to a partial time-domain main body signal truncated from a time-domain main body signal; generating the hyper prefix according to the entirety or a portion of the partial time-domain main body signal; and generating time-domain symbol based on at least one of the cyclic prefix, the time-domain main body signal and the hyper prefix, the preamble symbol containing at least one of the time-domain symbols.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 23, 2021
    Inventors: Wenjun Zhang, Guanbin Xing, Ge Huang, Hongliang Xu
  • Patent number: 10721113
    Abstract: The data recovery from sub-carriers (DRSC) of a received OFDM signal, contributes a method and a circuit for utilizing parameters of OFDM sub-carriers comprised in the received OFDM signal or subspaces comprising the OFDM sub-carriers for recovering transmitted data symbols from the received OFDM signal affected by deterministic and random distortions introduced by a transmission link.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 21, 2020
    Inventor: John W Bogdan
  • Patent number: 10666491
    Abstract: In a communication device and corresponding methods to determine a phase offset imbalance, an input signal (e.g. oscillator signal) is phase shifted to generate a set of phase-shifted values. The set of phased-shifted values and the input signal are mixed to generate a respective set of mixed signals. The phase offset imbalance (e.g. phase error) is calculated based on the set of mixed signals and a gradient value.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 26, 2020
    Assignee: Apple Inc.
    Inventor: Florian Mrugalla
  • Patent number: 10659264
    Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 19, 2020
    Assignee: Cable Television Laboratories, Inc
    Inventor: Thomas H. Williams
  • Patent number: 10656993
    Abstract: In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 19, 2020
    Assignee: Unification Technologies LLC
    Inventors: Jonathan Thatcher, David Flynn, Joshua Aune, Jeremy Fillingim, Bill Inskeep, John Strasser, Kevin Vigor
  • Patent number: 10587275
    Abstract: A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Fredenburg, Muhammad Faisal
  • Patent number: 10560081
    Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Zuoguo J. Wu, Venkatraman Iyer, Gerald S. Pasdast, Todd A. Hinck, David M. Lee, Narasimha R. Lanka
  • Patent number: 10411929
    Abstract: Provided are a preamble symbol receiving method and a receiving device, characterized in that: the received preamble symbol contains a time-domain symbol which is generated from a single three-segment structure by a transmitting end according to a predefined generation rule, the single three-segment structure containing: a time-domain main body signal, a prefix generated based on the entirety or a portion of the time-domain main body signal, and a postfix or a hyper prefix generated based on the entirety or a portion of the time-domain main body signal. Therefore, using the entirety or a portion of a certain length of a time-domain main body signal as a prefix, it is possible to implement coherent detection, which solves the issues of performance degradation with non-coherent detection and differential decoding failure under complex frequency selective fading channels.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Shanghai National Engineering Research Center of Digital Television Co., Ltd.
    Inventors: Ge Huang, Hongliang Xu, Guanbin Xing, Wenjun Zhang, Yunfeng Guan, Dazhi He
  • Patent number: 10402291
    Abstract: A checking device for a data preparation unit, including a preparation element for preparing sensor data for a data transmission; and a comparator for comparing the sensor data with the prepared sensor data; a fault of the data preparation unit being detected in the event that the prepared sensor data do not match the sensor data.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: September 3, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Matthias Kalisch, Ali Abbas Husaini, Christian Pfahler
  • Patent number: 10348412
    Abstract: An apparatus comprises an optical signal generator configured to provide a first radiation comprising a first nominal carrier frequency and a second nominal carrier frequency, and provide a second radiation comprising a third nominal carrier frequency and a fourth nominal carrier frequency; an optical to electrical converter coupled to the optical signal generator and configured to: generate a first electrical current based on the first radiation and the second radiation without the second radiation passing through the Device under Test (DUT); and generate a second electrical current based on the first radiation and the second radiation after the second radiation passes through the DUT; and a data processor configured to determine a transfer function of the DUT at the third nominal carrier frequency and the fourth nominal carrier frequency based on the first electrical current and the second electrical current.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 9, 2019
    Assignee: Nanjing University of Aeronautics and Astronautics
    Inventors: Min Xue, Yuqing Heng, Shilong Pan
  • Patent number: 10326538
    Abstract: Embodiments herein describe calibrating a plurality of radio heads having a plurality of wireless antennas. In one embodiment, the plurality of radio heads communicate a calibration signal in a round robin fashion such that each of the radio heads communicates a respective calibration signal to the remaining radio heads. The received calibration signals are then used to calibrate the radio heads. In one embodiment, a controller coupled with the plurality of radio heads calibrates the radio heads. The calibrated radio heads then communicate to one or more client devices.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 18, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Mithat C. Dogan, Jiunming Huang, Brian D. Hart, Matthew A. Silverman
  • Patent number: 10284361
    Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: May 7, 2019
    Assignee: MEDIATEK INC.
    Inventors: Li-Hung Chiueh, Tse-Hsien Yeh, Chen-Yu Hsiao
  • Patent number: 10281523
    Abstract: Proposed digital on-chip jitter and phase noise measurement techniques and circuits are presented and include the use of a digitally controlled delay locked loop having very fine resolution but limited range to track the phase error between the tested device output clock and its reference clock. Some implementations employ a combination of a high-gain 1-bit phase detector, a digital accumulator and a fine digitally controlled delay element to track the accumulated phase difference between the reference clock and the device under test. Observing the accumulator output is an indication of the jitter and performing a Fast Fourier Transform of the accumulator output provides the phase noise of the device under test.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 7, 2019
    Assignee: Ciena Corporation
    Inventors: Sadok Aouini, Naim Ben-Hamida, Chris Kurowski
  • Patent number: 10237765
    Abstract: A measuring instrument for detecting a source of passive intermodulation (PIM) includes a signal source, a reference signal source, and a first transmitter module and a second transmitter module each configured to receive a signal from the signal source and a reference signal from the reference signal source and generate a tone at a first frequency and a second frequency, respectively. The measuring instrument further includes a receiver and a receiver module configured to receive the signal from the signal source and a harmonic of the test signal generated by a source of PIM to generate a sample signal at the fixed frequency of the reference signal. The receiver is configured to determine a shift in phase between the reference signal and the sample signal. The receiver determines an estimate of distance to the source of PIM using determinations of the shift in phase as the signal source is swept.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 19, 2019
    Assignee: ANRITSU COMPANY
    Inventor: Donald Anthony Bradley
  • Patent number: 10218546
    Abstract: A digital transmission system includes a transmitter configured to transmit an orthogonal frequency division multiplexing (OFDM) signal along a signal path, a receiver for receiving the OFDM signal from the transmitter and extracting OFDM symbols from the received OFDM signal, and a diagnostic unit configured to (i) demodulate the received OFDM signal to create an ideal signal, (ii) compare the received OFDM signal with the ideal signal to calculate an error signal, (iii) cross-correlate the error signal with the ideal signal, and (iv) determine a level nonlinear distortion from one of the transmitter and the signal path based on the correlation of the error signal with the ideal signal.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 26, 2019
    Assignee: Cable Television Laboratories, Inc.
    Inventor: Thomas H. Williams
  • Patent number: 10103807
    Abstract: Disclosed are embodiments of an apparatus and method relating to an optical signal to noise ratio detection circuit, adopting an optical switch, a tunable optical filter, a photoelectric conversion module, a pilot-tone modulation signal conditioning module and a control module. After the photoelectric conversion module converts a to-be-detected optical signal to a voltage signal, the pilot-tone modulation signal conditioning module respectively amplifies an AC signal and a DC signal in the voltage signal, correspondingly converts the AC signal and the DC signal to two-way digital signals, determines a modulation depth of the pilot-tone modulation signal and a modulation depth of an ASE noise according to the two-way digital signals, and calculates an optical signal to noise ratio of the optical signal.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 16, 2018
    Assignee: ZTE CORPORATION
    Inventor: Yadong Gong
  • Patent number: 10057049
    Abstract: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 21, 2018
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 9979498
    Abstract: The broadcast-signal transmitter according to one embodiment of the present invention includes: an encoder for encoding physical layer pipe (PLP) data, including a base layer and an enhancement layer of a broadcasting service, and signaling information through a SISO, and/or MIMO technique; a frame builder for generating a transmission frame, which includes a preamble having the encoded signaling information and the PLP data and an OFDM generator for modulating and transmitting a broadcast signal including the transmission frame.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 22, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Woosuk Ko, Seoyoung Back, Sangchul Moon
  • Patent number: 9971975
    Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 15, 2018
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9959096
    Abstract: A method for generating random numbers on multiprocessor systems and a multiprocessor system for generating true random numbers, using the method, generate truly random numbers with high entropy in a multiprocessor system with little additional effort to chip area and power dissipation. The method includes the steps of: measuring a phase error signal of a clock generator circuit of a first and a second processing unit respectively, forwarding the phase error signal of the respective clock generator circuit of the first and second processing unit to a true random network, combining the phase error signal of the clock generator circuit of the first processing unit and the phase error signal of the clock generator circuit of the second processing unit in the true random network to random bit streams, picking-up a random bit stream of the true random network, passing the respective random bit stream back to a random generator of the respective processing unit for outputting true random.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: May 1, 2018
    Assignee: TECHNISCHE UNIVERSITAT DRESDEN
    Inventors: Sebastian Hoeppner, Felix Neumaerker, Andreas Dixius
  • Patent number: 9909907
    Abstract: A method for correcting a timing error in a test and measurement instrument. The method includes receiving a clock signal at each of four samplers. The first clock signal is sampled at the first sampler at a first phase, the second clock signal is sampled at the second sampler at a second phase that is 90 degrees offset from the first phase, the third clock signal is sampled at the third sampler at a third phase that is 45 degrees offset from the first phase, and the fourth clock signal is sampled at the fourth sampler at a fourth phase that is 90 degrees offset from the third phase. Each of the outputs from the samplers are digitized and a timing correction is calculated based on the digitized outputs from the digitized outputs.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 6, 2018
    Assignee: Tektronix, Inc.
    Inventors: Jan P. Peeters Weem, Klaus M. Engenhardt, Laszlo J. Dobos
  • Patent number: 9876697
    Abstract: A jitter measuring setup (10) comprises a signal generator (14), a sample-and-hold circuit (15), and the inventive all stochastic jitter measuring device (1) comprising signal acquisition means (2) and calculation means (3). The input signal of the sample-and-hold circuit (15) is generated by the signal generator (14). Furthermore, the output signal of the sample-and-hold circuit (15), respectively the input signal of the measuring device (1), is comprised of a superposition of the sampled input signal of the sample-and-hold circuit (15) and a cyclostationary random process.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 23, 2018
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Thomas Schweiger
  • Patent number: 9813282
    Abstract: A sampling phase difference compensation apparatus includes a signal generator, a signal analyzer and a compensator. The signal generator generates a first signal and a second signal, and outputs the first and second signals to a first path in a first time interval and a second path in a second time interval, respectively. The signal analyzer receives a transmitted first signal from the first path and a transmitted second signal from the second path, and performs a predetermined calculation on the transmitted first and second signals to determine a phase difference relationship, which is associated with a frequency-dependent phase difference and a sampling phase difference, between the transmitted first and second signals. The transmitted first signal is associated with the first signal, and the transmitted second signal is associated with the second signal. The compensator performs a phase difference compensation according to the phase difference relationship.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 7, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Po-Hung Liu, Tzu-Yi Yang, Teng-Han Tsai, Tai-Lai Tung
  • Patent number: 9805787
    Abstract: A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyung-soo Ha
  • Patent number: 9791492
    Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 17, 2017
    Assignee: Rambus Inc.
    Inventors: Hae-Chang Lee, Jaeha Kim, Brian Liebowitz
  • Patent number: 9767921
    Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor, a register storing timing information, and an arbiter circuit configured to determine whether the resistor is available based, at least in part, on the timing information stored in the register. The timing information stored in the register of each respective chip of the plurality of chips is unique to the respective chip among the plurality of chips.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Dong Pan
  • Patent number: 9740580
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for enhancing margin in a serial data transfer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 22, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Mohammad Mobin, Bruce A. Wilson, Haitao Xia
  • Patent number: 9672089
    Abstract: A system and method for calculating a bit error rate for a mask is described. For each time during the time duration of the mask, the minimum and maximum voltages of the mask at that time are determined. The maximum bit error rate can be calculated for each time by integrating between those voltages. The maximum bit error rate for all times during the time duration of the mask can be selected as the maximum bit error rate for the mask.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: June 6, 2017
    Assignee: TEKTRONIX, INC.
    Inventor: Richard J. Poulo
  • Patent number: 9672884
    Abstract: A semiconductor device includes a division period signal generation circuit and a clock sampling circuit. The division period signal generation circuit generates a division period signal which is enabled in synchronization with a write period that is set according to a write command and latency information. The clock sampling circuit samples an internal strobe signal to output a sampling clock signal in response to the division period signal and the internal strobe signal during a sampling period. The sampling period is set to be longer than the write period.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 9571266
    Abstract: This invention relates to methods and systems for estimating skew based on, for example, the IEEE 1588 Precision Time Protocol (PTP). These methods and systems can allow the clock skew between a master clock (server) and slave clock (client) exchanging PTP messages over a packet network to be estimated. In one embodiment, the slave employs a digital phase-locked loop (DPLL) driven by timestamps supplied from a master clock. The slave is able to process the timestamp information embedded in PTP Sync and Follow_Up messages in order to lock its frequency to that of the master clock. In certain embodiments a frequency locked DPLL and a local free-running counter are used to estimate the skew of the local slave oscillator.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 14, 2017
    Assignees: British Telecommunications PLC, Khalifa University of Science Technology, and Research, Emirates Telecommunications Corporation
    Inventors: James Aweya, Ivan Boyd
  • Patent number: 9467211
    Abstract: Frequency-selective phase shifts are applied to signals transmitted from multiple transmission points involved in a coordinated (joint) transmission to a given UE. An eNodeB or other network node controlling the joint transmission artificially induces frequency selectivity between signals received by the UE in joint transmission from different transmission points, so as to ensure an even balance between constructive and destructive combination over frequency. By applying frequency-selective phase shifts (e.g., pseudo-random phase shifts) to the different transmission points that perform joint transmission, the signals from the different transmission points are forced to combine at the UE in a non-coherent manner. As a result, uncertainty in how the signals combine is drastically reduced, since it can be expected that the signals will always combine incoherently. The reduced uncertainty translates to reduced back-off offset in the link adaptation, and thus in an increased throughput.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 11, 2016
    Assignee: TELEFONATIEBOLAGET L M ERICSSON
    Inventors: David Hammarwall, Svante Bergman
  • Patent number: 9395706
    Abstract: A noise determination device is provided that determines the presence of noise on an input signal with a constant value that is output from an external device. The noise determination device includes a sampling unit that performs three samplings on the input signal, a sampling-interval setting unit that sets an interval between a first one and a second one of the samplings to have a value that is different from an integral multiple of the period of the periodic noise, and sets an interval between the second one and a third one of the samplings to be equal to or larger than an interval that is large enough to fully attenuate the periodic noise, and a noise determination unit that determines that the noise is not superimposed on the input signal only when all values acquired by the first, second, and third samplings match one another.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: July 19, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomoya Furukawa, Kengo Kato
  • Patent number: 9369269
    Abstract: Described are methods, devices and systems for communicating data measurements from a sampling device to a remote master device in a distributed power measurement system using high-speed isochronous data links. The sampling device receives a time-stamp packet from the master device over the isochronous data link, the time-stamp packet containing a sequence number of the time-stamp packet, and the sampling device starts a counter clocked by a local clock signal to determine an offset time since receipt of the time-stamp packet. The sampling device obtains power system data and generates and transmits framed output data to the remote master device over the isochronous data link. The framed output data includes the sequence number, the offset time, and a data payload that includes the power system data.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 14, 2016
    Assignee: SMART ENERGY INSTRUMENTS INC.
    Inventors: Donald Jeffrey Dionne, Jennifer Marie McCann
  • Patent number: 9329967
    Abstract: Method and related systems are described for navigating through information related to the status of one or more layers of a signal, such as a serial or parallel bus. Information may be displayed by selecting fields within a visual depicted on an oscilloscope or similar measuring instrument. By selecting particular fields, and indicators, different aspects of a layer may be analyzed without the need to have extensive knowledge of the operation of the measuring instrument.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 3, 2016
    Assignee: TEKTRONIX, INC.
    Inventors: Keith D. Rule, Walter R. Strand, Keith A. Olson, Michael J. Wadzita, Steve M. Mishler
  • Patent number: 9325554
    Abstract: The present technique relates to a receiving device, a receiving method, and a program for realizing a prompt start of data demodulation. A receiving device of one aspect of the present technique includes: a detecting unit that detects a first preamble signal from a frame signal having a frame structure that contains the first preamble signal indicating a frame partition, a second preamble signal containing control information to be used in processing a data signal, and the data signal, the second preamble signal being transmitted after the first preamble signal; an accumulating unit that accumulates the second preamble signal when the first preamble signal is detected; and a processing unit that processes the data signal based on the control information contained in the second preamble signal accumulated in the accumulating unit, the data signal being contained in the same frame as the second preamble signal accumulated in the accumulating unit.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: April 26, 2016
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokokawa, Yuken Goto, Kenichi Kobayashi
  • Patent number: 9307549
    Abstract: To support very high QAM rates, a user equipment (UE) needs extremely good signal-to-noise ratio (SNR). Using a receiver configuration that improves SNR comes at the expense of higher power consumption. However, consuming higher power to support very high QAM rates when poor channel conditions are present is a waste of power. By correlating the modulation and coding scheme used by the UE with the UE channel quality estimate, the UE can modify the receiver configuration to improve SNR only when channel conditions support very high QAM rates.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Udara Charman Fernando, Supratik Bhattacharjee, Valentin Alexandru Gheorghiu, Gene Fong