Abstract: A method includes generating automatic repeat request feedback information at a first device in response to a downlink transmission from a second device; encoding the feedback information to comprise an indication of a number of streams received in the downlink transmission and transmitting encoded feedback information to the second device. Another method includes transmitting a multi-stream downlink transmission from a first device to a second device; receiving encoded hybrid automatic repeat request feedback information from the second device; decoding the received hybrid automatic repeat request feedback information at the first device; and determining from the encoding of the hybrid automatic repeat request feedback information at least a number of streams that were actually received by the device from the downlink transmission. A wireless link between the devices can be a 2×2 MIMO link.

Abstract: A multiple input, multiple output (MIMO) transceiver includes a reconfigurable pooled digital filter. A processor sets parameters of the filter to minimize the number of instructions per second and the amount of power required by the filter to perform, while matching the filter to at least one of: a transmitter filter and a receiver filter. The processor uses an algorithm or a lookup table stored in memory to select the combination of filter parameters. The parameters may be selected from at least one of: a number of taps, a filter length, a word length, a coefficient quantization, a sampling rate, bits per sample, a sampling bit, a tap delay and a coefficient length. After selecting a combination of filter parameters, the processor sends a control signal to the adaptive filter. The pooled adaptive filter reconfigures itself in accordance with the selected filter parameters.

Abstract: An orthogonal frequency division multiplexing (OFDM) equalizer includes a memory that stores OFDM frame information, a partial sum calculator configured to calculate a partial sum of a data cell corresponding to an OFDM reception signal based on a current pilot cell and a fixing coefficient corresponding to the current pilot cell, an adapting coefficient calculator configured to calculate a channel response of the data cell and calculate an adapting coefficient based on the calculated channel response and an interpolated channel response, an interpolated channel response calculator configured to calculate the interpolated channel response based on the partial sum and the adapting coefficient, and a channel compensation unit configured to output a corrected OFDM reception signal based on the fast Fourier transformed OFDM reception signal and the interpolated channel response. Related receivers and channel equalization methods are also disclosed.

Abstract: A communication system receives a modulated signal that carries encoded communication data. An adaptive filter has a plurality of adaptive filter taps and weighted coefficients and a variable delay circuit operative before the adaptive filter taps for separating the spacing of multipath introduced by adaptive filter and producing a filtered output signal with improved multipath performance. A demodulator and decoder receive the filtered output signal from the adaptive filter and demodulate and decode the signal to obtain the communications data.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has an input, a plurality of non-adaptive and adaptive filter taps with weighted coefficients, and an output. The received signal is passed through the adaptive filter and around adaptive filter and a switch selects which signal to pass to demodulator based on measured output power of the adaptive filter and of the original received signal. A demodulator and decoder receive the filtered output signal and demodulate and decode the signal to obtain the communications data.

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

Abstract: Methods and systems for processing signals in a receiver are disclosed herein and may include updating a plurality of filter taps utilizing at least one channel response vector and at least one correlation vector, for a plurality of received clusters, based on initialized values related to the at least one channel response vector and the at least one correlation vector. At least a portion of the received signal clusters may be filtered utilizing at least a portion of the updated plurality of filter taps. The update may be repeated whenever a specified signal-to-noise ratio (SNR) for the received signal clusters is reached. The initialized values may be updated during a plurality of iterations, and the update may be repeated whenever a specified number of the plurality of iterations is reached.

Abstract: A method for frequency domain equalization of a cyclic CPM signal received via a channel is disclosed. In one aspect, the method includes representing the received cyclic CPM signal as a matrix model comprising a channel matrix representing influence of the channel, separate from a Laurent pulse matrix and a pseudocoefficient matrix respectively representing Laurent pulses and pseudocoefficients determined by Laurent decomposition of the received cyclic CPM signal. The method may further include applying a channel equalizer on the separate channel matrix and after the equalization. It may further include demodulating the received cyclic CPM signal by the matrix model, the demodulation exploiting known correlation properties of the Laurent pulses and the pseudocoefficients.

Abstract: A direct determination equalizer system (“DDES”) for compensating for the deterministic effects of a transmission channel and a data source is disclosed. The DDES may include an equalizer having equalizer-tap coefficients, a cross-correlator configured to receive the first sampled signal and an ideal signal and in response produce a cross-correlated signal, and a processor in signal communication with the equalizer and the cross-correlator. The equalizer is configured to receive a first sampled signal and in response produce an equalized output data signal sequence and the processor is configured to determine the equalizer-tap coefficients from the cross-correlated signal.

Abstract: A pre-emphasis circuit to emphasize edges of transmission data is controlled in correspondence with the result of analysis of the transmission data.

Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Abstract: For a data group composed of pieces of data each indicating channel characteristics of a scattered pilot signal position whose phase is adjusted by dividing scattered pilot signals included in an OFDM signal by a scattered pilot signal at the time of transmission, a carrier extension circuit 341 inserts data having a same value as a value of data of a lower end into an outside of the lower end of a band, and inserts data having a same value as a value of data of an upper end into an outside of the upper end of the band. On the data group composed of 2N pieces of data including the data inserted by the carrier extension circuit 341, IFFT processing by an IFFT circuit 342, noise removal processing by a noise removal filter 343, and FFT processing by a FFT circuit 344 are performed. The data inserted by the carrier extension circuit 341 is removed from the data group outputted from the FFT circuit 344, and the data group after the data removal is used for interpolation in a symbol direction.

Abstract: Embodiments of a multicarrier receiver and method for generating soft bits in a multiple-input multiple-output system are generally described herein. In some embodiments, operational parameters for an equalizer and a soft-bit demapper in a multicarrier receiver are determined. Other embodiments may be described and claimed.

Abstract: A transmitter includes a first amplifier to amplify an in-phase oscillator signal to produce an in-phase mixing signal and a second amplifier to amplify a quadrature-phase oscillator signal to produce a quadrature-phase mixing signal. A first mixer mixes the in-phase mixing signal with a first information signal to produce a first output signal. A second mixer mixes the quadrature-phase mixing signal with a second information signal to produce a second output signal. The first output signal and an inverted second output signal are summed to produce a transmitter output signal that includes an image signal caused by a phase imbalance between the in-phase and quadrature-phase mixing signals. An image monitor monitors the image signal and reduces or eliminates the phase imbalance by independently adjusting a phase of the in-phase mixing signal and/or a phase of the quadrature-phase mixing signal. Consequently, a power of the image signal is reduced or eliminated.

Abstract: A technique for enhanced reconditioning equalizer filter chain for multi-carrier signals is described. The input to a transmitter chain is modified by an enhanced reconditioning equalizer filter chain, prior to being applied to the transmitter. The enhanced reconditioning equalizer filter chain modifies and smoothen the amplitude of the signal. The modified and smoothen signal has its picks reduced which results to lower Crest Factor. The input to the enhanced reconditioning equalizer filter chain could be a baseband, an intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal it needs to be down converted to baseband before applied to enhanced reconditioning equalizer filter chain. The enhanced reconditioning equalizer filter chain could be implemented in digital or analog domain.

Abstract: In accordance with a particular embodiment of the present invention, a method is offered that includes providing a filter and an adaptive control element that is operable to communicate with the filter. The method also includes measuring, over a period, a data correlation matrix and an uncompensated error correlation vector using first and second low pass filters. In addition, the method includes implementing a data-pattern compensation matrix online, whereby the data-pattern compensation matrix is obtained online dynamically from the data correlation matrix.

Abstract: A method having enhanced decoding operations associated with receiving multiple Radio Frequency (RF) Burst(s) is provided. Multiple RF burst(s) are received where the multiple RF Burst(s) include first RF bursts and second RF Burst(s). The second RF bursts may be transmitted in parallel or in response to a decoding error associated with the first RF burst. The received RF burst(s) are equalized and deinterleaved to yield extracted soft samples. Then the first estimated bit sequences and second estimated bit sequences are decoded from the extracted soft samples. A set of possible bit sequences may then be pruned based on based on combined knowledge of the first estimated bit sequence and the second estimated bit sequences. This pruned set may be compared using a sequence detector and the combined first estimated bit sequences and second estimated bit sequences to select a decoded bit sequence.

Abstract: Methods, circuits, and systems for increasing bandwidth and/or transition separation in data communications and data storage in the presence of potential intersymbol interference (ISI). The method includes writing L bits of serial data per data transition period to a channel, reading data units from the channel M times per data transition period (M?L), and determining a most likely value for a K*2(L-M)-bit binary sequence of the data. The circuit generally receives m-ary symbols, converts them to n-ary data, and includes detector logic that (i) calculates a most likely n-ary data sequence from L-unit blocks thereof, and (ii) disallows subsequent L-unit blocks in which there is a transition and any of the first x units do not equal any of the last y units in an immediately preceding block (where x+y=L). Generally, successive transitions in the serial data are at least L/M bit lengths apart.

Abstract: A method and apparatus for receiving data in a communication system is disclosed. Receiving a first signal from a transmitter, a first canceller cancels from the received first signal a second signal desired to be received from the transmitter. A second canceller detects and cancels an interference signal from the second signal-canceled first signal. A calculator calculates a Log Likelihood Ratio (LLR) of the interference signal-canceled first signal.

Abstract: In accordance with a particular embodiment of the present invention, a method is offered that includes characterizing a data correlation matrix for an idle pattern offline in a filter environment and, further, using a static adaptive control scheme with a static value of a data-pattern compensation matrix to achieve a compensated adaptive equalizer control. In more specific embodiments, the adaptive control scheme is used with a ZF adaptation scheme in conjunction with a constant adaptation matrix. In other embodiments, the adaptive control scheme is used with a fast steepest-descent method using a variable adaptation matrix. In still other embodiments, the adaptive control scheme is used with a constant adaptation matrix, whereby a value of is statically calculated. If the adaptive control scheme is used with a decoupling matrix, a value of is statically calculated. An inverter is used between the data correlation matrix and the data-pattern compensation matrix.

Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

Abstract: Disclosed is a radio transmission device for lightening the waveform distortion of a received signal in a single-carrier transmission irrespective of a fading state. In this device, an FFT unit (103) converts a modulation signal outputted from a modulation unit (102), into a signal of a frequency range, and a repetition unit (104) repeats the frequency range signal outputted from the FFT unit (103), and arranges a plurality of frequency range signals adjacent to each other on a frequency axis. A tooth-shaped waveform forming unit (105) shapes the waveform of the frequency range signals outputted from the repetition unit (104), into a tooth-shaped waveform, and an IFFT unit (106) converts the frequency range signal outputted from the tooth-shaped waveform forming unit (105), into a signal of a time range.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: A baseband processing module of a Radio Frequency receiver produces time domain equalizer coefficients and calculates a power threshold based upon a total power of a plurality of taps of the time domain equalizer coefficients. The baseband processing module then performs a plurality of iterations, during each of which it identifies at least one minimum power tap and determines a total power figure based upon zeroing the at least one minimum power tap. When the total power figure compares favorably to the power threshold, the baseband processing module modifies the plurality of taps by zeroing the at least one minimum power tap and continuing iterating. When the total power figure compares unfavorably to the power threshold, the baseband processing module ceases iterating without modifying the plurality of taps by zeroing the at least one minimum power tap and then produces modified time domain equalizer coefficients.

Abstract: A partial response signaling system includes a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; and a receiver circuit configured to recover an output data from the partial response signal and to generate the control signal based on the partial response signal and an expected signal to output the control signal to the transmitter circuit.

Abstract: A digital radio frequency memory (DFRM) which converts an incoming analog radio frequency signal to a fourteen bit digital signal allowing for digital signal processing and then retransmitted as an analog RF signal. The DFRM provides a time delay for RF signals by storing the signal. The DFRM also changes the signal frequency in the range of plus or minus 100,000 KHz which places a doppler on the signal. The signal phase is changed in a range of 0 to 359 degrees by the DFRM.

Abstract: Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.

Abstract: An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Abstract: A method for processing a sampled signal includes receiving a signal from a channel at a channel speed and providing error adjustment to the signal. The method includes sampling the signal at a speed less than the channel speed to yield a sampled signal and determining an error associated with the signal. The method also includes determining compensation information for the error adjustment. The compensation information is based on the error, and the compensation information is determined at a compensation speed less than the channel speed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the alternating (AC) voltage swing of a CTE to reference voltage.

Abstract: A channel equalizer for use in a receiving system includes an overlap unit, a first estimator, an interpolator, and a second estimator. The overlap unit overlaps a group of normal data packets including a head, a body, and a tail, and a known data region is periodically repeated in the body. The first estimator estimates CIRs of the known data regions according to a first algorithm, and the interpolator estimates CIRs of normal data regions in the body by interpolating the estimated CIRs of the known data regions. The second estimator estimates CIRs of normal data regions in the head and tail according to a second algorithm different from the first algorithm. A calculator calculates equalization coefficients based on the estimated CIRs and a compensator multiplies the overlapped data with the coefficients. A save unit saves the compensated data.

Abstract: An equalizing apparatus for an orthogonal frequency division multiplexing (OFDM) wireless communication receiving system includes a channel estimation block, a first equalizer, and an error compensation block. The channel estimation block performs channel estimation by extracting a pilot signal from a signal supplied to the first equalizer. The first equalizer performs first channel equalization based on the channel estimation from the channel estimation block. The error compensation block outputs an error compensation value of the first equalizer, based on data signals from the first equalizer. The error compensation value may be used by the first equalizer and/or a second equalizer. Related methods and computer program products are also described.

Abstract: A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.

Abstract: A method of synchronizing a feedforward filter that receives a signal resulting from the transmission of a series of symbols through a channel, wherein the series of symbols includes a predetermined sequence of symbols includes the step of developing a plurality of samples from the received symbols, wherein a sequence of samples corresponds to the predetermined sequence of symbols. The method may further include the steps of estimating a channel impulse response from the plurality of samples, wherein the channel impulse response estimate is represented by a plurality of correlation values, identifying a maximum correlation value from the plurality of correlation values, defining a window relative to the maximum correlation value, calculating a characteristic of the correlation values within the window, and synchronizing the feedforward filter in accordance with the characteristic.

Abstract: A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal.

Abstract: A circuit and method for suppressing interference components in a received signal are provided. The circuit includes an adaptive filter configured to process a first quantity of digital signal samples per unit time when the adaptive filter is operating in a first mode, and a second quantity of digital signal samples per unit time when operating in a second mode, wherein the first quantity is less than the second quantity. The method includes implementing an adaptive filter configured to operate in an adaptive mode and in a second mode having a reduced adaptability compared to the adaptive mode; operating the adaptive filter in the adaptive mode to process a first quantity of digital signal samples per unit time; and operating the adaptive filter in the second mode to process a second quantity of digital signal samples per unit time; wherein the first quantity is less than the second quantity.

Abstract: Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used.

Abstract: A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.

Abstract: A technique for enhanced reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by an enhanced reconditioning equalizer filter, prior to being applied to the transmitter. The enhanced reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the enhanced reconditioning equalizer filter could be a baseband, an intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal it needs to be down converted to baseband before applied to enhanced reconditioning equalizer filter. The enhanced reconditioning equalizer filter could be implemented in digital or analog domain.

Abstract: A phase detector includes a decimator to decimate a digitized in-phase signal and a digitized quadrature signal to N times a symbol rate, where N is an integer greater than one. A burst detector to detect bursts in an output of the decimator. A carrier offset block to determine an offset angle based on an output of the burst detector. A rotator to generate a rotated signal by rotating the output of the decimator based on the offset angle determined by the carrier offset block. An equalizer to perform coherent demodulation of the rotated signal.

Abstract: A method to reduce peak power consumption during adaptation for an integrated circuit (IC) with multiple serial link transceivers including the steps of (A) inactivating equalizer adaptation loops until a triggering event occurs, (B) when the triggering event occurs, determining whether the triggering event is a minor change or a major change, (C) when the triggering event is a minor change, spreading out activation of adaptation loops in time, and (D) when the triggering event is a major change, simultaneously activating all adaptation loops.

Abstract: A method and system of estimating frequency offset at a subscriber station is disclosed. The method includes the subscriber station receiving a composite signal, in which the composite signal includes multi-carrier signals transmitted from a plurality of base stations. The subscriber station selects a subset of the plurality of base stations. The subscriber station selects at least one pair of multi-carrier symbols of the composite signal, wherein each of the at least one pair of multi-carrier symbols include a plurality of pilot sub-carriers. The subscriber station selects a subset of the plurality of pilot sub-carriers of the at least one pair of multi-carrier symbols based on transmit pilot symbols of the pilot sub-carriers of the multi-carrier signals transmitted by the subset of the plurality of base stations.

Abstract: An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.

Abstract: A receiver module includes an input that receives a data message from a wireless communication channel. The data message has a plurality of training fields and data. A channel estimator module recursively estimates a matrix H that represents the channel based on the plurality of training fields. The recursive estimation is performed as the plurality of training fields are being received. An equalizer module applies coefficients to the data based on the matrix H.

Abstract: In one embodiment, a receiver has an equalizer, a tap-averaging block, a delay buffer, and a filter. The equalizer receives an input signal from upstream processing and generates sets of filter coefficients. Each set of filter coefficients is adaptively generated by 1) filtering the received signal to generate an equalized signal, 2) calculating an error of the equalized signal, and 3) generating a new set of coefficients based on the error of the equalized signal. The sets of filter coefficients are output to the tap-averaging block, which averages groups of the sets of filter coefficients to generate sets of averaged filter coefficients, where each averaged set is output to the filter. The filter receives a time-delayed version of the input signal from the delay buffer and applies the current set of averaged filter coefficients to the time-delayed signal. The filtered signal is then output to downstream processing.

Abstract: Adaptive generalized decision feedback equalization (GDFE) allows variations in one or more channels and noise of a multi-line/multi-channel communication system to be tracked. Such tracking can be used in vector upstream (one-sided) situations in communication systems such as ADSL and VDSL, among others. The GDFE may be separated into adaptive and static portions and/or components. Either a feedforward section or a feedback section (or both) can be separated to create a static component and an adaptive component. The adaptive components adjust to the instantaneous channel and noise changes (for example, using the instantaneous errors and simple LMS algorithms). When the channel and noise do not exhibit any time-variation, the adaptive filters can zero themselves.

Abstract: A fast adaptive time domain equalizer for a Time Reversal-Space Time Block Code (TR-STBC) system is provided. More particularly, a reduced-complexity hybrid Decision Feedback Equalizer (DFE) configuration for the TR-STBC system, and a Least Mean Square (LMS), a normalized LMS (NLMS), and a Recursive Least Square (RLS)-based adaptive algorithms for the hybrid DFE are provided.

Abstract: Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

Abstract: A device for scaling and quantization of digital soft output values (sk) from an equalizer has a control loop for controlling a statistical parameter (?) for the scaled and quantized soft output values (sD,k), which contains a calculation unit (4) for calculation of the statistical parameter (?), and a control unit (5) for calculation of a scaling factor (c) for scaling the soft output values (sk) from the equalizer on the basis of the statistical parameter (?).

Abstract: Methods and systems for reconfigurable soft-output bit demapping, reconfigurable for different modes of operation (i.e., different transmitter/receiver configurations) and for different modulation schemes are provided. In an embodiment, a reconfigurable soft-output bit demapping system includes a mode/modulation independent equalizer, a plurality of mode/modulation independent soft-slicers coupled to the outputs of the equalizer, a plurality of mode/modulation independent post-scalers coupled to the outputs of the soft-slicers, and a mode-dependent coefficient calculator. The coefficient calculator generates parameters for configuring the equalizer, the soft-slicers, and the post-scalers according to the used mode of operation and modulation scheme.