Abstract: A receiving link device includes a receiver (RX) to receive a data signal from a transmitting link device, the receiver including an equalizer to detect RX tap values and a processing device coupled to the receiver, the processing device to perform operations including: programming the receiver with information related to target RX tap values that are associated RX pre-cursors or RX post-cursors; detecting, using the equalizer, that an RX pre-cursor value is greater or less than a target RX tap value; generating, based on the detecting, a tap message including an up or a down command to decrease or increase a corresponding transmitter (TX) pre-cursor value of the transmitting link device; and causing the tap message to be provided to a local transmitter to be transmitted to a remote receiver of the transmitting link device, which causes the transmitting link device to adjust the corresponding TX pre-cursor value.

Abstract: A receiver includes a decision feed forward equalization (DFFE) system coupled to a partial response (PR) system. The partial response system generates, based on a digital signal that includes pre-cursor intersymbol interference (ISI) and post-cursor ISI introduced by a communication channel, a detected signal including a set of detected symbol values. The detected signal is equalized to a partial response. The DFFE system includes a PR inverter to generate a set of estimated transmitted symbol values based on the set of detected symbol values and DFFE circuitry to cancel the pre-cursor ISI and the post-cursor ISI from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

Abstract: An audio signal processor includes a digital filter block configured to receive an audio signal and output a first filtered audio signal, and a phase linearization block configured to receive the first filtered audio signal and output a second filtered audio signal with a more linear phase.

Abstract: A machine learning (ML) agent operates at a transmitter to optimize signals transmitted across a communications channel. A physical signal modifier modifies a physical layer signal prior to transmission as a function of a set of signal modification parameters to produce a modified physical layer signal. The ML agent parses a feedback signal from a receiver across the communications channel, and determines a present tuning status as a function of the signal modification parameters and the feedback signal. The ML agent generates subsequent signal modification parameters based on the present tuning status and a set of stored tuning statuses, thereby updating the physical signal modifier to generate a subsequent modified physical layer signal to be transmitted across the communications channel.

Abstract: A hybrid delta modulator that can be used as a variable threshold neuron in a neural network is described. The hybrid delta modulator exhibits a memory of the prior state of the modulator, similar to a delta modulator, and receives a sum-of-products signal from a weighting circuit and generates a quantized output stream that represents the sum-of-products signal, potentially including an activation function and offset. With appropriately selected components, the hybrid delta modulator separates the integral function of the feedback from the gain function. Further, the gain can be selected, and the characteristic of the output pattern can be tailored to include an arbitrary combination of the input and the rate of change of the input. The use of a hybrid delta modulator of the present approach provides a simpler solution and better performance than many prior art neurons.

Abstract: An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

Abstract: Certain aspects of the present disclosure provide techniques for encoding image data for one or more images. In one embodiment, a method includes the steps of downscaling the one or more images, and encoding the one or more downscaled images using an image codec. Another embodiment concerns a computer-implemented method of decoding encoded image data, and a computer-implemented method of encoding and decoding image data.

Abstract: Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Abstract: A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.

Abstract: A signal receiving apparatus includes at least one signal separating apparatus that separates a specific signal from a plurality of received signals. Each of the at least one signal separating apparatus includes a spatial filtering unit that separates at least one equalized signal and a decision signal outputting unit that generates a first decision signal by deciding the equalized signal and outputs the generated first decision signal. The spatial filtering unit separates the at least one equalized signal by multiplying at least the plurality of received signals among the plurality of received signals and either the first decision signal output from the decision signal outputting unit or a second decision signal output from another signal separating apparatus by predetermined weighting coefficients.

Abstract: A method for equalizer correction in a communication network includes (a) obtaining raw equalizer coefficients in a frequency domain, (b) removing time delay from the raw equalizer coefficients to generate corrected equalizer coefficients in a time domain such that a direct current (DC) corrected equalizer coefficient of the corrected equalizer coefficients has a phase of zero, and (c) converting the corrected equalizer coefficients from the time domain to the frequency domain.

Abstract: This document discloses a solution for detecting interference in a radio access network. According to an aspect, a method includes as performed by a network node of the radio access network: acquiring a first equalized signal representing a signal received by a first radio head serving a terminal device, the first equalized signal including a signal received by the first radio head from the terminal device; acquiring a second equalized signal representing a signal received by a second radio head not serving the terminal device, wherein the second radio head is spatially distant from the first radio head; cross-correlating the first equalized signal with the second equalized signal and determining, on the basis of said cross-correlating, whether or not the second equalized signal also includes a signal received from the terminal device; and as a result of the second equalized signal being determined to include the signal received from the terminal device, causing execution of an interference management action.

Abstract: The present disclosure relates to a method for estimation of an interfering signal of a signal received by a receiving system and to a method for attenuation of an interfering signal contained in a received signal, and a receiving system.

Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N?1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

Abstract: Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp1 of a first postcursor tap of a first FFE and a coefficient h1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h1 and hp1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

Abstract: An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

Abstract: Techniques are provided for automatic gain control processing to reduce adverse effects associated with clipped samples resulting from conversion of analog signals to digital signals. A methodology according to an embodiment includes identifying a clipped sample of the digital signal, for example by comparison of the digitized sample values to a threshold value associated with a full scale value of the converter. The method also includes applying a window function to portions of the digital signal. The window function is configured to attenuate samples of the digital signal within a region centered on the identified clipped sample. A Hilbert finite impulse response (FIR) filter may be applied to the digital signal prior to applying the window function. Parameters of the window function are selected based on frequency response characteristics of the FIR filter and on signal to noise ratio requirements of an application that receives the windowed digital signal.

Abstract: A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.

Abstract: This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

Abstract: A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Abstract: A method and a system for automatically adjusting intensity of a signal outputted by an HDMI transmitter are provided. With the method, a length of an HDMI transmission line between the HDMI transmitter and an HDMI receiver is determined. A swing amplitude and a pre-emphasis intensity of the signal outputted by the HDMI transmitter are determined based on the length of the HDMI transmission line and a frequency of the signal outputted by the HDMI transmitter. An HDMI output drive circuit is configured based on the swing amplitude and the pre-emphasis intensity.

Abstract: An apparatus, method, and non-transitory computer readable medium that can mitigate wireless channel impairments in seismic data transmission using deep neural networks is disclosed. The apparatus includes a receiving circuitry to receive seismic data and a processing circuitry. The processing circuitry is configured to apply a blind system identification process to the seismic data to estimate a channel impulse response of the seismic data, apply an optimum equalization process to obtain estimated seismic data based on the channel impulse response, process the estimated seismic data to generate processed seismic data, classify the processed seismic data into a first group of seismic data each of which has a signal-to-noise ratio (SNR) less than an SNR threshold and a second group of seismic data each of which has an SNR no less than the SNR threshold, and enhance the SNR of each of the first group of seismic signals.

Abstract: A system and method for orthogonal time frequency space communication and waveform generation. The method includes receiving a plurality of information symbols and encoding an N×M array containing the plurality of information symbols into a two-dimensional array of modulation symbols by spreading each of the plurality of information symbols with respect to both time and frequency. The two-dimensional array of modulation symbols is then transmitted using M mutually orthogonal waveforms included within M frequency sub-bands.

Abstract: One illustrative equalizer converts a receive signal into a sequence of symbol decisions using: a linear filter that filters the receive signal as part of deriving a first sequence of equalized signal samples; a first decision element that derives a tentative sequence of symbol decisions from the first sequence of equalized signal samples; a nonlinear filter that, when enabled, applies nonlinear compensation to the linearly filtered receive signal as part of deriving a second sequence of equalized signal samples; a second decision element that, when enabled, derives replacement symbol decisions from the second sequence of equalized signal samples; a subtraction element that calculates an equalization error for each symbol decision in the tentative sequence; and a controller that selectively enables the nonlinear filter and the second decision element to obtain a replacement symbol decision for each symbol decision in the tentative sequence having an equalization error greater than a predetermined value.

Abstract: Embodiments are disclosed for computing an eye diagram based on input pulse responses. An example method includes receiving a set of input pulse responses in one or more unit interval (UI) spaced samples. The set of input pulse responses is generated based on measuring a signal histogram of a receiver of a pulse amplitude modulation analog signal. The method further includes receiving a set of voltage range constraints and generating a matrix based at least in part on an element-wise trigonometric-based operation performed on one or more products of each element of the set of input pulse responses and the set of voltage range constraints. The method further includes generating an eye diagram probability density function based on the matrix and computing an eye diagram based on the eye diagram probability density function, the voltage range constraints, and time data associated with the one or more unit interval spaced samples.

Abstract: [Problem] Provided is a demodulation circuit, a processing method, and a processing device which are capable of improving robustness in demodulating a broadcast signal. [Solution] Provided is a demodulation circuit including a demodulation unit that demodulates a broadcast signal received by a reception circuit that receives the broadcast signal, an error correction processing unit that performs an error correction on a first packet obtained by demodulation, and a packet processing unit that extracts a second packet from the first packet on which an error correction has been performed, in which when an error correction is unsuccessfully performed on the first packet that was to be processed immediately before, the packet processing unit extracts the second packet from the first packet to be processed based on pointer information included in the first packet to be processed.

Abstract: The invention discloses a data processing method and an intelligent terminal based on an orthogonal frequency division multiplexing (OFDM) system. The method comprises: a communication base station inserting equally spaced frequency domain reference signals to frequency domain data; obtaining frequency domain signals by equivalently transforming the frequency domain data being inserted with the frequency domain reference signals, wherein the frequency domain signals comprise the frequency domain reference signals superimposed with the frequency domain data; obtaining time domain signals by performing inverse Fast Fourier Transform (IFFT) on the frequency domain signals, wherein the time domain signals comprise time domain reference signals superimposed with the time domain data; and transmitting the time domain signals to the intelligent terminal.

Abstract: Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.

Abstract: Systems, methods, and computer-readable storage media for signaling filters for reference picture resampling are described. One example involves obtaining an encoded video bitstream associated with the video data, identifying a current picture and at least one reference picture from the encoded video bitstream, and identifying signaling data from the encoded video bitstream for the video data, the signaling data including a partial set of coefficient data for at least one filter. A complete set of coefficients (e.g., filter coefficients) is derived for the at least one filter from the partial set of coefficient data and characteristics of the at least one filter, and the current picture is processed using the complete set of coefficients for the at least one filter.

Abstract: An illustrative digital communications method includes: filtering a receive signal to provide a filtered receive signal; deriving symbol decisions from the filtered receive signal; detecting a baud rate of the receive signal; adapting one or more coefficients of the filter if the baud rate is above a predetermined rate; and inhibiting coefficient adaptation if the baud rate is below the predetermined rate. The method may be implemented in a receiver having: a filter to convert a receive signal into a filtered receive signal; a decision element coupled to the filter to derive symbol decisions; a baud rate detector to detect a baud rate of the receive signal; and an adaptation module to adapt one or more coefficients of the filter if the baud rate is above a predetermined rate, the baud rate detector inhibiting adaptation if the baud rate is below the predetermined rate.

Abstract: A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

Abstract: A signal generator outputs a reference signal corresponding to at least one wireless signal according to the predefined signal encoding to a channel emulator processor. The channel emulator processor is programmed to use at least one synthesized channel parameter and the reference signal to produce and store a perturbed signal as data for training machine learning and artificial intelligence systems. The synthesized channel parameter is synthesized using a channel synthesizer processor programmed to: ingest map elevation data, reference a transmitter and a receiver to the map elevation data, and perform ray tracing of a representative signal between the transmitter and the receiver, while applying at least one predetermined perturbation property to synthesize at least one channel parameter.

Abstract: An equalization method has been developed for low latency, low bandwidth wireless communication channel environments. With this method, an exact copy, nearly exact copy, or some facsimile of a message (or associated information), which was transmitted via a low latency, low bandwidth wireless communication channel, is also sent via a backend communication channel such as a fiber optic network. Equalization is generally performed by comparing the originally received message to the copy sent via the backend channel. The original message can incorporate an added channel delay to compensate for the time delay between the primary wireless channel and the backend channel.

Abstract: Methods and apparatus in a multi-carrier cellular wireless network with random access improve receiving reliability and reduce interference of uplink orthogonal frequency division multiplex (OFDM) signals of a random access, while improving the detection performance of a base station receiver by employing specifically configured ranging signals. The OFDM signals of the random access are transmitted in a at least one block indicated in configuration information. Uplink signals are transmitted with a timing adjusted based on a received time advance and a power adjusted based on a received power adjustment.

Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.

Abstract: Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

Abstract: The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include determining, using a decision feedback equalization (“DFE”) training block, a voltage value for one or more resistor values. Embodiments may further include determining, using the DFE training block, a voltage value for one or more capacitor values and identifying a voltage difference between the voltage value for one or more resistor values and the voltage value for one or more capacitor values. Embodiments may further include iteratively performing the determining of the voltage value and identifying of the voltage difference for each of the plurality of capacitor values until the voltage difference is at one or more minimum values to generate one or more optimal resistor and capacitor coefficients for a continuous time linear equalization filter.

Abstract: In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

Abstract: A semiconductor apparatus may include a first semiconductor apparatus configured to transmit a first input signal as first data in synchronization with a first edge of a first clock signal having a first frequency. The semiconductor apparatus may also include a second semiconductor apparatus including: a first storage unit, configured to receive the first data as a set signal and output a second input signal as an internal signal in synchronization with a first edge of a second clock signal having a second frequency; and a second storage unit, configured to output the internal signal as second data in synchronization with a second edge of the second clock signal.

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Abstract: Selection of equalization coefficients to configure a communications link between a receiver in a host system and a transmitter in an optical or electrical communication module is performed by a management entity with access to management registers in the receiver and transmitter. Continuous modification of the selected equalization coefficients is enabled on the communications link after the communications link is established to handle varying operating conditions such as temperature and humidity.

Abstract: An example method may include a processing system of a channel sounding receiver having a processor receiving from a base station, at a location, a channel sounding waveform via a plurality of carriers, sampling the channel sounding waveform via the plurality of carriers to generate a plurality of per-carrier time domain sample sets, and processing the plurality of per-carrier time domain sample sets via a plurality of discrete Fourier transform modules to provide a plurality of per-carrier frequency domain sample sets. The method may further include the processing system aligning the plurality of per-carrier frequency domain sample sets in gain and phase to provide a combined frequency domain sample set and measuring a channel property at the location based upon the combined frequency domain sample set.

Abstract: An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.