Abstract: A wireless communications relay includes a first radio and a second radio operating over adjacent channels. A baseband signal to be transmitted (the “transmit signal”) from the first radio is split along two paths. A first path is delayed by a delay element and the second path is provided as input to a channel model configured to implement a transfer function approximating an echo channel of the local RF environment. The channel model outputs a baseband approximation of echo channel effects of the transmit signal, after which an RF chain modulates the echo channel approximation to the RF domain. This RF echo channel approximation is thereafter filtered by an RF band pass filter turned to an operating channel of the second radio. The filtered signal is thereafter combined with received signal to compensate for self-interference.

Abstract: The present disclosure provides a data receiving circuit, a data receiving system, and a memory device. The data receiving circuit includes: a receiving module, configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module, connected to a feedback node of the receiving module, and configured to perform a decision feedback equalization on the receiving module on the basis of a feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained on the basis of data received previously, and an adjustment capability of the decision feedback equalization module to the first output signal and the second output signal is adjustable.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A wideband transmission circuit is provided. The wideband transmission circuit includes a power amplifier circuit(s) and an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to generate a modulated voltage based on a modulated target voltage. The power amplifier circuit(s) amplifies a radio frequency (RF) signal(s) based on the modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit. In embodiments disclosed herein, the ETIC is configured to cause the modulated target voltage to be equalized by a real equalization filter to thereby compensate for a complex voltage distortion filter resulting from a coupling between the power amplifier circuit(s) and the RF front-end circuit. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the complex voltage distortion filter to thereby improve efficiency and linearity of the power amplifier circuit(s).

Abstract: The symbol determination device generates the plurality of estimated reception symbol sequences on the basis of the estimated transfer function of the transmission line represented by the tap gain value applied to each tap of the nonlinear filter including the plurality of taps and the plurality of candidate symbol sequences, determines the transmission symbol by the maximum likelihood sequence estimation on the basis of the determination target reception symbol sequence obtained from the reception signal sequence and each of the plurality of estimated reception symbol sequences, identifies the estimated transmission symbol corresponding to the determination target reception symbol sequence, calculates the new tap gain values on the basis of the determination target reception symbol sequence and the identified estimated transmission symbol sequence, updates the estimated transfer function by applying the calculated tap gain values to the taps of the transmission line estimation unit, and selects the tap to be

Abstract: A method and timing recovery circuit for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation applies a filter pattern decoder to detected symbol sequence at more than two adjacent data symbols, particularly to the detected symbol patterns of four adjacent samples ?(k?2), ?(k?1), ?(k), ?(k+1), and calculates an estimated phase error e(k).

Abstract: An electronic device is provided. The electronic device includes an antenna and an ultra wide band (UWB) communication circuit connected with the antenna. The UWB communication circuit is configured to filter a positioning signal received from the antenna into a specified band to be converted into a digital signal, generate a UWB packet including a first field associated with synchronization and a second field associated with security, obtain a first channel impulse response corresponding to the first field and a second channel impulse response corresponding to the second field, when the UWB packet is valid based on the second field, obtain a third channel impulse response, when there is a correlation between the first channel impulse response and the second channel impulse response, and measure a distance to the external electronic device based on the third channel impulse response.

Abstract: An oscilloscope includes a memory that stores instructions; and a processor that executes the instructions. When executed by the processor, the instructions cause the oscilloscope to obtain a measurement of a first radio frequency signal; split a first spectrum based on the first radio frequency signal into a first low-frequency band and a first high-frequency band; perform a first Fourier transform to compute a first new spectrum based on the first spectrum; compute a first waveform of the first new spectrum with noise of the oscilloscope reduced by performing a first inverse Fourier transform based on the first new spectrum; and combine the first new spectrum with noise of the oscilloscope reduced with the first low-frequency band.

Abstract: Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.

Abstract: A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

Abstract: A feed-forward equalizer includes a shift register, a look-up table circuit, a selection circuit and an output terminal. The shift register temporarily stores and shifts input data based on a clock signal to obtain multiple shifted input data. The look-up table circuit has multiple processed signals. The processed signals are obtained by logical operation of multiple coefficients. An input terminal of the selection circuit is coupled to the look-up table circuit. A control terminal of the selection circuit receives the shifted input data. The selection circuit selects at least one of the processed signals of the look-up table circuit as a selected signal based on the shifted input data. The output terminal provides an output signal according to the selected signal.

Abstract: An adaptive continuous-time linear equalizer (CTLE) includes a CTLE cell including input terminals and output terminals, a low-pass filter configured to respectively output low-band differential signals obtained by respectively low-pass filtering differential output signals, and an error amplifier configured to amplify a difference between the low-band differential signals and output the difference as a control voltage. The CTLE cell includes first and second transistors each including an input terminal and an output terminal and an offset compensator configured to adjust a potential difference between a supply voltage source and the output terminal according to the control voltage.

Abstract: Certain disclosed embodiments pertain to suppressing interference in a wireless communication system. For example, a method of suppressing interference can include receiving one, two, or more first signals including components from a plurality of sub-channels. Each of the first signals can be processed by a Finite Impulse Response filter adapted using an LMS update algorithm.

Abstract: A communication system includes a receiver device having a continuous time linear equalizer circuitry. The continuous time linear equalizer circuitry includes first gain circuitry, second gain circuitry, second gain circuitry a first capacitor, a first resistive element, a first inductor, and a second resistive element. The first gain circuitry and the second gain circuitry receive an input signal. The first capacitor is connected between an output of the first gain circuitry and an output of the second gain circuitry. The first resistive element is connected between the output of the first gain circuitry and the output of the second gain circuitry. The first inductor is connected to the output of the first gain circuitry, the first capacitor, and the first resistive element. The second resistive element is connected in parallel with the first inductor.

Abstract: An apparatus is disclosed, comprising means for providing in an integrated circuit a resistive network comprising a first resistance element having a first resistance value and a second resistance element having a second resistance value, each resistance element of the resistive network being provided by one or more high-resistance contacts between conductors of the integrated circuit. The apparatus may also provide a means for providing in the integrated circuit an electrical current from the resistive network to one of a summing node output and a subtraction node output for input to a corresponding summing node input and a subtraction node input of a signal processing component. A method for forming such an integrated circuit is also disclosed.

Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.

Abstract: A feed forward equalizer includes a plurality of delay circuits connected to each other in series and configured to delay input signals. A plurality of filters respectively correspond to outputs of the plurality of delay circuits, except for a reference output which is an output of a first delay circuit among the plurality of delay circuits, and the input signals. A calculator configured to sum the reference output and outputs of the plurality of filters. Each of the plurality of filters is configured to receive an output of a delay circuit corresponding thereto, among the plurality of filters, and the reference output.

Abstract: A feed forward echo cancellation device includes a first impedance circuit, a second impedance circuit, and an echo cancellation current generator circuit. The first impedance circuit is configured to output a first current to a node in response to a transmission current. The second impedance circuit is configured to output a second current to a node in response to the transmission current. The echo cancellation current generator circuit is configured to drain an echo cancellation current from the node. The node is connected to an input terminal of a programmable gain amplifier circuit via a gain control circuit, and the gain control circuit is configured to set a gain of the programmable gain amplifier circuit.

Abstract: Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. A digital nonlinearity correction (NLC) can be implemented in a receiver signal chain having an ADC. Digital NLC can be designed as a drop in signal preconditioner for existing RF ADC wideband receiver signal chains. A unique equalizer can compensate for a variety of mixer spurs. Accordingly, digital NLC can correct nonlinearities due to mixers and any amplifiers preceding or following the ADC, potentially improving receive chains performance by 15-25 dB. Such a digital NLC solution can be particularly beneficial in defense and instrumentation applications which demand the greatest performance.

Abstract: Disclosed are a signal processing device and an image display apparatus including the same. The signal processing device comprises an equalizer configured to receive an input signal through a channel and equalize the received input signal and a control circuit configured to determine an equalizer control code in response to a first signal output from the equalizer and output the determined equalizer control code to the equalizer, wherein the equalizer may equalize the received input signal based on the equalizer control code. Accordingly, there is an effect of effectively adapting the equalizer even when a channel environment changes.

Abstract: A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Abstract: A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.

Abstract: A method for realizing predistortion compensation processing for 5G NR in-band modulated signals includes configuring the modulator to output a continuous wave signal, switch the output frequency interval of the signal to be consistent with the 5G NR subcarrier bandwidth, and record the power value P0 corresponding to the current frequency through the power meter. The power measurement difference between all points and P0 is calculated and performs normalization, and generates a compensated channel impulse response after shaping filtering; converts it into a power compensation factor in the time domain; performs inverse Fourier transform to generate I and Q baseband signals; generates compensated baseband data; the generated baseband data is filtered, and an analog zero intermediate frequency signal is generated, which is input to the broadband demodulator for frequency conversion modulation of the 5G NR broadband signal. The method operates without the need to modify the device circuit in the channel.

Abstract: A system and method for ranging secured by feedback of one or more channel metrics. The method may include: receiving, by a first modem, a first training signal, from a second modem; generating, by the first modem, a first estimate of a channel metric, based on the first training signal; receiving, by the first modem, from the second modem, a second estimate of the channel metric; determining, by the first modem, that the first estimate of the channel metric and the second estimate of the channel metric do not meet a similarity criterion; and denying, by the first modem, access to a resource.

Abstract: Embodiments may relate to a baseband module with communication pathways for a first data signal and a second data signal. The baseband module may also include a finite impulse response (FIR) filter in a communication path between the first signal input and the second signal output. Other embodiments may be described or claimed.

Abstract: Methods, systems, and devices for wireless communications are described. A base station may receive an uplink transmission from a user equipment (UE) over a wireless channel and measure a post-digital post-distortion (post-DPOD) signal-to-noise ratio (SNR) of the uplink transmission. The base station may generate a power output back-off indication for the UE according to the post-DPOD SNR and a change in a post-DPOD noise level of the transmission between a non-linear distortion noise component and a thermal noise component. The base station may transmit the power output back-off indication and a downlink transmission to the UE. In response, the base station may receive an uplink transmission from the UE over the wireless channel. The uplink transmission may be based on the power output back-off indication, a signal quality metric of the downlink transmission, or both.

Abstract: A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

Abstract: Wireless communication between a base station and at least one user equipment comprises the following. Each user equipment periodically measures channel quality of communication with the base station and transmits a channel quality indicator to the base station. The base station schedules communication with the at least one user equipment based upon the periodically transmitted channel quality indicators.

Abstract: A system includes a first device including a first transmitter and a first receiver, and a second device including a second transmitter and a second receiver and configured to communicate with the first device. The two devices perform a first equalization operation by performing a first phase in which the first receiver performs a signal tuning operation on the second transmitter, a second phase in which the second receiver performs a signal tuning operation on the first transmitter, and one or more other phases. The first, second, and other phases may constitute all the phases of the first equalization operation, and some of the other phases may precede the first and second phases. In response to detection of an error after the first equalization operation, the two devices may perform a second equalization operation by performing the first phase, the second phase, or both, but not performing the other phases.

Abstract: The present disclosure provides a decision feedback equalizer circuit. The decision feedback equalizer circuit includes: a first adder circuit, configured to add sampled data, first correction data and target correction data; a first sampler amplifier, configured to sample data output by the first adder circuit through a first signal component in a first clock signal to obtain a first sampling result; a second adder circuit, configured to add the sampled data, the first correction data and the target correction data; a second sampler amplifier, configured to sample data output by the second adder circuit through a second signal component in the first clock signal to obtain a second sampling result; and a correction parameter processing element, configured to determine the target correction data through a second clock signal, the first sampling result and the second sampling result.

Abstract: A system can comprise a memory that is configured to store and retrieve a first signal. The system can comprise a generator that is configured to generate first in-phase, quadrature sub-carrier values. The system can comprise a look up table that stores predetermined second in-phase, quadrature sub-carrier values. The system can comprise a pseudo-random look up table generator that is configured to operate on the predetermined second in-phase, quadrature sub-carrier values to produce pseudo-random data values. The system can comprise a component that is configured to inject a second signal into a radio unit, wherein the second signal is selected from the memory, the generator, the look up table, and the pseudo-random look up table generator, and wherein the second signal is configurably switched between a time domain path of a digital front end of the system, and a frequency domain path of the digital front end.

Abstract: The present disclosure relates to a concept of nonlinear signal processing which may be used for predistortion for RF power amplifiers. The concept includes generating time variant filter coefficients for a linear filter circuit based on a nonlinear mapping of an input signal, and filtering the input signal with the linear filter circuit using the time variant filter coefficients in order to generate a filtered output signal. Thus, it is proposed to implement a non-linear filter by a time-varying linear filter where the time-varying coefficients are derived from the input signal.

Abstract: Systems, methods, and devices enable spectrum management by identifying, classifying, and cataloging signals of interest based on radio frequency measurements. In an embodiment, signals and the parameters of the signals may be identified and indications of available frequencies may be presented to a user. In another embodiment, the protocols of signals may also be identified. In a further embodiment, the modulation of signals, data types carried by the signals, and estimated signal origins may be identified.

Abstract: A single-signal receiver including an active inductor continuous time linear equalizer and a reference voltage selection equalizer is provided. The single-signal receiver includes a continuous time linear equalizing unit to receive a single signal, and compensate for distortion of the single signal to generate an output, and a reference voltage selection equalizing unit to select one of a first reference voltage value and a second reference voltage value based on a previous output from a comparator, and sample the output from the continuous time linear equalizing unit, based on the one of the first reference voltage value and the second reference voltage value.

Abstract: A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.

Abstract: A system can comprise a radio unit comprising a digital front end, wherein the digital front end comprises a group of tap points that are configured to receive a first custom signal. The system can also comprise a first component that is configured to originate the first custom signal. The system can also comprise a second component that is configured to select a first tap point of the group of tap points, and inject the first custom signal into the first tap point.

Abstract: An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.

Abstract: Millimeter-wave (mmWave) and sub-mmWave technology, apparatuses, and methods that relate to transceivers and receivers for wireless communications are described. The various aspects include an apparatus of a communication device including one or more antennas configured to receive an RF signal and an ADC system. The ADC system includes a 1-bit ADC configured to receive the RF signal, and an ADC controller circuitry configured to measure a number of positive samples in the received RF signal for a plurality of thresholds of the 1-bit ADC, estimate receive signal power associated with the received RF signal based on the measured number of positive samples, determine a direct current (DC) offset in the received RF signal using the estimated received signal power, and adjust the received RF signal based on the determined DC offset.

Abstract: Techniques for new radio layer two relay are disclosed. In an example, a base station may configure a user equipment (UE) and a relay UE having individual direct communication links with the base station to configure a sidelink communication link between the UE and the relay UE. The sidelink communication link may allow the UE to communicate with the base station via the direct communication link between the base station and the UE and the sidelink communication link between the UE and the relay UE.

Abstract: An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. In embodiment, a single-ended receiver trains DFE coefficients and the slicer reference voltage to improve the received eye height. The process for training avoids many whole range sweeps thereby shortening training time. A custom data pattern that includes low-frequency (DC with respect to DFE) and high-frequency (AC with respect to DFE) worst cases is used for training in a closed loop manner. Negative DFE is used to measure the AC height of the data. Positive DFE is used to find the DC height of the data pattern.

Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

Abstract: An audio processing method includes the following operations. A calculated value is obtained according to multiple audio clock frequency information contained in multiple audio input packets. An audio sampling frequency is generated according to the calculated value and a link symbol clock signal. Multiple audio output packets corresponding to the audio input packets are generated according to the audio sampling frequency.

Abstract: A receiver device according to an embodiment includes a equalizer, a sampler, and a controller. The equalizer receive a first signal. The equalizer boosts the first signal to output a resultant as a second signal. The sampler samples the second signal. The sampler outputs a sampling result of the second signal as a first digital signal. The controller executes adaptive processing for adapting an amount of boost of the first signal. In the adaptive processing, the controller is configured to: adjust an amount of boost for the equalizer based on inter-symbol interference of a part in the first digital signal, the part matching a data pattern of a set pattern filter; and dynamically change a pattern filter to be set according to the amount of boost for the equalizer.

Abstract: A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

Abstract: A controller extracts a distortion component of a readback signal from a magnetic read head. The distortion component may be found using a finite length Volterra series, for example. The controller estimates a clearance between the read head and a recording medium based on the distortion component. This clearance measurement can be used for closed loop fly-height control of the read head.

Abstract: The present disclosure discloses a two-group portable same-frequency or different-frequency control radio frequency circuit, including two groups of radio frequency circuits and a circuit for controlling the two groups of radio frequency circuits; each group of radio frequency circuit includes a power filter circuit, a quartz crystal oscillator, a harmonic suppression circuit, an input end bias circuit, an input matching inductor, an amplifier, an output end bias circuit, an output matching circuit, a detection circuit, an antenna matching circuit, and an antenna. According to the disclosure, a controller and the detection circuits are used to perform time-sharing work on two groups of signals, and the two groups of signals are continuously switched to work, so that the problem of local heat accumulation is not caused, an action area is enlarged, and a load on key components is reduced, thereby improving the effect, the application range, and the reliability.

Abstract: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

Abstract: According to the present invention, in a wireless communication system that performs single carrier MIMO transmission between a transmitting station device and a receiving station device, the transmitting station device includes a time-domain linear equalization unit, a propagation path characteristics estimation unit configured to receive a training signal and estimate a transfer function matrix of propagation path characteristics, a filter tap calculation unit configured to calculate filter tap coefficients for the time-domain linear equalization unit based on the transfer function matrix by a predefined approach, and a transmission mode determination unit configured to make the filter tap calculation unit calculate the filter tap coefficients when the transfer function matrix meets a predefined condition, and to change a transmission mode and determine the transmission mode that meets the predefined condition when the transfer function matrix does not meet the predefined condition.