Abstract: In one embodiment, a method receives a pulse width modulation signal. A value that is a function of the pulse width modulation signal is determined. The value is used to modulate a switching frequency of the pulse width modulation signal to generate a modulated pulse width modulation signal. The applied value reduces electro-magnetic interference from tones in the modulated pulse width modulation signal.

Abstract: An NFC transmitter using a delay-locked loop and an NFC transmission method thereof are provided. The NFC near field communication (NFC) transmitter includes a delay-locked loop (DLL) that outputs a reference clock and a delayed clock using the reference clock and a value of a duty code which are input, a clock output unit that receives the reference clock and the delayed clock, outputs the reference clock in any of a high section and a low section of input data, and outputs a converted clock having a duty ratio using the reference clock and the delayed clock in the other of the high section and the lower section of the input data, and an RF signal generator that generates an RF signal using a PWM (Pulse Width Modulation) signal input from the clock output unit.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: A clock data recovery circuit includes a ring oscillator, an oscillation control circuit unit to start or stop the ring oscillator according to existence or absence of a PWM signal, a counter circuit unit to count pulse signals to hold N bits of count value, a register circuit unit which is configured to transmit upper M bits of count value, as a reference count value, in response to a transmission signal, a comparison circuit unit to output a timing clock when the count value exceeds the reference count value, and a transmission control circuit unit to be synchronized with a rising timing of the PWM signal to generate the transmission signal and a reset signal for resetting the counter circuit unit.

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Abstract: A device and a method for pulse width modulation is disclosed, wherein the temporal occurrence of both the respectively rising and the respectively falling edges of a pulse signal is varied.

Abstract: A PWM circuit that can have two refresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two refresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal.

Abstract: A torque measurement system that includes a rotor device and a stator device can perform automatic tuning to improve the initial tuning performed during design and assembly. The stator device can include a variable capacitive element and a micro-controller configured to adjust a capacitance value of the variable capacitive element. Additionally or alternatively, the rotor device can include a variable capacitive element and a micro-controller configured to adjust a capacitance value of the variable capacitive element. The adjustment of the capacitive elements can be based on the quality of signal detected at either the rotor device or stator device.

Abstract: A method of generating spurious-noise-free power from a switching device. The method includes generating an oscillating signal in the form of a series of pulse trains, and randomly changing the switching frequency, or the on-time, or both the switching frequency and the on-time of the switching device. The method further includes causing the switching device to change from a first frequency to a second frequency only at the end of a pulse train of the first frequency, and causing the second frequency to start at the beginning of its first pulse train such that no switching duty-cycle disturbance at the time of the change from first to second frequency. In a particular embodiment, the method further generates spurious-noise-free power from a switching device by implementing a relationship between the different switching frequencies involved such that spurious-noise-free operation is achieved.

Abstract: The present systems and methods may shape signals to meet emission mask requirements, current consumption requirements, and overshoot/undershoot requirements relating to the interaction that, for example, occurs when a near field communications (NFC) target comes within range of an NFC initiator, and the initiator generates and transmits an NFC waveform. In some implementations, a pair of bit patterns are defined whose differential output from an amplifier is a shaped pulse width modulated waveform. Varying individual bits of the bit patterns can vary the shaped pulse waveform with predictability. The pulse width modulated waveform may be filtered using a matching network that reduces higher order harmonics, thereby reducing out-of-band emissions.

Abstract: A Power Management Integrated Circuit (PMIC) includes a pulse width modulator and driver circuit (PWMDC), a processor, and high-side and low-side driver circuitry. The PWMDC, along with components external to the PMIC, forms a switching power supply. A small linear regulator powers the PWMDC from power received via a terminal. The power supply supplies power to other on-chip circuitry, including the driver circuitry and processor. The PWMDC starts an on pulse (of a power supply switching cycle) in response to a clock signal. In a first mode, the PWMDC stops the on pulse based on a signal received from a terminal via an analog feedback signal path. In a second mode, the PWMDC stops the on pulse based on a signal received via a digital feedback signal path. In one example, the digital feedback signal path extends from a terminal, through an ADC, processor, and DAC, to an error node.

Abstract: A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. These components, in combination with other circuitry external to the integrated circuit, are configurable to form a selected one of a number of different switching power supply circuits. Upon power up, an internal regulator supplies power to the CSPSPWM. The CSPSPWM then controls the power supply to begin switching in a low frequency start-up mode. The CSPSPWM determines during start-up the current sensing method based on circuitry external to the integrated circuit. A supply voltage generated is then supplied via a conductor of a standardized bus to a processor in the MCU/ADC tile. The processor begins executing instructions, and as a result writes across the standardized bus to configure the various tiles of the MTPMIC.

Abstract: In an embodiment, a method of generating a pulse-width modulated signal from an input signal includes calculating a finite number of basis functions of a first pulse-width modulated signal based on the input signal, and forming an electronic output based on the calculated finite number of basis functions.

Abstract: A pulse width modulator has a first clock source providing a clock signal to a set input of an output controller configured to set a pulse width output signal and having a reset input to reset the pulse width output signal. A duty cycle control unit is coupled with the reset input of the output controller, wherein the duty cycle control unit has a numerical controlled oscillator (NCO) being coupled with a register and configured to provide for a direct digital synthesis to produce a specified frequency according to a value set in the register. Furthermore, logic is provided for receiving a signal from a second clock source and the pulse width output signal to trigger the numerical controlled oscillator.

Abstract: A system involves a transmitting device (for example, a first wireless communication device) and a receiving device (for example, a second wireless communication device). In the receiving device, LLR (Log-Likelihood Ratio) values are stored into an LLR buffer. LLR bit width is adjusted as a function of packet size of an incoming transmission to reduce the LLR buffer size required and/or to prevent LLR buffer capacity from being exceeded. The receiver may use a higher performance demodulator in order to maintain performance despite smaller LLR bit width. In the transmitting device, encoder code rate is adjusted as a function of receiver LLR buffer capacity and packet size of the outgoing transmission such that receiver LLR buffer capacity is not exceeded. Any combination of receiver LLR bit width adjustment, demodulator selection, and encoder code rate adjustment can be practiced to reduce LLR buffer size required while maintaining performance.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A discrete digital transceiver includes a receiver sample and hold module, a discrete digital receiver conversion module, a transmitter sample and hold module, a discrete digital transmitter conversion module, clock generation module, and a processing module. The receiver sample and hold module samples and holds an inbound wireless signal in accordance with a receiver S&H clock signal. The discrete digital receiver conversion module converts the receiver frequency domain sample pulse train into an inbound baseband signal. The transmitter sample and hold module samples and holds an outbound signal to produce a transmitter frequency domain sample pulse train. The discrete digital transmitter conversion module converts a transmitter frequency domain sample pulse train into the outbound wireless signal. The clock generation module generates S&H clock signals in accordance with a control signal. The processing module generates the control signal such that the S&H clock signals are shifted.

Abstract: A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. These components, in combination with other circuitry external to the integrated circuit, are configurable to form a selected one of a number of different switching power supply circuits. Upon power up, an internal regulator supplies power to the CSPSPWM. The CSPSPWM then controls the power supply to begin switching in a low frequency start-up mode. The CSPSPWM determines during start-up the current sensing method based on circuitry external to the integrated circuit. A supply voltage generated is then supplied via a conductor of a standardized bus to a processor in the MCU/ADC tile. The processor begins executing instructions, and as a result writes across the standardized bus to configure the various tiles of the MTPMIC.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: An electrical resonance network comprising a first capacitor and a first inductor whose resonance frequency can be tuned by means of a second capacitor and/or a second inductor. The resulting effective capacitor- or inductor value of a network period is controlled by a variable coupling respectively decoupling interval by means of at least one coupling switch. The coupling respectively decoupling interval is synchronized by a sign change of a current and/or voltage in the network.

Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between a reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

Abstract: System and method embodiments are provided for improving power efficiency in an outphasing amplifier with a non-isolating combiner. Some embodiments include a circuit comprising a signal decomposer configured to receive an input signal, a non-isolating combiner coupled to the signal decomposer and configured to provide an amplified output signal corresponding to the input signal, a first power amplifiers (PA) on a first branch between the signal decomposer and the non-isolating combiner, a second PA on a second branch between the signal decomposer and the non-isolating combiner, and a switch on the second branch between the signal decomposer and the second PA. The switch is configured to disconnect the second PA from the signal decomposer upon determining that the input signal is in a first condition, and further configured to connect the second PA to the signal decomposer upon determining otherwise.

Abstract: A power converter system includes an interleaved power converter having a plurality of parallel-connected phase legs between DC terminals and an AC terminal. A plurality of parallel-connected inductors are each connected to one of the plurality of parallel-connected phase legs to provide a summed output of the parallel-connected phase legs to the AC terminal. A controller generates PWM signals used to control the state of each of the plurality of phase legs by comparing a carrier signal to a reference signal, wherein a period of the carrier signal is randomly varied from a nominal period.

Abstract: A method for transmitting radio frequency (RF) signals is provided. In-phase (I) and quadrature (Q) signals are received and filtered using sigma-delta modulation. I and Q pulse width modulation signals are generated from the filtered I and Q signals and interleaved so as to generate a time-interleaved signal. The time-interleaved signal is then amplified to generate the RF signals.

Abstract: Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). The EVSE and EV exchange a Pulse Width Modulation (PWM) signal on the pilot wire to control charging operations of the EV. Data communications may also be transmitted on the pilot wire, such as between transmit and receive modems. The modems transmit communication signals either continuously, without regard to the state of the PWM signal, or only when the PWM is in an off-state. If transmitting while PWM is on, the modem needs a large coupling impedance and/or a large signal injection. To transmit only when the PWM is off, the modem may use a blocking diode in the coupling circuit or may synchronize to the pulses in the PWM signal.

Abstract: A method comprises: detecting a first change of a physical property of a signal; starting a measurement of a duration of a first time interval that begins with the detection of the first change; detecting a second change of the physical property; stopping the measurement of the duration of the first time interval and starting a second measurement of a duration of a second time interval in response to the detection of the second change; detecting a third change of the physical property, and stopping the second measurement in response to detecting the third change; determining a relation of the durations of the first time interval and the second time interval from the first measurement and the second measurement; and determining the received data value based on the determined relation of the durations of the first time interval and the second time interval.

Abstract: An amplifier includes a first stage, a second stage coupled to the first stage, and a summation circuit. The first stage is configured to receive an analog input signal, convert the analog input signal to a digital signal, and output an intermediate analog output signal in response to the digital signal. The second stage is configured to output a second analog intermediate output signal based on a scaled pulse width modulation quantization error of the first stage. The summation circuit is configured to combine the first and second analog intermediate output signals to generate an amplified output signal.

Abstract: A finite sequence of code values is formed, and can be used for example in communications or remote sensing. A code value in said finite sequence of code values has a validity period specific to that code value. There are code values of different validity periods in said finite sequence of code values. Each of said validity periods is longer than or equal to a predetermined minimum baud length.

Abstract: Described herein are an apparatus, system, and method for generating pulse modulated (PWM) signals. The apparatus (e.g., input-output transmitter) comprises: an edge detector to detect one of a rising or falling edges of a clock signal; a counter to count up or down in response to detecting one of the rising or falling edges of the clock signal, the counter to generate a select signal; and a control unit to receive a data signal for transmission to a receiver and to generate a PWM signal as output according to a value of the select signal and the data signal, wherein the receiver and the transmitter are a Mobile Industry Processor Interface (MIPI®) M-PHYSM receiver and transmitter.

Abstract: A method is provided for generating a digital signal (DS) from an analog signal (IA, UA) generated by a frequency converter on the basis of pulse width modulation, wherein the digital signal corresponds to a mean value of the analog signal over a period of the pulse width modulation. The method includes the acts of: generating a bit stream (BS(i)) with a predetermined bit repetition duration (BW) depending on the analog signal by way of a sigma-delta modulator (1) and, during a time interval which has a duration which is at least as great as the period of the pulse width modulation: multiplying a respective bit (BS(i)) of the bit stream by a corresponding rating coefficient (BK(i)) for generating a respective bit/rating coefficient product and summing the respective bit/rating coefficient products, wherein the sum represents the digital signal.

Abstract: A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay.

Abstract: A transmission circuit comprises a ??? modulator to perform ??? modulation of an amplitude modulation component of a modulation signal and to output a pulse width modulation signal, an angle modulator to generate an angle modulation component signal of a signal obtained by multiplying the modulation signal by a transmission output control coefficient corresponding to a transmission output in a power amplifier, and a multiplier to multiply the pulse width modulation signal by the angle modulation component signal and to output a result of the multiplication as an output signal to the power amplifier.

Abstract: A method, an apparatus, and a system for controlling a carrier Power Amplifier (PA) of a Base Station (BS) in a network communication field are disclosed. The method includes: obtaining power control information of the carrier PA at a next timeslot; and adjusting working voltage of the carrier PA at the next timeslot according to the power control information. An apparatus and a system for controlling a carrier PA of a BS are also disclosed. The method, apparatus, and system can reduce energy consumption of the BS and improve energy efficiency of the BS.

Abstract: A method for a wireless communication system is provided. The method includes isolating a set of pilot signals, where the pilot signals are associated with multiple base stations or multiple sectors of a single base station. This includes nulling a subset of the pilot signals to mitigate co-channel interference and to perform channel estimation in accordance with at least one of the pilot signals.

Abstract: A transmitter (TX) for transmitting a pulse density modulated signal comprises means (SDM) for generating a pulse density modulated input signal (SI) and an encoder (ENC). The encoder (ENC) comprises a first input for receiving the pulse density modulated input signal (SI) and a second input for receiving additional information (AI) comprising at least one data bit. The encoder (ENC) is configured to generate a multi-bit telegram (TG) on the basis of the additional information (AI), the telegram (TG) comprising a predefined bit-sequence, and to replace an appropriate number of consecutive bits of the input signal (SI) with the telegram (TG) in order to generate an output signal (SO).

Abstract: An integrated circuit includes: a digitally-controlled power generation stage for converting an input signal to a radio frequency (RF) carrier, the digitally-controlled power generation stage including a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal according to a fractional word and operably coupleable to the plurality of selectable switching devices of the digitally-controlled power generation stage; wherein the PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope of the RF carrier output from the digitally-controlled power generation stage.

Abstract: A pulse-width modulator (PWM) includes a plurality of comparators for comparing an input signal with a plurality of reference signals and for providing a plurality of corresponding comparison signals. The pulse-width modulator also includes a combinational logic for receiving the plurality of comparison signals and for generating a plurality of binary pulse-width modulation signals on the basis of the plurality of comparison signals. At most only a currently selected binary pulse-width modulation signal of the binary pulse-width modulation signals is at a first signal level at a time. The currently selected binary pulse-width modulation signal is associated to a specific reference signal of the plurality of reference signals which is currently closest to the input signal among the plurality of reference signals in terms of a given amplitude relation between the plurality of reference signals and the input signal.

Abstract: A method and system for storing and transmitting data using variable pulse characteristics to represent ASCII or UNICODE characters, of the value of a string of data using a number base higher than 2. Pulse characteristics are modified to correspond to different data values. Pulse characteristics can include pulse durations, pulse spacings, pulse amplitudes, pulse phases, pulse polarities, pulse shapes and/or other pulse characteristics.

Abstract: A switching amplifier with an embedded harmonic rejection filter is disclosed. In an exemplary design, the switching amplifier includes a generator circuit and a plurality of output circuits. The generator circuit receives an input signal and a carrier signal at a carrier frequency and generates a plurality of versions of a drive signal associated with different delays. The drive signal may be a pulse width modulation (PWM) signal. The plurality of versions of the drive signal may be generated by delaying the carrier signal, or the input signal, or the drive signal. The output circuits receive the plurality of versions of the drive signal and provide an output signal. The output circuits have outputs that are coupled together and implement a finite impulse response (FIR) filter based on the plurality of versions of the drive signal. The FIR filter has a frequency response with zeros at harmonics of the carrier frequency.

Abstract: An amplifying circuit is provided and includes a signal processor, an edge detector, and a calibration controller. The signal processor transforms amplitude information of a first and second input signals into time domain to provide first and second output signals respectively. The edge detector detects a polarity of a voltage offset from a timing relationship of the first and second output signals. The calibration controller compensates the voltage offset according to a change of the detected polarity.

Abstract: In a data communication system according to one aspect of the present invention, a data carrier driving apparatus, which communicates with a data carrier apparatus using a rectification smoothing circuit for generating a power supply voltage, controls a pulse width of each pulse of a clock signal (pulse voltage) supplied to the data carrier apparatus. The data carrier driving apparatus sets the duration of each pulse of a pulse voltage generated by the data carrier driving apparatus, so as to suppress a decrease in the level of the pulse voltage caused by a charging operation for the rectification smoothing circuit, particularly, such that the duration in which the pulse voltage becomes a high-level voltage is longer than or equal to the duration in which the pulse voltage becomes a low-level voltage during one period.

Abstract: An apparatus and method for controlling a device using pulse signals. In the apparatus and method, a two-stage control is used to generate pulse signals, which can be a PWM signal, a pulse signal including a PWM signal with a sleeping time, or a PDM signal. The two-stage control includes a second stage control, which generates pulse signals according to parameter values generated periodically by a first stage according to a target value and feedback sensing values. The two-stage control can be used in decreasing perturbation in a closed-loop control and accurate open-loop control.

Abstract: A systems, pulse generators, apparatus and methods for generating a high power signal are presented. A pulse generator includes a generator and a modulator unit. The generator generates a bipolar signal. The modulator unit modulates the bipolar signal with oscillating signals to generate a modulated bipolar signal with oscillating portions. The frequency spectrum of the modulated bipolar signal contains very little to no direct current (DC) component.

Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.

Abstract: A communication apparatus includes a detecting unit, a process performing unit, and a range setting unit. The detecting unit detects a boundary pattern periodically appearing between codes in a binary coded signal transmitted through a transmission line. The boundary pattern is information showing a boundary appearing between codes. The process performing unit performs a process in synchronization with timing of appearance of the boundary pattern. The range setting unit sets an allowance range which is set include timing at which it is estimated that the next boundary pattern appears. The timing is counted from the timing currently detected by the detecting unit. The detecting unit includes a section which detects the timing of appearance of the boundary pattern during the allowance range.

Abstract: A technique includes using a first signal that is produced by a counter to generate a center-aligned pulse width modulation signal having a first time profile and using the first signal to concurrently generate a pulse width modulation signal that has a second time profile that is different from the first time profile.

Abstract: A method and apparatus is provided for reducing interference in a communication system. A feedback-controlled biased inverting limiter is used to reduce interference power by trapping the interfering signal, while passing the wanted signal through to the output. The amplitude trap triples the frequency of a signal component of a particular amplitude, thus shifting it out of the communication band and into the stopband of the receiver or transponder filter. The feedback-controlled biased inverting limiter uses a hard limiter, window comparator, feedback loop, and an exclusive NOR gate to trap the interfering signal, while allowing the wanted signal to pass through to a receiver.

Abstract: A method and an apparatus for sending a Precoding Matrix Index (PMI) and performing precoding are provided in the embodiments of the present invention. The method for sending the PMI comprises the following steps: a user equipment acquires the transmission channel capability of carrying the PMI; according to the transmission channel capability of carrying the PMI, the precoding matrices are selected from a locally-stored first codebook set to form a second codebook set; a first precoding matrix is selected from the second codebook set; an index corresponding to the first precoding matrix is sent to a base station over the transmission channel so as to make the base station can find out the first precoding matrix according to the index and precode the data according to the first precoding matrix. The embodiments of the present invention can realize the flexible configuration and use of the PMI.

Abstract: A system having has a pulse width modulation controller to successively activate each of a plurality of channels each in its own individual channel time slot is described. The system also has a sampling multiplexer configured to successively sample a signal derived from each of the plurality of channels during each individual channel time slot. Each individual time slot has an individual sampling sequence.

Abstract: An active circuit control system that utilizes multiple PWM signals to activate and power an array of active components, requiring minimal wiring between the multi-mode signal conditioner and active components. Signal conditioning and filtering is implemented to allow transmission of power and control signals for multiple components over a single or multiple transmission lines. The circuit can be used to provide supply voltage and control signals for active antennas, switch networks, and other components in communication systems and electronic devices.