Abstract: A video signal processing device is configured to include a quantizer that sequentially outputs quantized data obtained by quantizing input data based on the video data of the first gradation into the video data of the second gradation, a storage that sequentially stores the quantized data output from the quantizer, a difference calculator that sequentially calculates differences between the video data of the first gradation for a current frame and the quantized data for a previous frame stored in the storage, and an integrator that sequentially outputs integral data obtained by sequentially integrating data output from the difference calculator as the input data of the quantizer.

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.

Abstract: A jitter generating circuit wherein a simple structure can be used to generate a pattern effect jitter. A jitter generating circuit 1 comprises a driver input circuit 20 that serves as a signal analyzing unit for analyzing the contents of the signal pattern of an input signal; a plurality of gain adjusting circuits 30; a plurality of lowpass filters 40; a plurality of adders 50; an adder 52; and a driver output circuit 60 that outputs a signal obtained by adjusting, in accordance with a signal analysis result, the phase of the input signal in such a direction in which the change timing deviates when the input signal is transmitted to the transmission line. Thus, the phase of an input signal is adjusted, thereby adding the jitter to the input signal.

Abstract: At a base station apparatus, known pilot signals for use in channel estimation are transmitted, and in addition thereto MCS pilot signals that are used to perform adaptive modulations respectively corresponding to a plurality of modulation schemes are multiplexed and output. A mobile station apparatus dispreads the respective MCS signals out of the multiplex signal, compares these to known symbols patterns, and sends the MCS pilot signals that show a matching relationship to the base station apparatus as a mobile station reception result. Upon receiving the mobile station reception result from the mobile station apparatus, the base station apparatus selects the modulation scheme of the optimum modulation level for the downlink signals. This configuration makes it possible to switch the modulation schemes in an accurate and simple way.

Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

Abstract: An Ethernet mapping enables high speed Ethernet data streams having a data rate of 10 Gb/s to be transported across a synchronous packet switched network fabric having a standard SONET OC-192 line rate of 9.953280 Gbaud. The 10 Gb/s Ethernet data stream is compressed by removing interframe gaps between successive MAC frames to produce a compressed data stream, which is then mapped to a synchronous container. The synchronous container is then launched across the synchronous packet switched network fabric at a standard SONET OC-192 line rate of 9.953280 Gbaud. The synchronous container is preferably provided as a stripped STS-192c frame having only A1 and A2 octets of the Transport Overhead (TOH).

Abstract: A multi-level pulse width modulation (multi-level PWM) technique uses multiple voltage levels and/or multiple output channels to obtain improved resolution (also referred to as dynamic range) over ordinary PWM-based digital systems, in particular digital audio systems. A digital audio signal is converted to either (1) an N-level PWM signal which is output to a single channel including a filter and loudspeaker, (2) N components of an N-level PWM signal output to N corresponding channels, or (3) some number of multi-level signals output to multiple channels. The digital audio signal can also be divided into different frequency bands to be processed separately and output to different sets of loudspeakers, wherein fewer low frequency loudspeakers can be used than high frequency loudspeakers to produce equal effective resolution for the output of all frequency bands. The multi-level PWM technique can also be adapted to control the output of other types of PWM-based systems when greater resolution is desired.

Abstract: High-bit rate communication system for networking computing systems are described. The system uses a hybrid ultra-wideband orthogonal frequency division-multiplexing scheme. The transmitted signals are sparse pulse trains modulated by a frequency selected from a properly designed set of frequencies. The train itself consists of frequency modulated ultra-wide pulses. Sigma-Delta modulation is used in some implementations. Additionally, pilots can be transmitted over some subcarriers to demodulate an information bearing subcarrier. The system achieves good detection by integrating several pulses, and high throughput by transmitting frequencies in parallel. Unlike traditional orthogonal frequency division-multiplexing systems, a given tone is transmitted only during parts of the transmission interval.

Abstract: In a digital radio communication system for wireless bidirectional communication between a master station and a slave station, each of the master station and the slave station includes a antenna, a subscriber interface, a first signal processing circuit for converting a first continuous data signal from the subscriber interface into a first burst digital signal and allocating it to a first predetermined time slot, a single modulation circuit for modulating the output signal of the first signal processing circuit and transmitting a modulated signal to the antenna, a single demodulation circuit for demodulating a signal from the antenna and generating a second burst digital signal; and a second signal processing circuit for converting a demodulated signal of a second predetermined time slot into a second continuous data signal and transmitting it to the subscriber interface.

Abstract: A signal processing system receives and mixes a plurality of analog input signals having a maximum frequency. Each analog input signal is connected to an input of a modulator producing a high frequency oversampled digital signal. Each high frequency oversampled signal is connected to an input of a first decimation filter which produces an intermediate frequency oversampled multiple bit signal. Each of the intermediate frequency oversampled signals is connected to a respective input of a first digital mixer which produces a single mixed multiple bit output signal. The single mixed multiple bit output signal is connected to a second decimation filter which produces a final digital output signal, at a frequency suitable for representing the mixed analog input signals.

Abstract: A delta modulator automatically adjusting the slewing rate is disclosed. In the absence of a transition in the output data of a delta modulator, a parameter used for the integrator of the delta modulator is increased. When the comparator of the modulator indicates that the feedback signal of the modulator has overshot the input signal, the parameter is decreased or reversed until the two signals are approximately equal as signalled by a 50% duty cycle.