Abstract: A touch sensor device includes a first panel, a second panel, and a drive-sense circuit (DSC). The first panel that includes first electrodes arranged in a first direction and second electrodes arranged in a second direction. The second panel includes third electrodes arranged in a third direction and fourth electrodes arranged in a fourth direction. The DSC is operably coupled via a single line to a coupling of a first electrode of the first electrodes and a first electrode of the third electrodes. The DSC is configured to provide the signal, which is generated based on a reference signal, via the single line to the coupling and simultaneously to sense the signal via the single line. The DSC generates a digital signal representative of the at least one electrical characteristic associated with the first electrode of the first electrodes and/or the first electrode of the third electrodes.

Abstract: Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Abstract: An input stage circuit for a sigma-delta analog-to-digital converter circuit receives a digital-to-analog converter generated feedback signal and an analog current input signal to generate a difference signal applied to an integrator circuit. A single bit quantization circuit quantizes an output of the integrator circuit to generate a bit signal that is applied to an input of the digital-to-analog converter. The input stage circuit includes a switched input capacitor controlled by first and second, non-overlapping, clock signals.

Abstract: A vibration rectification error correction device includes a reference signal generation circuit that outputs a reference signal, a first frequency delta-sigma modulation circuit that performs frequency delta-sigma modulation on the reference signal by using a first measured signal to generate a first frequency delta-sigma modulated signal, a first filter, a second filter that operates in synchronization with the reference signal, and a first timing control circuit that controls a timing of outputting an input signal in synchronization with the first timing signal, in which the first filter and the first timing control circuit are provided on a signal path from an output of the first frequency delta-sigma modulation circuit to an input of the second filter.

Abstract: A power supply signal conditioning system includes a power supply, one or more loads, and a drive-sense circuit (DSC). The power supply is operably coupled to one or more loads. When enabled, the power supply configured to output a power supply signal having a DC (direct current) voltage component and a ripple voltage component that is based on conversion of an AC (alternating current) signal in accordance with generating the power supply signal. The DSC is operably coupled to the power supply. When enabled, the DSC is configured simultaneously to sense the power supply signal and, based on sensing of the power supply signal, adaptively to process the power supply signal in accordance with reducing or eliminating the ripple voltage component of the power supply signal to generate a conditioned power supply signal to service the one or more loads.

Abstract: A touch sensor device includes a first panel, a second panel, and a drive-sense circuit (DSC). The first panel that includes first electrodes arranged in a first direction and second electrodes arranged in a second direction. The second panel includes third electrodes arranged in a third direction and fourth electrodes arranged in a fourth direction. The DSC is operably coupled via a single line to a coupling of a first electrode of the first electrodes and a first electrode of the third electrodes. The DSC is configured to provide the signal, which is generated based on a reference signal, via the single line to the coupling and simultaneously to sense the signal via the single line. The DSC generates a digital signal representative of the at least one electrical characteristic associated with the first electrode of the first electrodes and/or the first electrode of the third electrodes.

Abstract: A touch sensor device includes a first panel, a second panel, and a drive-sense circuit (DSC). The first panel that includes first electrodes arranged in a first direction and second electrodes arranged in a second direction. The second panel includes third electrodes arranged in a third direction and fourth electrodes arranged in a fourth direction. The DSC is operably coupled via a single line to a coupling of a first electrode of the first electrodes and a first electrode of the third electrodes. The DSC is configured to provide the signal, which is generated based on a reference signal, via the single line to the coupling and simultaneously to sense the signal via the single line. The DSC generates a digital signal representative of the at least one electrical characteristic associated with the first electrode of the first electrodes and/or the first electrode of the third electrodes.

Abstract: A method for detecting objects via a vehicular radar sensing system includes equipping a vehicle with a vehicular radar sensing system, the vehicular radar sensing system including a radar sensor. An analog input signal derived from received radio signals is converted, via a first ADC, into a first number of bits M. The first number of bits M is converted, via a DAC, into a first analog signal. A second analog signal is determined by subtracting, via a subtractor, the first analog signal from the analog input signal. The second analog signal is converted, via a second ADC, into a second number of bits K. A total number of bits N is established by concatenating the first number of bits M to the second number of bits K. A processor processes the total number of bits N to detect the object that the received radio signals are reflected from.

Abstract: Wireless communications systems may configure a subset of allocated resources (e.g., one or more resource elements (REs) of one or more allocated resource blocks (RBs)) as peak reduction tones (PRTs) for a peak-cancelation signal. For instance, wireless communications systems may configure a fixed PRT allocation based on a Costas array. In some examples, each column of a Costas array may correspond to a RB of a set of allocated resources. A transmitting device may thus identify one or more PRT REs based on the Costas array and a mapping of allocated RBs to the columns of the Costas array. For instance, a transmitting device may identify a pattern of PRT REs to use for a peak-cancellation signal based at least in part on a configured Costas array (e.g., where the peak-cancellation signal may reduce peaks of a corresponding data signal to ultimately reduce peak-to-average power ratio (PAPR) of a transmission).

Abstract: A touch sensor device includes a first panel, a second panel, and a drive-sense circuit (DSC). The first panel that includes first electrodes arranged in a first direction and second electrodes arranged in a second direction. The second panel includes third electrodes arranged in a third direction and fourth electrodes arranged in a fourth direction. The DSC is operably coupled via a single line to a coupling of a first electrode of the first electrodes and a first electrode of the third electrodes. The DSC is configured to provide the signal, which is generated based on a reference signal, via the single line to the coupling and simultaneously to sense the signal via the single line. The DSC generates a digital signal representative of the at least one electrical characteristic associated with the first electrode of the first electrodes and/or the first electrode of the third electrodes.

Abstract: One embodiment is directed to a method of using variable-resolution quantization to front-haul at least some data over a front-haul network in a system configured to provide wireless service to user equipment. The method comprises, for each symbol position, determining a respective number of required resource blocks having respective actual user-equipment (UE) signal data to front-haul for each carrier and determining the number of high-resolution resource blocks that can be quantized at a higher resolution as a function of a difference between a nominal per-symbol-position front-haul link capacity and a link capacity needed to front-haul the required resource blocks for all of the carriers if quantized using a lower resolution. The method further comprises, for each symbol position, allocating the high-resolution resource blocks to each carrier and determining, for each carrier, which of the required resource blocks to quantize at the higher resolution. Other embodiments are disclosed.

Abstract: A touch sensor device includes a first panel, a second panel, and a drive-sense circuit (DSC). The first panel that includes first electrodes arranged in a first direction and second electrodes arranged in a second direction. The second panel includes third electrodes arranged in a third direction and fourth electrodes arranged in a fourth direction. The DSC is operably coupled via a single line to a coupling of a first electrode of the first electrodes and a first electrode of the third electrodes. The DSC is configured to provide the signal, which is generated based on a reference signal, via the single line to the coupling and simultaneously to sense the signal via the single line. The DSC generates a digital signal representative of the at least one electrical characteristic associated with the first electrode of the first electrodes and/or the first electrode of the third electrodes.

Abstract: A sigma-delta modulation device includes a detection circuit and a sigma-delta modulator. The detection circuit is configured to detect an input signal to generate a detection signal, and compare the detection signal and a threshold to generate a control signal. The sigma-delta modulator is coupled to the detection circuit and configured to store a plurality of noise transfer functions, select one of the noise transfer functions according to the control signal, and convert the input signal into an output signal according to the noise transfer function.

Abstract: Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

Abstract: Methods and systems for processing audio signals containing speech data are disclosed. Biometric data associated with at least one speaker are extracted from an audio input. A match is determined between the extracted biometric data and stored biometric data associated with a consenting user profile, where a consenting user profile is a user profile associated with a record indicating consent to store biometric data. If a match is determined to exist with such a profile, the speech data is stored in an archive after processing. If no such match is determined, or if the extracted biometric data includes data from a speaker not having a consenting user profile, the speech data is discarded, optionally after having been processed. The system and method provides a safeguard against transferring to storage data of users, particularly minors or children, for whom a verified and valid consent has not been obtained from an authorised adult.

Abstract: A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: A bandgap reference circuit includes a first bipolar junction transistor (BJT) in series with a first current generator, the first BJT and the first current generator configured to produce a first proportional to absolute temperature (PTAT) signal. The circuit also includes a second BJT in series with a second current generator, the second BJT and the second current generator configured to produce a second PTAT signal. The bandgap reference circuit maintains a current through at least one of the first BJT or the second BJT within a constant ideality factor region of the at least one of the first BJT or the second BJT.

Abstract: A method for generating a tone signal (TS) having a tone frequency, f, wherein the method comprises the following steps: supplying (S1) a binary bit stream (BBS) having a mark pattern with a supply bit rate, BR, to a signal filter unit; and filtering (S2) the supplied binary bit stream (BBS) by said signal filter unit to generate the tone signal (TS), wherein the mark pattern of the binary bit stream (BBS) supplied to said signal filter unit is adapted to minimize a ratio of the supply bit rate, BR, to the tone frequency, f, of the generated tone signal (TS).

Abstract: The present invention presents fully noncausal predictive encoding and decoding methods for image, video and other signal coding. The presented noncausal predictive image coding methods largely reduce the prohibitive computational cost of the prior invention. The presented noncausal signal encoding method comprises: (1) splitting the source signal into a plurality of noncausal coding units; (2) extending each noncausal coding unit with the selected extension type; and (3) encoding each noncausal coding unit with the selected intra-unit noncausal predictor and intra-unit noncausal predictive encoding method.

Abstract: An analog-to-digital converter can produce a digital signal representative of an analog input electrical signal. An optical amplitude modulator can modulate an input optical pulse train using the analog input electrical signal to produce a first modulated optical pulse train. An optical splitter can split the first modulated optical pulse train into a plurality of modulated optical pulse trains. A plurality of detectors can convert the plurality of modulated optical pulse trains into respective modulated voltage pulse trains. A plurality of comparators and a decoder, arranged in a flash converter topology, can receive the modulated voltage pulse trains and output the digital signal representative of the analog input electrical signal using a timing reference derived from the input optical pulse train. Using a relatively high-precision input optical pulse train, such as a Kerr Comb, can produce a relatively high-accuracy analog-to-digital converter.

Abstract: Disclosed are three methods for precise measurement of frequency deviation of known nominal frequency. Delta adder method (DA), comprising of delta-sigma modulator, delta-adder, delay line, low-pass filter, and zero crossing detector. The second method (DA+RE), comprising of delta-sigma modulator, circuit for squaring delta-sigma bit-stream, delta-adder, low-pass filter, and zero-crossing detector. The third method comprises of reference delta-sigma modulator for synchronization of two or more dislocated frequency sources of known nominal frequency.

Abstract: To prevent that the noise occurs at timing switching between PCM data and DSD data by a simple configuration. An AV receiver 1 includes a mute circuit 5 that mutes output from a DAC 4, a detection circuit 6 that detects that a digital audio signal is zero data and supplies a detection signal, a microcomputer 2 that supplies a control signal at timing switching from PCM data to DSD data before switches from PCM mode that the DAC 4 converts PCM data into an analog audio signal to DSD mode that the DAC 4 converts DSD data into the analog audio signal, and an AND circuit 7 that activates the mute circuit 5 in case that the detection signal from the detection circuit 6 and the control signal from the microcomputer 2 are supplied.

Abstract: An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.

Abstract: A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

Abstract: Methods and systems for stabilizing a resonant modulator include receiving pre-modulation and post-modulation portions of a carrier signal, determining the average power from these portions, comparing an average input power to the average output power, and operating a heater coupled to the modulator based on the comparison. One system includes a pair of input structures, one or more processing elements, a comparator, and a control element. The input structures are configured to extract pre-modulation and post-modulation portions of a carrier signal. The processing elements are configured to determine average powers from the extracted portions. The comparator is configured to compare the average input power and the average output power. The control element operates a heater coupled to the modulator based on the comparison.

Abstract: An amplifier includes a differential input with a positive and a negative input and an analog integrator with a differential integrator input and a differential integrator output. The analog integrator further includes an operational amplifier with a positive operational amplifier input, a negative operational amplifier input, a positive operational amplifier output and a negative operational amplifier output. The differential integrator input is coupled to the differential input. A ternary pulse width modulator includes two modulator inputs coupled to the differential integrator output and two modulator outputs. A first feedback path is coupled between a first of the two modulator outputs and the positive operational amplifier input and a second feedback path is coupled between a second of the two modulator outputs and the negative operational amplifier input. A first divert capacitor is coupled between the positive operational amplifier input and a constant voltage reference.

Abstract: The invention discloses a transmitter comprising a pulse encoder for creating pulses from the amplitude of an input signal to the transmitter, a compensation signal generator for cancelling quantization noise caused by the pulse encoder, a mixer or I/Q modulator for mixing an output of the pulse encoder with the phase of an input signal to the transmitter and an amplifier for creating an output signal from the transmitter. In the transmitter, a control signal (CA) for controlling a function of the amplifier comprises an output signal from the compensation signal generator, and an input signal to the amplifier comprises an output from the mixer having been modulated to a desired frequency.

Abstract: A signal conversion method including converting an input signal into a 1-bit pulse train representing an analog signal is provided. The 1-bit pulse train has a pulse rising waveform frise and a pulse falling waveform ffall. The pulse rising waveform frise includes a first distortion component with respect to an ideal pulse rising waveform, and the pulse falling waveform ffall includes a second distortion component with respect to an ideal pulse falling waveform. The first distortion component and the second distortion component are substantially line-symmetric with respect to a time axis.

Abstract: An input stage for an A/D converter includes a transconductance element adapted to receive, at a first input of the transconductance element, an analog input signal that is to be converted to a digital signal by the A/D converter, a feedback path for providing an analog feedback signal to a second input of the transconductance element, the analog feedback signal being based on a digital output signal of the A/D converter, and an integrator for integrating an output current of the transconductance element, wherein the integrating element is adapted to generate an integrator output signal representative of the integrated output current. The input stage may be included in an A/D converter. A plurality of such A/D converters may be included in a system.

Abstract: A processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

Abstract: An interleaved digital to analog converter (DAC) includes at least a first signal path and a second signal path. The DAC further includes at least a first high speed DAC and a second high speed DAC each having an input and an output. The first signal path and the second signal path are electrically coupled to the first high speed DAC input and the second high speed DAC input, respectively. The DAC also includes a zero phase clock signal supplied to the first high speed DAC and a 180° phase shifted clock signal supplied to the second high speed DAC. A summation circuit, having at least two inputs and one output, is coupled to the outputs of the first high speed DAC and the second high speed DACs. A high-pass delta sigma modulator, a low-pass delta sigma modulator, a band pass delta sigma modulator, or notch filter delta sigma modulator is coupled between the first signal path and the first high speed DAC.

Abstract: Transport of differential signals is provided. In one aspect, a telecommunications system includes a first unit and a second unit. The first unit can calculate a differential signal from an original signal. The differential signal can represent a change in signal levels between constant time intervals in the original signal. The second unit can estimate the original signal from the differential signal received from the first unit over a communication medium.

Abstract: A modulator and a method are disclosed. The modulator is for generating a band pass signal and comprises: sigma delta modulation logic operable to receive an input signal and to perform at least a 3-level quantisation of the input signal to generate an at least 3-level quantised signal; and requantisation logic operable to requantise the at least 3-level quantised signal to a 2-level quantised signal to be provided as the band pass signal. This approach improves the coding efficiency achieved compared to that possible using a 2-level sigma delta modulator, whilst also providing improved noise performance due to the inherent linearity of the 2-level quantised signal which is provided to drive the switch mode power amplifier. Accordingly, the performance of the modulator is improved by increasing its coding efficiency whilst maintaining its linearity which improves the noise performance in adjacent channels.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: A low-power diversity receiver includes at least two receive paths, each of which is designated as a primary or secondary receive path. A primary receive path is compliant with system requirements (e.g., IS-98D requirements). A secondary receive path is not fully compliant with the system requirements and is designed for lower power, less area, and lower cost than the primary receive path. For a multi-antenna receiver, the two receive paths may be used to simultaneously process two received signals from two antennas. For a single-antenna receiver, either the primary or secondary receive path is selected, e.g., depending on whether or not large amplitude “jammers” are detected, to process a single input signal from one antenna. The receiver may include additional receive paths for additional frequency bands and/or GPS.

Abstract: A delta-sigma modulator and a transmitter apparatus including the same are disclosed. The delta-sigma modulator includes a first integrator, a second integrator, a first comparator configured to compare an output signal of the second integrator and a reference signal, and output a first comparison signal, a second comparator configured to compare the output signal of the second integrator and the reference signal, and output a second comparison signal, a first DAC configured to output the first signal corresponding to the first comparison signal and the second comparison signal, a second DAC configured to output the second signal corresponding to the first comparison signal and the second comparison signal, a delayer configured to generate a delayed signal that delays the first comparison signal and the second comparison signal by a predetermined time, and an output DAC configured to generate an output signal having a multi-level corresponding to the delayed signal.

Abstract: A wireless communication device configured for receiving multiple signals is described. The wireless communication device includes a single-chip carrier aggregation receiver architecture. The single-chip carrier aggregation receiver architecture includes a first antenna, a second antenna, a third antenna, a fourth antenna and a transceiver chip. The transceiver chip includes multiple carrier aggregation receivers. The single-chip carrier aggregation receiver architecture reuses at least one of the carrier aggregation receivers for secondary diversity.

Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

Abstract: To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

Abstract: Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.

Abstract: A method and a circuit are provided for providing phase or frequency synthesis using sigma-delta modulation bit-stream techniques in which data is encoded utilizing sigma-delta modulation and then digital-to-time conversion (DTC) or digital-to-frequency conversion (DFC). In some embodiments this encoded data stream is further subjected to phase or frequency domain filtering, which in some embodiments is carried out by a higher-order phase-locked loop (PLL).

Abstract: Some of the example embodiments presented herein are directed towards an eNodeB (401), and corresponding method therein, for providing data transmission in a multiple antenna system. The eNodeB (401) may be configured to receive a plurality of signal quality assessments and a CSI report from a user equipment. Based on the received data the eNodeB (401) may determine a received power difference between the received data. The eNodeB (401) may further determine a beamforming direction for subsequent data transmissions. Based on the power difference, the eNodeB (401) may account for the received power difference in the subsequent data transmissions, thus improving data communications towards the user equipment.

Abstract: A frequency translating analog-to-digital converter for receiving an analog band-pass signal is described. The analog-to-digital converter comprises an adder/input block for receiving the analog band-pass signal and an analog band-pass feedback signal, thereby forming an analog band-pass error signal. The analog-to-digital converter has at least one analog mixer for mixing and down converting the analog band-pass error signal and thus generating a down-converted analog error signal and at least one quantization path for generating at least one digital signal.

Abstract: A transmitting device includes a parallel data generation unit and a transmitting unit. The parallel data generation unit generates first serial data and second serial data from a data packet, converts the first serial data and second serial data respectively into first parallel data and second parallel data, transmits the first parallel data and second parallel data respectively through first and second parallel transmission paths, and performs the transmission of the first parallel data and the transmission of the second parallel data in parallel. The transmitting unit receives the first parallel data and second parallel data respectively through the first and second parallel transmission paths, re-converts the first parallel data and second parallel data respectively into the first serial data and second serial data, and transmits the first serial data and second serial data to a receiving device respectively through first and second serial transmission paths.

Abstract: A communications system, e.g., a wireless microphone, incorporates a quadrature modulator system to reduce power consumption with respect to traditional approaches and is general in nature to support any two-dimensional digital technique. The quadrature modulator system comprises different subsystems, including a digital-analog transformation circuit, a baseband filter, and a quadrature modulator. The digital-analog transformation circuit converts discrete time samples to a continuous time signal, and further includes an oversampling noise-shaping modulator such as a sigma-delta modulator. The baseband filter then removes out-of-band energy including sampling images and quantization noise. Some of the circuit components may comprise discrete devices that may result in a reduction of power consumption for the quadrature modulator system. Alternatively, some or all of the circuit components may be incorporated in a single electronic device.

Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.

Abstract: An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.

Abstract: Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit.