Abstract: A data processing method is disclosed, and the method includes: receiving, by an encoding end, a to-be-encoded data block; obtaining, by the encoding end, a first mother code element for each first indication element in a first indication sequence based on an association relationship in which S=Q+B*N0 when B>0, and S=Q when B=0; and placing the first mother code element at a location of the first indication element in the first indication sequence to obtain a first mother code sequence.

Abstract: The invention concerns receive circuitry for demodulating an input signal received from a transmission channel, the receive circuitry including a frequency interpolation filter arranged to provide channel estimations (?n) of the entire channel, the frequency interpolation filter having at least one filter receiving the pilot frequency channel estimations and performing filtering based on a plurality (Q) of the pilot channel estimations at a time; and a memory arranged to store the filter coefficients for the at least one filter, the coefficients being based on a frequency-domain autocorrelation of a model of the transmission channel, the model representing the time distribution of the channel power of the transmission channel determined independently of the pilot frequency channel estimations, wherein said model is based on a ?2 distribution.

Abstract: A method and system for combining a guard interval and a corresponding portion of a received symbol, whereby when receiving a signal that contains the symbol with a guard interval corresponding to the symbol, a portion of the guard interval that is free from inter-symbol interference may be extracted, and the extracted portion of the guard interval may be combined with the corresponding portion of the symbol. The extracting and combining may be done after a determining, based on a delay profile provided by the received signal, that a delay spread is smaller than a predetermined channel delay. The delay spread may be determined by filtering an instantaneous delay spread associated with the received signal. The filtering may be performed using a 1-tap infinite impulse response low-pass filter. The low-pass filter may include a time constant that is the inverse of a maximum Doppler frequency shift.

Abstract: An apparatus and method sequentially parses bitstreams based on a removal of an Emulation Prevention Byte (EPB). The apparatus and method may detect an EPB pattern from among sequentially input bitstreams, may store the bitstreams, may store a processed bitstream where the EPB pattern is removed, among the bitstreams, and may select an output of a register buffer based on an input of a buffer selection flag.

Abstract: A method of estimating the Doppler spread of a communication channel includes computing a first sum defined by a difference between the pilot tones of a first group of N symbols and a corresponding pilot tones of a second group of N symbols preceding the first group of N symbols, computing a second sum defined by the pilot tones of the second group of N symbols, and computing a ratio of the first sum and the second sum for each of the N symbols of the first and second group of symbols to generate N ratios representative of the Doppler spread of the channel. The first sum is further defined by the square of the difference between the pilot tones of the first group of N symbols and the corresponding pilot tones of the second group of N symbols.

Abstract: An apparatus and method for transmitting information through a fast feedback channel in a wireless communications system are provided. The apparatus includes a plurality of mappers for mapping a sequence, corresponding to an index to be fed back, to a first set of resource blocks in a fast feedback channel by using a first mapping pattern and to a second set of resource blocks in the fast feedback channel by using a second mapping pattern, and a transmitter for transmitting the sequence mapped to a plurality of sets of resource blocks, wherein the sequence is mapped to each of the plurality of sets of resource blocks, and wherein each element of the sequence is mapped to each resource block.

Abstract: A transmission circuit transmits a header pulse signal which has signal length being equal to or more than twice as long as reference time, pulse period having predetermined ratio thereof to the signal length, and pulse stop period being successive and longer than the reference time via transmission path. The transmission circuit subsequently and successively transmits a plurality of data pulse signals which have signal length being the same as the reference time, pulse period having predetermined ratio thereof to the signal length associated with data, and pulse stop period being located before and after the pulse period via the transmission path. A reception circuit receives pulse signals via the transmission path, detects the header pulse signal based on the pulse stop period of the received pulse signal, and obtains a plurality of pieces of data based on the pulse period of pulse signals following the header pulse signal.

Abstract: In one embodiment, a method executed by at least one processor includes receiving text from submitted by a user. The method also includes determining a text score for the received text by comparing a first set of phrases included in the received text to a second set of phrases. The second set of phrases includes phrases from stored text. The stored text includes stored text known to be genuine and stored text known to be fraudulent. The method also includes determining that the received text is fraudulent based on the text score.

Abstract: The present invention relates to a wireless communication receiver, wireless communication receiving method and television receiver. The wireless communication receiver has signal processing circuits including a first signal processing circuit and a second signal processing circuit, a data storage module, and a deinterleaver. The first signal processing circuit receives a wireless communication signal and then performs a first signal processing to generate a first output data according to the wireless communication signal. The deinterleaver stores the first output data into the data storage module, and retrieves a deinterleaved data corresponding to the first output signal from the data storage module. The second signal processing circuit performs a second signal processing to generate a second output data according to the deinterleaved data.

Abstract: A bandwidth expansion method and apparatus are disclosed, where the method includes: estimating a bandwidth of at least one decoded frame of a whole-band signal, so as to obtain an estimated bandwidth, where the estimated bandwidth corresponds to a whole-band signal that a decoded lower-band signal needs to be extended into; performing first predictive decoding on a part of the lower-band signal in a band above an effective bandwidth of the lower-band signal and below the estimated bandwidth, so as to obtain the part of the lower-band signal above the effective bandwidth of the lower-band signal and below the estimated bandwidth; and performing second predictive decoding on a part of the lower-band signal in a band above the estimated bandwidth, so as to obtain the part of the lower-band signal above the estimated bandwidth.

Abstract: Methods and systems for processing a plurality of pixels, in a video system, are disclosed. Aspects of the method may comprise acquiring scaling factors associated with a plurality of output pixels and generating filter coefficients during the generation of the output pixels. The filter coefficients may be utilized to filter a plurality of pixels to produce the plurality of output pixels. The filter coefficient may be generated on the fly utilizing a windowed sinc function corresponding to the scaling factors. The sine function may be sampled according to the needed number of filter taps to determine the filter coefficients.

Abstract: An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.

Abstract: A multimedia information receiving apparatus receives multimedia information which is transmitted by a broadcast system and receives multimedia information which is simultaneously transmitted by another transmission system such as IP communications, and generates one received information by selecting elements having a few errors from elements of demodulated broadcast system information and elements of demodulated other transmission system information and then arranging the selected elements.

Abstract: Image data is encoded to generate encoded data. An encoding-time buffer period that is a minimum buffer period necessary to prevent synchronous reproduction in which the encoded data is decoded and reproduced in synchronization with a timestamp added to the encoded data from failing due to a delay caused by encoding of the image data is added to the encoded data as encoding header information. A transmission-time buffer period that is a minimum buffer period necessary to prevent the synchronous reproduction from failing due to a delay caused by encoding of the image data and transmission of the encoded data is added to the encoded data as transmission header information different from the encoding header information. The encoded data having the encoding-time buffer period and the transmission-time buffer period added thereto is transmitted to another apparatus that performs the synchronous reproduction via a network.

Abstract: Disclosed are methods and apparatus for sampling rate conversion in a wireless transceiver. The methods and apparatus achieve agile setting of sampling rates or resampling by adaptively setting a sampling rate of a signal based on at least one performance requirement of the transceiver. In particular, the methods and apparatus perform sampling of an input signal at a first sampling rate to gain one or more input signal samples. The input signal samples are then filtered using parallel or polyphase filtering operating at a second sampling rate lower than the first sampling rate. The filtered samples are then interpolated at the second sampling rate to achieve resampling of the input signal. Polyphase filtering affords an effectively high input sampling rate for good spectrum image rejection, while allowing the second sampling rate to be effectively much lower than the first rate, thereby reducing the complexity of multiplier operations for interpolation.

Abstract: The present invention relates to a video decoder (DEC) for decoding a bit stream (BS) corresponding to pictures (P) of a video signal, coded pictures being likely to include macroblocks coded in a progressive and in an interlaced way, said decoder including a decoding unit (DEU) for decoding macroblocks coded in a progressive way. A video decoder according to the invention includes a decoding configuration unit (DCU) for activating said decoding unit several times for decoding a single picture and for configuring the read and/or write stride at each pass of said picture in said decoding unit.

Abstract: An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value.

Abstract: An apparatus and method for transmitting and receiving information through a fast feedback channel in a broadband wireless communications system are provided. The apparatus includes a generator for generating a quasi-orthogonal signal stream corresponding to a codeword to be fed back, a plurality of mappers for mapping the quasi-orthogonal signal stream to a plurality of bundles in the fast feedback channel by using different mapping patterns, and a transmitter for transmitting the quasi-orthogonal signal stream mapped to the plurality of bundles.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

Abstract: Device, system, and method of flicker noise mitigation. For example, an apparatus includes a digital adaptive filter to mitigate flicker noise from a received Orthogonal Frequency-Division Multiplexing (OFDM) signal, wherein the digital adaptive filter includes: a prediction filter to estimate a value of the flicker noise based on linear combination of past low-pass filtered signal samples; a trainer sub-circuit to modify a coefficient of the prediction filter based on a difference between: a known incoming signal filtered by the prediction filter in a training stage, and a locally-generated reference copy of the known signal; a first path including a first pair of analysis-synthesis filters; and a second, parallel, path including a second pair of analysis-synthesis filters and further including the prediction filter.

Abstract: A data transmission apparatus is provided, which is capable of performing good communication with a noncontact data carrier under the circumstances where pulse noise is generated. A noise detection circuit in a reader/writer detects a generation period of noise contained in received signals. A communication time calculating circuit calculates estimated time for communication to be performed for an IC card. A timing signal generation unit determines transmission start timing based on the noise generation period and the estimated communication time.

Abstract: Methods and systems for processing a plurality of pixels, in a video system, are disclosed. Aspects of the method may comprise acquiring scaling factors associated with a plurality of output pixels and generating filter coefficients during the generation of the output pixels. The filter coefficients may be utilized to filter a plurality of pixels to produce the plurality of output pixels. The filter coefficient may be generated on the fly utilizing a windowed sinc function corresponding to the scaling factors. The sinc function may be sampled according to the needed number of filter taps to determine the filter coefficients.

Abstract: A method of generating an output signal comprises receiving an input signal, mixing the input signal with a reference signal having a reference frequency to obtain an intermediate frequency signal having an intermediate frequency, filtering the intermediate frequency signal using a filter having a filter characteristic that is configured according to the intermediate frequency and performing frequency translation on the filtered intermediate frequency signal to obtain the output signal.

Abstract: A coding apparatus capable of reducing a circuit scale and also reducing the amount of coding processing calculation is disclosed. In this apparatus, frequency domain conversion section (103) performs a frequency analysis of the signal sampled at a sampling rate Fx with an analysis length of 2·Na and calculates first spectrum S1(k) (0?k<Na). Band extension section (104) extends the effective frequency band of first spectrum S1(k) to 0?k<Nb so that a new spectrum can be assigned to the extended area following to the frequency k=Na of first spectrum S1(k). Extended spectrum assignment section (105) assigns extended spectrum S1?(k) (Na?k<Nb) input to the extended frequency band from outside. Spectral information specification section (106) outputs information necessary to specify extended spectrum S1?(k) out of the spectrum given from extended spectrum assignment section (105) as a code.

Abstract: At a base station apparatus, known pilot signals for use in channel estimation are transmitted, and in addition thereto MCS pilot signals that are used to perform adaptive modulations respectively corresponding to a plurality of modulation schemes are multiplexed and output. A mobile station apparatus dispreads the respective MCS signals out of the multiplex signal, compares these to known symbols patterns, and sends the MCS pilot signals that show a matching relationship to the base station apparatus as a mobile station reception result. Upon receiving the mobile station reception result from the mobile station apparatus, the base station apparatus selects the modulation scheme of the optimum modulation level for the downlink signals. This configuration makes it possible to switch the modulation schemes in an accurate and simple way.

Abstract: Coded digital data symbols sent from a transmitter through a transmission channel of a communications network are received in a receiver. An estimate, represented by a first number of bits, of a sent data symbol is calculated, and a second number of bits, lower than the first number, is selected from the estimate to achieve a rounded estimate represented by the second number of bits. The rounded estimate is decoded to achieve a decoded data symbol. A target value for a block error rate of the transmission channel is received from the network; and the second number of bits is selected in dependence on the target block error rate value. Thus an optimal rounded estimate is provided in most situations, and the method can be performed with the limited computational resources of a terminal.

Abstract: There is provided a position detecting signal with high accuracy in which a high order distortion error is corrected by the use of a simple processing circuit and method. Two measuring targets which are not illustrated are displaced at a constant velocity, and an analog signals Sa and Sb detected with displacement by the sensor signal detection section are converted into digital data by A/D converter (1). Then, position data ?0 is calculated by position data calculator (2). Next, the position data ?0 is encoded in an error-correction parameter acquiring section (3) and stored in a first memory (4). When a power source is applied, an error-containing position data preparing section (5) decodes by reading out a correction coefficient. An error-correction position table preparing section (6) prepares a decoded data and a correction table of ideal position data and recodes in a second memory (7).

Abstract: A bandpass delta sigma truncator receives a series of first multi-bit digital signals each having a number of data bits, a first number of sign bits and sign extending means for sign extending each of the first multi-bit digital signals to a second multi-bit digital signal having the same number of data bits as the number of data bits in the first multi-bit digital signals, and a second number of sign bits. The truncator outputs from a series of third multi-bit digital signals a series of fourth multi-bit digital signals each having a selected number of the most significant data bits of the third multi-bit digital signals, and a series of fifth multi-bit digital signals each having the remaining number of the least significant data bits of the third multi-bit digital signals.

Abstract: For use in a receiver capable of decoding trellis encoded signals, there is disclosed an apparatus and method for reducing error propagation in a two stage decision feedback equalizer. The apparatus of the invention comprises a first stage equalizer comprising a first forward equalizer filter, a first decision feedback equalization filter, and a trellis decoder. The apparatus of the invention also comprises a second stage equalizer comprising a second forward equalizer filter and a second feedback equalization filter. The two stage decision feedback equalizer is capable of obtaining symbol values from the trellis decoder and using the symbol values as estimates in channel equalization. In one embodiment of the invention, a two stage decision feedback equalizer is provided in which forward filter coefficients remain constant for the duration of D symbols.

Abstract: For use in a receiver capable of decoding trellis encoded signals, there is disclosed an apparatus and method for reducing error propagation in a two stage decision feedback equalizer. The apparatus of the invention comprises a first stage equalizer comprising a first forward equalizer filter, a first decision feedback equalization filter, and a trellis decoder. The apparatus of the invention also comprises a second stage equalizer comprising a second forward equalizer filter and a second feedback equalization filter. The two stage decision feedback equalizer is capable of obtaining symbol values from the trellis decoder and using the symbol values as estimates in channel equalization. In one embodiment of the invention, a two stage decision feedback equalizer is provided in which forward filter coefficients remain constant for the duration of D symbols.

Abstract: A digital encoding system for encoding a series of input bits into a plurality of frequencies, includes an encoder for generating a sampled representation of the frequencies corresponding to an input data sequence comprised of bits, and a decoder. The decoder incorporates a Fourier Transform means for recovering the data stream.

Abstract: A transmitter, receiver, and communication system that utilize a pseudo-random number sequence (PRNS) output unit that provides a PRNS of length N. The PRNS output unit generates the PRNS responsive to a number (s) of prescribed positive integers (qx), a prescribed real impulse constant (r), and a prescribed non-zero real constant (C), where 1<x<s. The PRNS output unit includes an input acceptance section that accepts the number (s) of real number sequence initial values (Yx), and the number (s) of integer parameters (px); and a calculation section that uses the prescribed real impulse constant (r), the prescribed non-zero real constant (C), the real number sequence initial values (Yx), the integer parameters (px), and the prescribed positive integers (qx) to calculate a recurrence formula that is used to generate a PRNS (z′[y]) of length N, and that outputs the PRNS (z′[y]), where 1<y<N.

Abstract: The subtracter performs subtraction processing between a pointer outputted from the pointer register and code words candidate outputted from the code word count storing circuit, and in accordance with whether the result is negative or positive, determines the code words of input data words. Code word candidates stored in the code word count storing circuit are created according to a finite-state transition diagram stored in the state transition storing circuit. An encoder and a decoder are thus made compact and faster.

Abstract: A delta modulation type data converter is adapted to carry out signal processing by sequentially comparing in cycles an inputted signal with a reference voltage set according to the results of previous comparisons and includes a plurality of current sources, switch circuits for setting a current value by appropriately selecting one or more of these current sources, an integrator circuit for generating the reference voltage according to a specified current value, and a control circuit for controlling the switch circuits to make an appropriate selection of these current sources according to the result of a comparison between the reference voltage and the inputted analog signal. The control circuit controls the switch circuits such that, if the result of comparison is the same as in the precious cycle, a selection from the current sources is made such that the current value will be increased, provided such selection is possible.

Abstract: The encode and decode subsystems use a continuously variable slope delta-modulation (CVSD) approach, with either parallel or serial data transfers. To allow for synchronization with a stable data transfer, the entire subsystem uses the main acquisition systems bit rate clock (BRC) as a basis. All other clocks required are simply divided down versions of the BRC and a request pulse from the main system to transfer the data. The delta-modulator is clocked at a rate commensurate with the word placement in the minor frame of the data acquisition cycle; the NRZ-L bits are clocked into serial-to-parallel registers, then latched into the parallel discrete interface (PDI) unit of the main data system. For a serial feed, a similar situation is possible by clocking the data off the circuit board into a serial discrete interface (SDI) unit. The request pulse that activates, the transfer is synchronized with the BRC to ensure a stable transfer. The decoder uses the same CVSD integrated circuit to decode the digital data.

Abstract: A codec uses a number of different signal processing techniques to improve audio compression. These techniques include (1) dynamically varying the size of the processing block to match the duration of the signal over which the audio signal can be considered to be substantially constant, (2) reducing the power gain of the LPC coefficients to reduce leakage of coding noise from one block into the following block, (3) allocating bits to the residual signal in accordance with both objective and subjective criteria, and (4) computing a modified residual signal to take into account the zero input response of the synthesis filters to the reconstruction noise of past blocks.

Abstract: A system is provided on an Integrated Multiport Repeater (IMR) to monitor the activity of the IMR when the repeater is in minimum mode. Through this system the serial output pin outputs status based upon inputs at two input pin the signal in and the clock signal. In a preferred embodiment there are four different status outputs, partition, loopback/link, Bitrate and SQE/Polarity. This system finds use in low end applications where complex control circuitry is not desired.

Abstract: A PLL circuit produces a synchronous signal by utilizing a regenerative clock signal in a VFO portion in a regenerative signal which was read out from a recording medium in sections. When a defective portion is present in a regenerative clock signal, the same sector is read out again from the recording medium to obtain the regenerative signal. A loop gain of the PLL circuit is made to be low in the defective portion of the regenerative signal which was read out again, thereby to prevent the synchronous fault of the PLL circuit due to the defective portion.