Abstract: When a receiver (200) receives a signal transmitted from a transmitter, an A/D converter (204) converts the signal into a digital signal having two or more levels by A/D conversion. A zero-level detector (207) converts the signal into a two-level digital signal of positive and negative levels. The converted signals are subjected to spectrum despreading by correlators (206, 208), respectively. Whichever signal has a higher intensity is selected by absolute value detectors (209, 210), a comparator (211), and a switch (212). A decoder (213) decodes the selected signal. In a receiving state where the zero-level detector (207) is selected, the transmitter transmits the transmission signal after the signal is converted into a two-level signal. In a receiving state where the A/D converter (204) is selected, the transmitter transmits the transmission signal after the signal is converted into a signal having two or more levels.

Abstract: An estimator of the noiseless output of a noisy partial response channel is described. The estimator operates recursively. In each iteration, the estimator processes a window of the N most recently received noisy channel outputs to compare output level metrics for all possible channel output level, and selects a noiseless output level with maximal posterior probability.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A fast block mode determining method for motion estimation, and an apparatus thereof. A cost of motion estimation for an input image frame is predicted by Kalman filtering, and one block mode is selected from a plurality of block modes. A cost for the motion estimation of the input image frame is calculated. The predicted cost and the calculated cost are compared with each other, and the block mode for performing the motion estimation is determined. In an H.264 moving picture encoding device, the operation load is reduced and time wasted for calculation is shortened, because it is not necessary to perform the motion estimation for all the block modes.

Abstract: A device for suppressing pulse interferences contained in a signal, including a circuit for detecting pulse interferences contained in the signal, and a circuit for correcting the signal disturbed by the detected pulse interferences, in which the detection circuit comprises a circuit for determining a first coefficient representative of a statistical feature of the variation of the signal over a first time period; a circuit for determining a second coefficient representative of a statistical feature of the variation of the signal over a second time period longer than the first time period; and a comparison circuit comparing the first and second coefficients and providing a signal indicative of the presence of a pulse interference over the first time period when the first coefficient clearly differs from the second coefficient.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; data stream inputs below the first threshold and above the third threshold are a “0” if both the second and third bits are “1” values, and as a “1” if either of the second and third values is a “1”; data stream inputs above the second threshold and below the third threshold are a “1” if both the second and third bits are a “0” value, and as a “0” if either of the second and third values is a “0”.

Abstract: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.

Abstract: An wireless terminal includes a demodulating unit which comprises an FV (fading vector) estimating unit for receiving a CPICH spread/demodulated signal to output an FV signal with a reduced noise ratio; a phase synchronization unit for multiplying a PDSCH spread/demodulated signal with a complex conjugate of the FV signal to correct the phase offset of the PDSCH I and Q signals to send the resulting PDSCH I and Q signals to a multi-level QAM amplitude synchronization detection unit and to an amplitude demodulating unit; a first-quadrant transformation unit for collecting the second to fourth quadrant signals of the phase-synchronized PDSCH I and Q signals; and a threshold value detecting unit for calculating a multi-level QAM threshold value from the first quadrant signals and the FV signals to send the threshold signal to an amplitude demodulating unit. The amplitude demodulating unit effects amplitude demodulation to output multi-level QAM demodulated signals.

Abstract: A demodulator recovers a transmitted symbol represented by a received quadrature amplitude modulation (QAM) signal. Such a demodulator may include: a QAM-decoding block operable to map a received signal vector onto a constellation so as to yield a first symbol, and identify a next-most probable second symbol based upon the signal vector; and a selection unit operable to select, among the first and second symbols, the one having the lower error content as corresponding to the transmitted symbol. A corresponding method may include similar steps.

Abstract: A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”).

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Abstract: A transmission line equalizer, communication system, and method are provided for adaptively compensating for changes in transmission path length and transmission path medium. Within the equalizer is a filter that exhibits a high pass characteristic and, more specifically, has an inverse frequency response to that of the transmission path. The inverse filter can include a pair of amplifier stages coupled in parallel, with a mixer chosen to adaptively select portions of one stage over than of the other. The dual stage inverse filter can, therefore, adapt to greater transmission path lengths and/or attenuation. A feedback architecture is used to set the inverse filter response by measuring the amplitude of a communication signal output from the inverse filter during periods of low frequency. A peak detector will capture a peak-to-peak voltage value during those periods, and adjust the output of the slicer to match a launch amplitude of the communication signal.

Abstract: A polarity independent differential data transceiver receives a differential voltage signal and outputs a first logic state when the differential voltage signal is in a positive voltage differential range and/or when the differential voltage signal is in a corresponding negative differential voltage range. The differential data transceiver will output a second logic state in response to receiving a voltage differential signal that is in an intermediate differential voltage range near zero between the positive differential voltage range and the corresponding negative differential voltage range.

Abstract: A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”).

Abstract: A driver circuit is coupled to an optical waveguide transmitter. The driver circuit has a current generator that is in series with the transmitter, and a current robbing circuit is coupled to the transmitter. The current robbing circuit is to divert first and second amounts of current from the transmitter, in accordance with predetermined values of first and second bit streams, respectively, in which data is received to be transmitted. Other embodiments are also described and claimed.

Abstract: A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data “eye” samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data “eye” samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.

Abstract: Transmitting a transition between high and low states across a lengthy conductor with a main transmitter to transmit data, providing emphasis with an emphasis transmitter to strengthen the transmission of the transition, transmitting a low-to-high transition to test for the absence of an electronic device coupled to the lengthy conductor, and detecting an occurrence of an overvoltage level indicating the absence of such an electronic device.

Abstract: To be capable of receiving many data without increasing a transfer speed. A wave detector detects a radio signal RF received by an antenna. The radio signal RF received by the antenna has been subjected to ASK modulation, for example, and by getting it through a lowpass filter or the like, an envelope (multilevel signal) that is a basis of received data D0, D1 is obtained. An amplitude detector detects the maximum value and the minimum value of the amplitude of the multilevel signal. A threshold calculator calculates a plurality of thresholds to be used for determining whether the multilevel signal is H state or L state, from the maximum value and the minimum value detected by the amplitude detector. A multilevel restoration unit compares the multilevel signal with each of the thresholds to detect the H state and the L state, and reconstructs a plurality of received data D0 to Dn.

Abstract: The invention relates to a method for demodulating information emitted by amplitude modulation by a reader (2) to a transponder (4) comprising: a step to compare variations of a slaving voltage (Vc) of the transponder (4) with threshold values, and to transform the result of this comparison into an authorized modulation level skip value, a step to add this skip to a previous first modulation level to determine a second modulation level.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: The present invention relates to an apparatus and method for detecting a data rate in a turbo decoder for a mobile communication system. When a rate selector selects one data rate among a plurality of data rates, a turbo decoder repeatedly decodes an input data frame within a predetermined repetition limit number using the selected data rate and outputs the decoded data. A CRC detector performs CRC check on the decoded data and outputs the CRC check result, and a decoding state measurer measures decoding quality depending on the decoded data and outputs decoding state information. A controller then sets the repetition limit number to a predetermined minimum value, controls the repetition limit number according to the decoding state information, controls the rate selector and determines a data rate of the input data depending on the CRC check result.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: A receiver for high bitrate binary signals contains a soft decision circuit with three parallel deciders coupled to a 2:1 multiplexer. The three deciders have different threshold values and generate four potential states. The 2:1 multiplexer translates the four different states into a restored data signal and a reliability signal indicating the decision reliability.

Abstract: For use in a CDMA receiver having a Viterbi decoder, a system for, and method of, performing one-pass blind transport format detection (BTFD) with respect to a received frame and a WCDMA receiver incorporating the system or the method. In one embodiment, the system includes: (1) a traceback circuit that performs a zero state BTFD traceback function with respect to at least a Viterbi-decoded portion of the frame, the traceback function being dependent upon a relative position of a BTFD checkpoint and generating hard decision bits and (2) a BTFD point selection circuit, coupled to the traceback circuit, that employs the hard decision bits to determine a location of a BTFD point with respect to the frame.

Abstract: A system and method are provided for five-level non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing a five-level threshold; comparing the first bit estimate to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; and, in response to the comparisons, determining the value of the first bit. Establishing a five-level threshold includes: establishing thresholds to distinguish a first bit value when the second and third bit values are a “1” value, when the second bit value is a “1” and the third bit value is a “0”, when the second bit value is a “0” and the third bit value is a “1”, when the second and third bit values are a “0” value, and an approximate midway threshold.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: A clock reproduction circuit receives a multi-valued input data signal to generate a reproduced clock signal with a higher accuracy. The clock reproduction circuit includes a data judgement block which judges whether or not three consecutive data are such that a first-order data is equal to a third-order data and is not equal to a second-order data, and a phase-locked-loop (PLL) which controls or does not control the phase of the reproduced clock depending on the judgement result by the data judgement block.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs an automatic slicer level adaption to enhance the performance of a high speed communications system.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: The multilevel data encoding and modulation technique uses a pair of complementary logic sets. In its most basic form, the sets are binary sets each containing a line level for a logical one and a line level for a logical zero for a total of four logic levels. The encoding technique requires a polar change in the line level after every bit. An optional fifth level may be used in order to skew the frequency or to enable automatic gain control circuitry to ensure consistent level discrimination. The encoding technique may be used in a bipolar device, or a bias level may be applied to the signal for unipolar transmission. The encoding technique involves inverting the polarity of alternating bits, filtering out all odd harmonics, transmitting and receiving the waveform, and decoding the demodulated waveform by comparing the absolute value of the half-cycle peak-to-peak voltage gain to a predetermined table.

Abstract: Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pNRZ) signal that can drive a conventional OOK clock recovery (CR) IC. The TD circuit can convert the edges of the ML signal into the pseudo-NRZ (pNRZ) signal. The TD circuit can capture as many transitions as possible to allow the conventional NRZ clock recovery (CR) chip to optimally perform. The TD circuit can differentiate the ML signal in order to detect the ML signal's transitions.

Abstract: An improved decoding technique useful for hard decision decoding, such as quadrature phase shift keying (PSK) and quadrature amplitude modulation (QAM), as well as soft-decision techniques, such as Viterbi decoding and trellis decoding. The system in accordance with the present invention provides adaptive decision regions for hard-decision decoding techniques and adaptive metrics for soft-decision detection techniques in which the decision boundaries and reference constellations, respectively are optimized in order to minimize the bit error rate (BER). In particular, the decision boundaries and metrics are optimized based on the locations of the received constellation points.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: An amplitude modulated optical communication system and method are disclosed that achieve bandwidth compression by making use of an n level amplitude modulation scheme in one or more frequency bands. A soft decision decoder is disclosed that provides at least two soft slicing levels between each signal level in the multiple level transmission scheme to define an “uncertainty” region therebetween. The soft slicing levels are used to evaluate the reliability of a given bit assignment. In addition to assigning a digital value based on the received signal level, one or more soft bits are assigned indicating a “reliability” measure of the output code.

Abstract: A system and method are provided for five-level non-casual channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing a five-level threshold; comparing the first bit estimate to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; and, in response to the comparisons, determining the value of the first bit. Establishing a five-level threshold includes: establishing thresholds to distinguish a first bit value when the second and third bit values are a “1” value, when the second bit value is a “1” and the third bit value is a “0”, when the second bit value is a “0” and the third bit value is a “1”, when the second and third bit values are a “0” value, and an approximate midway threshold.

Abstract: The present invention provides an apparatus, system and method of peak-to-average reduction of an oversampled signal for a digital communication system. Peak detection 504 and width measurement 504 are advantageously combined in which a peak portion or multiple peak portions of an input signal that exceeds a predetermined threshold is detected and a width of the peak portion is determined. The peak detection and width measurement are further combined with a novel variable width shape generation methodology 506 in which a variable width shaping response is applied 510 to the peak portion responsive to the peak portion width. Additionally, a novel receiver technique 1390 can be included to reduce or eliminate the upstream BER impact using downstream oversampled shaping.

Abstract: Binary information is subjected to RZ encoding and multi-level encoding, and the encoded signal is optically modulated.

Abstract: Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test data, and the test data is produced at a single output on edges of a clock signal.

Abstract: A method of decoding a signal in an optical fiber. In one embodiment the method includes receiving the optical signal, wherein the optical signal is a pulse amplitude modulated signal. Converting the optical signal to an electrical signal. Comparing the electrical signal with a plurality of levels. Producing comparison output signals based on the comparison of the electrical signal with the plurality of levels. Processing the comparison output signals on a clock to produce processed output signals and latching the processed output signals on a clock signal to generate the plurality of serial, digital data streams.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

Abstract: An adaptive bias module architecture and related methods is presented. According to one embodiment, for example, a method is presented comprising detecting a power level associated with data received by a transmit driver for transmission into an inductive load without analyzing the data content, and adapting a bias level applied to the transmit driver to facilitate transmission of the received data based, at least in part, on the detected power level.

Abstract: Digital signals from a group of three or more circuits (104, 105, 106) are used to create an encoded or combined signal on a common transmission line (108). The encoded signal is then decoded at each different circuit to produce or recreate the digital signal asserted by each different circuit in the group. The encoded signal comprises a signal included in a set of unique signal values, with each signal in the set corresponding to a different combination of digital signals asserted by the group of circuits. Decoding the encoded signal at each circuit (104, 105, 106) in the group involves comparing the encoded signal to a particular reference voltage from a set of reference voltages. A particular reference voltage used in this comparison may be selected using one or more digital signals already decoded from the encoded signal.

Abstract: Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase.

Abstract: The present invention is a decoder for decoding a signal. The decoder includes a discriminator and a threshold generator. The discriminator receives the signal and generates an output voltage equal to a first voltage if the signal is less than a threshold level that is input to the discriminator and equal to a second voltage if the signal is greater than the threshold level. The threshold level depends on the output from the discriminator in a preceding time interval that depends on the impulse response of a transmission link through which the input signal has passed. The threshold generator implements a low-pass analog filter that receives the output voltage during each of the clock periods and generates therefrom a filtered output signal.

Abstract: A method of encoding a plural-bit data word as a plurality of multi-level symbols, where each of the plurality of multi-level symbols has a value selected from a predetermined plurality of levels. The method includes first translating each one of the selected bit positions of the plural-bit data word to one of the levels. When the contents of a predetermined one of the bits of the data word is a predetermined value, the method provides a second translation of each of the selected bit positions of the plural-bit data word to one of the levels. The method further includes generating a plural-bit offset word from predetermined bit positions of the data word and generating the multi-level symbols by addition of the offset word to the translated levels. One embodiment of the invention provides that the multi-level symbols are assigned a five-level code and the codes are treated as twos-complement numbers.