Abstract: Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

Abstract: System, methods and apparatus are described that provide an N-factorial (N!) voltage-mode driver. A method communicating on an N! interface includes encoding data in a symbol to be transmitted over the N wires of the interface, and for each wire of the N wires, calculating a resultant current for the wire by summing current flows defined for two or more two-wire combinations that include the wire, and coupling a switchable voltage source to the each wire. Each bit in the symbol defines a current flow between a pair of the N wires that is one of a plurality of possible two-wire combinations of the N wires. The switchable voltage source may be selected from a plurality of switchable voltage sources in order to provide a current in the each wire that is proportionate to the resultant current calculated for the each wire.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A method of high-integrity data transmission including transmitting nominally-identical data via first and second channels, inverting the logic of the data in the second channel receiving the data via a respective data handling device for each channel, inverting the logic of data outputted by one of the data-handling devices and comparing the so-inverted data with data outputted by the other data handling device. The invention is relevant to the avoidance of common-mode failures in aircraft, other vehicles and plant employing high-integrity data systems.

Abstract: A duobinary voltage-mode transmitter comprises a first branch including a first logic circuit and a first driver, and a second branch including a second logic circuit and a second driver. When a transition occurs between NRZ signals, two ends of a first match circuit are electrically coupled between the output nodes of the first driver and the second driver, respectively, and the first driver and the second driver are turned off.

Abstract: A connection apparatus circuit includes an isolation transformer, an impedance matching network, a high-voltage capacitor and a first high-voltage surge protector. The isolation transformer has a first coil and a second coil, wherein the first coil has a first terminal, a second terminal and a center tap. The impedance matching network is coupled between the center tap and a relay terminal. The high-voltage capacitor is coupled between the relay terminal and a ground terminal. The first high-voltage surge protector is coupled between the relay terminal and the ground terminal. When a high-voltage surge exceeds a default value between the first terminal or the second terminal and the ground terminal, the first high-voltage surge protector is conducted to clamp current on the impedance matching network.

Abstract: System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.

Abstract: The present invention provides, in one embodiment, a method of transmitting a message. The method includes transmitting a first codeword from a transmitter to a relay. The method also includes subsequently transmitting a second codeword based on the first codeword from the relay and a third codeword from the transmitter wherein the second and third codewords are transmitted concurrently.

Abstract: This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol providing multiple frame formats to achieve delivery of one type of message with a reduced latency and other messages at increased latencies. Further, although the master initiates reads, the slave circuit may signal the master in real time over the TSI.

Abstract: An optical communication system, a transmitter, a receiver, and methods of operating the same are provided. In particular, a transmitter is disclosed as being configured to encode optical signals in accordance with a multi-level coding scheme. The receiver is configured to provide receive and decode to the optical signals received from the transmitter. One or both of the receiver and transmitter are configured to compensate for non-idealities or non-linearities introduced into the communication system by optical components of the system.

Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.

Abstract: The present invention provides a communication circuit, a communication network, and a connecting apparatus that can realize communication with very high reliability using a simple wiring system, that includes a communication line 2 comprising three or more signal lines 2a,2b,2c, a signal distributing section 4, that is connected to one end of the communication line 2, for distributing and transmitting a signal input into an input terminal 3i to respective signal lines 2a,2b,2c, and a majority selection receiving circuit 5, that is connected to the other end of the communication line 2, for comparing a plurality of reception signals received via the signal lines 2a,2b,2c and selecting reception signals which are most matched with one another as true so as to output them to an output terminal 30.

Abstract: The invention relates to the asynchronous communication of data in complex integrated systems, be it inside integrated circuit chips or between integrated circuit chips, for example in a compact stack of chips. According to the invention, the transmission is done on a single conductor of exchanges. The data are transmitted on this conductor in the form of at least three levels of potential, the first level representing a first value of data item transmitted, the second representing a second value of data item transmitted, and the third representing an inactive level. An acknowledgment signal is transmitted on the same exchange conductor as the data. This signal is preferably sent by the receiver in the form of the forcing of the exchange conductor by the receiver to the inactive potential level, the sender detecting this forcing.

Abstract: A system for communicating data comprises a clock channel configured to transmit a clock signal at a predetermined rate and at least one data channel configured to transmit data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate. Each block of multi-level symbols comprises a sequence of at least three multi-level symbols. Each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two. The fixed multiple of the clock rate is an integer greater than one.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract: A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines.

Abstract: An apparatus is disclosed where a Powerline interface is used to transmit data into the powerline grid network, where the powerline interface is pulling the required transmit energy from the power grid network, where the powerline interface is transmitting data using standard narrow band modulation such as ASK, FSK, S-FSK, where the transmitted data are passed on to the powerline interface by the use of an “Input signal” adapation stage, where an error calculation and a comparison to a “Triangle” signal is performed to create a command signal used to enable the transmission of data by providing enough voltage to polarize the Transistor (i.e: MOS FET) used in the powerline path.

Abstract: In one or more embodiments, a circuit is configured to receive a differential signal from a transmitter that is isolated from the receiver circuit and that includes a common-mode suppression circuit and signal combining circuit coupled to the corresponding lines carrying the differential signals. The common-mode suppression and signal combining circuits are configured to suppress common-mode signals of differential signals communicated on the set of differential signal lines and combine to form of differential-mode components of the differential signals.

Abstract: A combination noise-filter, surge protections circuit and HDMI communication device. HDMI specific noise filters, surge protection circuits, PLC modem and encoding/decoding apparatus are connect to, or integrated into, power outlets in a home or other wired building enabling a high bandwidth powerline communication network.

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plurality of components, some of which are quiescent components and some of which are non-quiescent components, wherein the number of quiescent components and non-quiescent components meet a sparseness requirement.

Abstract: There is provided an information processing apparatus, including a signal receiver that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value, wherein the first bit value is represented by first amplitude values, the second value is represented by a second amplitude value, and polarity of the encoded signal amplitude value is reversed in each period, a conversion processor performs conversion to add a delayed signal that is delayed by delaying a signal received by the signal receiver by one period of the received signal, an inversion processor that performs inverse processing of the conversion on the signal output from the conversion processor, and an input data decoder that decodes an input data by determining the first and second values based on the amplitude value of the signal output from the inversion processor.

Abstract: There is provided an information processing apparatus, including a signal receiving unit that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value that are mutually different, wherein the first bit value is represented by a plurality of first amplitude values, the second bit value is represented by a second amplitude value that is different from the first amplitude values, a same amplitude value is not taken successively, and polarity of the amplitude value is reversed in each period, an amplitude square unit that squares an amplitude of the signal received by the signal receiving unit, and an input data decoding unit that decodes an input data by determining the first and second bit values based on the amplitude value of the signal output from the amplitude square unit.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.

Abstract: In one or more embodiments, a system is provided for communicating between different voltage domains using N+1 capacitive-coupled conductive lines to provide N communication channels. For instance, bi-directional communication (e.g., a first communication in a first direction and a second communication path in the opposite direction) may be provided using three capacitive-coupled signal paths. Two of the signal paths are used as single-ended (i.e., non-differential) signal paths. The third signal path is used to suppress voltage disturbances between two voltage domains.

Abstract: A data transmission system comprises: a pair of transmission lines connecting a plurality of apparatuses; a bridge termination resistor connected between the transmission lines and having a resistance value matching a differential impedance of the transmission lines; a first switch connecting the bridge termination resistor to the transmission lines when being turned on, and disconnecting the bridge termination resistor from the transmission lines when being turned off; pull-up/down resistors connected between the transmission lines and a fixed voltage node, and having resistance values respectively matching characteristic impedances of the transmission lines, the fixed voltage node being a power supply or a ground; and second switches connecting the pull-up/down resistors between the transmission lines and the fixed voltage node when being turned on, and disconnecting the pull-up/down resistors from the transmission lines when being turned off.

Abstract: A method for searching for an input symbol string, includes receiving (B) an input symbol string, proceeding (C) in a trie data structure to a calculation point indicated by the next symbol, calculating (D) distances at the calculation point, selecting (E) repeatedly the next branch to follow (C) to the next calculation point to repeat the calculation (D). After the calculation (G), selecting the symbol string having the shortest distance to the input symbol string on the basis of the performed calculations. To minimize the number of calculations, not only the distances are calculated (D) at the calculation points, but also the smallest possible length difference corresponding to each distance, and on the basis of each distance and corresponding length difference a reference value is calculated, and the branch is selected (E) in such a manner that next the routine proceeds from the calculation point producing the lowest reference value.

Abstract: Disclosed herein is a power line channel-adaptive communications system and method. The power line channel-adaptive communications system includes a transmitting end, a channel-adaptive controller, and a receiving end. The transmitting end generates an adaptive chirp symbol signal of a preset type for transmission data according to a channel state of the power line, modulates the generated adaptive chirp symbol signal in any one of first and second transmission modes, and transmits the modulated adaptive chirp symbol signal via the power line channel. The channel-adaptive controller controls the type and transmission mode of the adaptive chirp symbol signal. The receiving end restores the transmission data by demodulating the adaptive chirp symbol signal, received via the power line channel, in any one of the first and second transmission modes according to the channel state of the power line.

Abstract: A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines.

Abstract: Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A method for detecting signals in a TMDS transmission system having a channel established between a receiver and a transmitter includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference.

Abstract: A communication circuit is provided which transmits an information bit string from a transmission unit to a reception unit. The transmission unit includes a first modulation circuit that modulates a first carrier wave by a start bit to generate a first frequency signal, a second modulation circuit that modulates a second carrier wave by the information bit string to generate a second frequency signal, and a transmission circuit that transmits the first and second frequency signals from a transmitting antenna. The reception unit includes a reception circuit that receives a signal from the transmission unit, a first detector circuit that detects a signal of the first carrier wave to demodulate the start bit, a second detector circuit that detects a signal of the second carrier wave to demodulate the information bit string, and a detection circuit that is synchronized by the start bit and reads the information bit string.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract: The invention relates to information transmission methods, in particular to the communication interfaces of electronic devices. The inventive method makes it possible to increase the communication range and reliability by improving noise protection through the compensation of a noise signal during the transmission and reading of the signal in both wires of a communication line. The inventive method involves connecting the first pole of a voltage supply source to the first wire of a two-wire transmission line via a first resistor and connecting the second pole of said voltage supply source to the second wire of the two-wire transmission line via a second resistor. Moreover, the first and second resistors have the equal resistance values, and a receiver is connected to the two-wire transmission line between a transmitter and the voltage supply source and is provided with two current sensors. A reading signal is defined as the sum of absolute values of the measured currents.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

Abstract: A powerline communications device comprises a powerline communications interface and at least one other communications interface configured to communicate over a computing network. The powerline communications interface is further configured to receive electrical power. The computing network may comprise mediums including powerlines, telephone lines, and/or coaxial cables. In some embodiments, the powerline communications interface may communicate with a network apparatus, such as a personal computer, via an Ethernet interface. The powerline interface, the telephone line interface, and/or the coaxial cable interface may all be associated with the same media access control (MAC) address. The powerline communications device may receive a message via a first medium and repeat the message via a second medium based on a quality of service (QoS) metric. In some embodiments, the powerline communications device may communicate using multiple frequency bands.

Abstract: A DC-balanced signal is imposed on the input of a transmission line. Prior to imposing the DC-balanced signal, the input of the transmission line is held at an intermediate DC level that intermediate between the maximum and minimum DC levels of the DC-balanced signal. Alternatively, a compensating pulse is additionally imposed on the input of the transmission line. The compensating pulse compensates for a change in the DC level at the output of the transmission line caused by the imposing of the DC-balanced signal on the input of the transmission line.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A power line communication apparatus controls a transmission using a plurality of parameters. The power line communication apparatus includes: a registration processor which performs a registration process for achieving a state to be communicable with another power line communication apparatus through a power line by use of transmission data based on a first parameter set at a first value and a second parameter set at a second value, a parameter controller which changes the first parameter to the third value to lengthen a communicable distance and the second parameter to the fourth value to shorten the communicable distance when the registration process has ended in failure. When the registration process has ended in failure, the registration processor retry the registration process by use of transmission data based on the first parameter set at a third value and the second parameter set at a fourth value.

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract: A method and device are provided for producing a transmission signal to be transferred over a transmission path from an input signal, for example an xDSL signal, wherein a bandwidth of the input signal is distributed onto a plurality of frequency bands in such a way that part signals are obtained corresponding to the individual frequency bands, and wherein each part signal is conducted to separate line drivers, and wherein output signals of the individual line drivers are combined to form the transmission signal to be transferred over the transmission path by combination means, which can be designed as an adder. In order to obtain the frequency band which pertains in each case from the input signal, which can be transformed into an analogue signal with a D/A converter, filter means can be used.

Abstract: A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines.

Abstract: A network transmitting apparatus and a power saving method thereof are provided. The network transmitting apparatus includes a chip, a transformer, and a power regulating unit. The chip includes a detecting and controlling unit, an analog circuit, and a digital circuit. The detecting and controlling unit receives a received signal and detects the received signal and a state of the chip to generate a first control signal. The transformer has a first side coupled to the chip and a second side. The power regulating unit coupled to the detecting and controlling unit and a center tap of the first side of the transformer is used for receiving a voltage, generating a first regulated voltage according to the first control signal, and connecting the first regulated voltage to the center tap of the first side of the transformer, the analog circuit, and the digital circuit.

Abstract: In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the same amplitude value not occurring consecutively and the amplitude value polarity being inverted with each cycle. Within a transmission time segment for a second information processing module, the first information processing module transmits a clock signal that corresponds to the cycle at which the polarity is inverted.

Abstract: An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.