Abstract: Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: Use of a training sequence having terms that are orthogonal to each other are employed to considerably speed up execution of the LMS algorithm. Such orthogonal sequences are developed for a channel that is described as a finite impulse response (FIR) filter having a length Mnew from the already existing orthogonal training sequences for at least two channels that have respective lengths Mold1 and Mold2 each that is less than Mnew such that the product of Mold1 and Mold2 is equal to Mnew when Mold1 and Mo1d2 have no common prime number factor. More specifically, a set of initial existing orthogonal training sequences is found, e.g., using those that were known in the prior art or by performing a computer search over known symbol constellations given a channel of length M.

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: A system for communicating data comprises a clock channel configured to transmit a clock signal at a predetermined rate and at least one data channel configured to transmit data as a sequence of blocks of multi-level symbols being sent at a fixed multiple of the clock rate. Each block of multi-level symbols comprises a sequence of at least three multi-level symbols. Each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an integer greater than two. The fixed multiple of the clock rate is an integer greater than one.

Abstract: An integrated circuit containing a communication channel is described. This communication channel includes a transmit circuit configured to transmit signals using a voltage-mode driver, a receive circuit, and a capacitive link that couples the transmit circuit to the receive circuit. The communication channel includes a filter with a capacitive-summing junction to equalize signals communicated between the transmit circuit and the receive circuit.

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.

Abstract: Digital video data is transmitted from a video source (61) to a video sink (62) as a group of three multilevel symbols (611, 612, and 613) per pixel color with each associated symbol being sent at a rate of three times the pixel clock (601). When eleven levels are used per symbol (611) and undesirable symbol groups having excess DC residual or minimal energy are eliminated, and a built-in-test symbol group is added for pixel alignment; there results a one-to-one correspondence between the remaining symbol groups available and the two-hundred and sixty possible states that are used in the TMDS physical layer that is in widespread commercial use.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: Transmitting a waveform over a shared medium from a first station to at least one second station comprises: forming a first portion of the waveform comprising a symbol having a predetermined symbol length, the symbol comprising a first set of frequency components at predetermined carrier frequencies modulated with preamble information stored in the second station and a second set of frequency components at predetermined carrier frequencies modulated with information to be communicated to the second station, with the carrier frequencies of the first and second sets of frequency components being integral multiples of a frequency interval determined by the inverse of the symbol length; forming a second portion of the waveform, the second portion of the waveform comprising an segment that is correlated with at least an initial segment of the first portion of the waveform; and transmitting the waveform including the second portion followed in time by the first portion over the shared medium.

Abstract: A data communication system, comprising at least three signal conductors and a first and a second power supply terminal, for supplying currents of mutually opposite direction to the signal conductors respectively. A driver circuit establishes respective combinations of currents through the signal conductors from a selectable set of combinations, which includes combinations with currents from the first supply terminal and to the second supply terminal, so that a sum of the currents through the signal conductors substantially has a same value for each combination and at least one of the conductors in operation does not merely function in a differential-pair relation with another one of the conductors, the driver circuit determining which of the combinations from the set are established depending on information to be transmitted.

Abstract: A transmission circuit (101) for transmitting data onto a transmission line, and a mask circuit (102) for generating a mask signal (105) for removing a reflected wave based on a transmission timing notification signal (104) supplied form the transmission circuit (101) are provided. For example, a timer circuit (301) causes the mask signal (105) to be effective only for a predetermined time immediately after transmission. A logic circuit (302) is used to remove a reflected wave from the received signal (106) based on the mask signal (105), and a resultant masked received signal (107) is input to a reception circuit (103).

Abstract: An encoding apparatus that converts input digital data and an input clock into three-bit six-state transition encode outputs and outputs them is disclosed. The encoding apparatus has a first state transition control section, second state transition control section, and an output selection section. The first state transition control section changes a state of first data at a positive edge of the input clock. The second state transition control section changes a state of second data at a negative edge of the input clock. The output selection section alternately selects the state of the first state transition control section and the second state transition control section.

Abstract: A novel data transmission method and apparatus is disclosed for communicating digital data using existing telephone wiring. According to the present invention, the digital data is represented by the time interval between two consecutive biphasic pulses. Biphasic pulses are used in the present invention because each biphasic pulse does not carry any dc component so DC component in the transmission line can be eliminated. In addition, additional data can be encoded in the amplitude or pulse width of each biphasic pulse so that higher data encoding ratio can be achieved.

Abstract: An integrated connecting device for coupling a communication link to a powered device (PD) in a system for supplying power to the PD over the communication link. The integrated connecting device has a housing configured for providing connection to the PD external with respect to the housing, communication interface circuitry coupled to the communication link for supporting data communication of the PD over the communication link, and power interface circuitry coupled to the communication interface circuitry for implementing a power supply protocol performed to supply power to the PD over the communication link. The communication interface circuitry and the power interface circuitry being held by the housing.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A novel system and methodology for supplying power over a communication cable, such as an Ethernet cable, using power distribution circuitry for controlling power distribution between wires or pairs of wires in the communication cable. The power distribution circuitry may control distribution of current among wires or pairs of wires in the communication cable. In particular, balance of current among the wires or pairs of wires may be provided.

Abstract: In one aspect, a differential signal transfer method is provided which includes converting 2M?1 original signals into 2M?1 differential signal pairs, where M is an integer of 2 or more, and wherein each pair consists of a first differential signal and a second differential signal having opposite phases, and transferring the 2M?1 differential signal pairs to 2M signal lines such that each of the 2M signal lines includes overlapping differential signals among the first differential signals and the second differential signals of the 2M?1 differential signal pairs.

Abstract: The present invention provides a data transfer system including a data transmitter and a data receiver. The data transmitter converts a plurality of bits of transmission parallel data into serial data and generates a multi-level logic signal representing a plurality of bits of information in one symbol, the information being obtained by combining the serial data with a word clock as one-bit information. The word clock indicates a word delimiter in the serial data. The data receiver receives the transmitted multi-level logic signal, extracts the serial data and the word clock from the signal, and reproduces the parallel data based on the extracted word clock. In the data transfer system, a multi-bit digital signal can be transmitted as one signal including a word clock. Thus, components and mounting space to be allocated to transfer can be reduced.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: A communication system includes a first device and a second device connected to the first device by a single communication line. The first device includes a first transmitting portion which transmits to the second device a pulse signal set to a predetermined cycle that differs according to data, and a first receiving portion which reads data transmitted from the second device based on a voltage value of a transmission signal transmitted over the communication line. The second device includes a second transmitting portion which transmits to the first device a voltage signal set to a predetermined voltage value that differs according to the data, and a second receiving portion which reads data transmitted from the first device based on a pulse signal cycle of the transmission signal transmitted over the communication line.

Abstract: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit(s) input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Abstract: A system and method for transferring data between a transmitter and a receiver over a single conductor is disclosed. During a data transfer operation of bit of information, the voltage level on the conductor is changed from a first voltage level to a second voltage level and maintained at the second voltage level for a predetermined duration of time. The predetermined duration of time is determined by the logical state of the data bit being transmitted. Upon expiration of the predetermined duration of time the voltage level on the conductor is driven back to substantially the first voltage level.

Abstract: An apparatus for transmitting data signals includes a logic unit configured to generate an encoded clock signal in response to a clock signal and a first data signal, and a demultiplexer configured to receive the encoded signal, the first data signal, and a second data signal, and to output odd-numbered data signals of the received signals at a first edge of the clock signal and even-numbered data signals of the received signals at a second edge of the clock signal. A data state elimination block is configured to receive the signals and to invert one of the received signals if logic levels of the signals are the same.

Abstract: There is provided an information processing apparatus, including a signal receiving unit that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value that are mutually different, wherein the first bit value is represented by a plurality of first amplitude values, the second bit value is represented by a second amplitude value that is different from the first amplitude values, a same amplitude value is not taken successively, and polarity of the amplitude value is reversed in each period, an amplitude square unit that squares an amplitude of the signal received by the signal receiving unit, and an input data decoding unit that decodes an input data by determining the first and second bit values based on the amplitude value of the signal output from the amplitude square unit.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and, logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: An apparatus for reducing modem command and status latency within a direct access arrangement (DAA) circuit is disclosed. The DAA circuit includes a serial audio interface for providing communications between the DAA circuit and the host computer system. The serial audio interface can operate under multiple serial communication interface standards, such as the AC '97 standard and the HD Audio standard. The DAA circuit also includes means for configuring the serial audio interface to transmit and receive modem samples at an audio sample rate higher than a modem sample rate of the modem samples and at a predetermined bit size that is wider than a bit size of the modem samples. The additional bits other than the modem samples are utilized to indicate command and status information associated with the DAA circuit or a telephone line such that modem command and status latency on the serial audio interface within the DAA circuit can be reduced.

Abstract: A digital multimedia broadcasting (DMB) reception apparatus receives DMB service in a mobile communication system. In the DMB reception apparatus, a Reed-Solomon (R-S) decoder receives a coded broadcast signal and outputs an error symbol with a transport error indicator bit, if all data bits in the symbol are ‘0’. A moving picture experts group (MPEG) decoder discards the error symbol.

Abstract: A transmission line equalizer, communication system, and method are provided for adaptively compensating for changes in transmission path length and transmission path medium. Within the equalizer is a filter that exhibits a high pass characteristic and, more specifically, has an inverse frequency response to that of the transmission path. The inverse filter can include a pair of amplifier stages coupled in parallel, with a mixer chosen to adaptively select portions of one stage over than of the other. The dual stage inverse filter can, therefore, adapt to greater transmission path lengths and/or attenuation. A feedback architecture is used to set the inverse filter response by measuring the amplitude of a communication signal output from the inverse filter during periods of low frequency. A peak detector will capture a peak-to-peak voltage value during those periods, and adjust the output of the slicer to match a launch amplitude of the communication signal.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Abstract: A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver, and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the receiver to the transmitter. In typical embodiments the auxiliary data include one or more streams of audio data.

Abstract: Provided are a current mode differential transmission method and system for differentially transmitting three units of data using four signal lines. The method includes: dividing the four signal lines 1a, 1b, 2a and 2b into two pairs of signal lines 1a/1b and 2a/2b, and differentially transmitting respective data (first data and second data) via the two pairs of signal lines 1a/1b and 2a/2b; and transmitting the other data (third data) by differentially changing common mode currents of the two pairs of signal lines 1a/1b and 2a/2b.

Abstract: A (binary) signal is transmitted through an electrical backplane, and the received signal is interpreted as a duobinary signal. In order to ensure that the received signal can be properly interpreted as a duobinary signal, the data signal is preferably filtered prior to being interpreted. The filter is preferably designed such that the combination of filter and the backplane approximates a binary-to-duobinary converter. In one embodiment, an (FIR-based) equalizing filter is applied to the data signal prior to transmission to emphasize the high-frequency components and flatten the group delay of the backplane. The resulting, received duobinary signal is converted into a binary signal by (1) splitting the duobinary signal, (2) applying each copy to a suitably thresholded comparator, and (3) applying the comparator outputs to a suitable (e.g., XOR) logic gate. The transmission system enables high-speed data (e.g., greater than 10 Gb/s) to be transmitted over relatively inexpensive electrical backplanes.

Abstract: A semiconductor integrated circuit device serving as a signal source, another semiconductor integrated circuit device serving as a destination and a transmission line form in combination a communication system; the transmission line is connected between a transmitting circuit of the semiconductor integrated circuit device and a receiving circuit of the other semiconductor integrated circuit device; equalizers are incorporated in the transmitting circuit and receiving circuit, respectively, so that the equalizer of the receiving circuit is not expected to exhibit a large amplification factor to the high frequency signal components; this results in that the received signal is restored to a waveform close to the original waveform.

Abstract: Nuclear spectroscopy systems have improved over the course of time especially with the advent of digital pulse processing. One disadvantage of digital processing, however, is that it has eliminated the older, universally compatible interface standard of analog signals. Digital component interfaces are often defined by computer software, protected by copyright and unique to a single manufacturer. Consequently, all components of an entire spectroscopy system must be from a single manufacturer. This not only dictates system wide component replacement, but also impedes optimization that would otherwise occur were component compatibility the rule rather than the exception. The present innovation describes a method and apparatus to relieve the present incompatibility between digital components of a nuclear spectroscopy system that are supplied by more than one manufacturer.

Abstract: A DC-balanced signal is imposed on the input of a transmission line. Prior to imposing the DC-balanced signal, the input of the transmission line is held at an intermediate DC level that intermediate between the maximum and minimum DC levels of the DC-balanced signal. Alternatively, a compensating pulse is additionally imposed on the input of the transmission line. The compensating pulse compensates for a change in the DC level at the output of the transmission line caused by the imposing of the DC-balanced signal on the input of the transmission line.

Abstract: An image transmitter, comprising: a color difference differential calculating unit configured to calculate color difference differential data relating to a difference between a current predicting value predicted based on a previous image data and current actual image data; a coding unit configured to code the color difference differential data to generate coding data; a multi-valuation unit configured to generate multi-valued data based on the coding data and an occurrence probability of the coding data based on statistical properties of the image data; and a transmitting unit configured to transmit the multi-valued data via at least one transmission line.

Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: An extender circuit for handling a communication signal transmitted over a transmission line includes a voltage clamp and a current booster circuit. The voltage clamp is connected to a receive end of the transmission line and is operable to clamp a reflection signal caused by the communication signal received at the receive end of the transmission line. The current booster circuit is connected to the receive end of the transmission line and is operable to provide a boost current at the receive end of the transmission line during a positive transition of the communication signal.

Abstract: Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided. In one embodiment, a data signal which represents the data to be transmitted by means of a sequence of first and second signal levels is applied to the first transmission line, and a reference signal which changes between a first and a second reference level only when a level change between the first and the second signal level is suppressed between two successive signal levels of the data signal on the first transmission line is applied to the second transmission line.

Abstract: We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.

Abstract: In the case of a method and a device for transmitting data units by way of a transmission medium that comprises at least three adjacent transmission lines, first of all a plurality of codes is supplied. Each code has a number of code sections that corresponds to the number of transmission lines of the transmission medium. Each code section has on an associated transmission line a predetermined signal value, the sum of the signal values for each transmitted code being substantially constant. For each data unit to be transmitted, a code is selected from the plurality of codes, and the selected code is supplied for transmission by way of the transmission medium. The data units and the codes to be transmitted can be supplied in accordance with a predetermined clock pulse, a new code being selected at each new clock pulse, based on the preceding code and the new data unit.

Abstract: An electrical isolation barrier for use in a Data Access Arrangement uses a high frequency (HF) transformer 24 to provide isolation. An input signal, which may be analog or digital, is connected to a modulator. The analog output of the modulator is connected to the input of the HF transformer. The output of the HF transformer is connected to the input of a demodulator. Simple amplitude modulation can be used in the modulator to modulate the input signal to the frequency range of operation of the HF transformer. A simple low pass filter may be incorporated in the demodulator to remove harmonic distortion caused by the HF transformer. The output signal of the demodulator is substantially the same as input signal.

Abstract: A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: A system transmits data on a multi-conductor signal path, which produces a current flow based on the value of the data transmitted. The system reduces changes in current flow between successive data transmissions by encoding data values represented by sets of N bits to produce corresponding sets of M symbols. Each set of M symbols represents multiple bits and each set of M symbols is selected to produce a current flow within a predetermined range of current flows. The sets of M symbols are transmitted across the multi-conductor signal path.

Abstract: A signal compensation circuit and associated method dynamically compensate for signal baseline wandering in a transmission line. The compensation circuit has a detection circuit and a correction circuit. The detection circuit first compares a transmission signal with a reference level and generates a comparison result. The correction circuit then corrects the transmission signal according to the comparison result. The compensation circuit can adjust its compensation over time based on the quality of the transmission signal.