Abstract: Systems and methods for detecting, localizing, and filtering signals such as radiofrequency signals using an array of antennas are disclosed. Input signals each containing a signal of interested are received, along with a reference signal sharing one or more characteristics of the signal-of-interest. Predetermined time delays and frequency shifts are applied to the input signals such that the signal-of-interest components of the signals are synchronized and to cancel any Doppler-shifting between the signal-of-interest components. A filtering process is employed to filter the shifted input signals and sum them such that a metric indicating the degree of difference between the reference signal and the summed filtered signals (such as the mean squared error, for example) is minimized.

Abstract: An enhanced LOng RAnge Navigation (eLORAN) system may include a plurality of eLORAN stations, each having an eLORAN antenna and an eLORAN transmitter that may transmit data over an eLORAN data channel and may transmit a series of eLORAN navigation RF pulses. An eLORAN control station may generate station specific eLORAN data and non-station specific eLORAN data, divide the non-station specific eLORAN data into non-specific eLORAN data subsets, and cause each eLORAN station to transmit the station specific eLORAN data and a corresponding non-station specific eLORAN data subset over the eLORAN data channel in a manner to optimize data throughput.

Abstract: A memory subsystem includes one or more communication channels that enable communication with more than one memory module of an information handling system (IHS). A memory controller of the memory subsystem is in communication with the one or more communication channels. In response to determining that one or more lines fail signal integrity testing at a target communication speed, the memory controller invokes an error checking and correcting (ECC) mode that reassigns lines of the communication channel for carrying data and ECC code. Lines that passed signal integrity testing are assigned to carrying data and ECC code. Lines that failed signal integrity testing are not used.

Abstract: An audio processing circuit may have a first path for processing multi-bit audio signals in parallel with a second path for processing single-bit audio signals. The parallel paths may share a common input node for receiving audio data and a common output node for reproducing audio at a transducer. Each path may have a volume control for adjusting an output of the path. The audio processing circuit may determine a type of an audio signal received at the input. The path not corresponding to the detected type of the audio signal is muted, and the path corresponding to the detected type of audio signal is unmuted.

Abstract: According to an aspect of the present disclosure, a method in a digital communication system comprising, receiving a first data packet comprising a set of preamble bits for transmission, selecting a first modulation parameter in relation with a first bit sequence property of the first data packet, modulating a carrier signal with the first modulation parameter to generate a first baseband signal embedding information in the data packet, receiving a second baseband signal at a receiver, performing correlation of the second baseband signal and a reference baseband signal to generate a correlation result and demodulating the second baseband signal to form a received bits when the correlation result peaks above a threshold value.

Abstract: A method includes, in a receiver, receiving a signal carrying data using multiple antennas, so as to produce multiple respective input signals. The input signals are divided into two or more subsets. The input signals within each of the subsets are combined in a first diversity-combining stage, to produce respective intermediate signals. In a second diversity-combining stage, the intermediate signals are combined to produce an output signal. The output signal is decoded so as to reconstruct the data carried by the received signal.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: A communication apparatus includes a Doppler shift amount calculation unit configured to calculate a Doppler shift amount of a reception signal which is obtained by modulating a signal, for which spectrum spreading is performed by using a predetermined spread code, by a predetermined carrier frequency, a frequency shift amount setting unit configured to set a frequency shift amount on the basis of the Doppler shift amount, a frequency conversion unit configured to shift the frequency of the reception signal by the frequency shift amount, a coherent addition unit configured to perform coherent addition of the reception signal, a spread code generation unit configured to generate a spread code, and a phase detection unit configured to perform correlation calculation between a calculation result of the coherent addition and the spread code and detect a phase of the spread code of the reception signal on the basis of the correlation calculation result.

Abstract: Embodiments of an apparatus for improving a gain imbalance between an in-phase and quadrature component recovered by a receiver are provided. The apparatus includes a first transition counter configured to count a number of bit transitions in a first sequence of one-bit values provided by a first sigma-delta modulator based on the in-phase component, and a second transition counter configured to count a number of bit transitions in a second sequence of one-bit values provided by a second sigma-delta modulator based on the quadrature component. The apparatus further includes a gain monitor configured to: (1) determine a first and second power level, proportional to a power of the in-phase and quadrature components respectively, using the number of bit transitions in the first and second sequences, and (2) adjust a gain of one of the in-phase and quadrature components based on a ratio between the first and second power levels.

Abstract: Logic may comprise a single phase tracking implementation for all bandwidths of operation and the logic may adaptively change pre-defined and stored track parameters if the receiving packet is 1 MHz bandwidth. Logic may detect a packet and long training fields before performing a 1 MHz classification. Logic may auto-detect 1 MHz bandwidth transmissions by a property of the long training field sequences. Logic may auto-detect 1 MHz bandwidth transmissions by detecting a Binary Phase Shift Keying (BPSK) modulated first signal field symbol rather than the Quadrature Binary Phase Shift Keying (QBPSK) associated with the 2 MHz or greater bandwidth transmissions. Logic may perform an algorithm to determine an estimated phase correction value for a given orthogonal frequency division multiplexing symbol and several embodiments integrate this value with an intercept multiplier that may be 0.2 for 1 MHz transmissions and, e.g., 0.5 for 2 MHz or greater bandwidth communication.

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Abstract: A symbol error detector can be configured to detect symbol errors of a Bluetooth enhanced data rate (EDR) packet without relying solely on a CRC error detection mechanism. After a phase of a current symbol is demodulated to determine a demodulated current symbol, the phase of the demodulated current symbol can be subtracted from the phase of the current symbol prior to demodulation to yield a phase error. The phase error can be compared against a phase error threshold to determine a potential unreliability of the demodulated current symbol. The phase error being greater than the phase error threshold can indicate that the demodulated current symbol may be unreliable. Accordingly, a symbol error notification can be generated to indicate that the demodulated current symbol may be unreliable.

Abstract: A mobile terminal and an operation control method thereof in which a delay time of the screen lock execution is controlled according to the type of application, are discussed. The mobile terminal according to an embodiment of the present disclosure may include an input unit configured to receive a user input; an execution controller configured to execute screen lock if the user input is not received for a first delay time; and a change controller configured to extend the first delay time to a second delay time based on the user's gaze information.

Abstract: The receiver (1) for FSK modulation signals includes an antenna (2) for receiving modulated data or control signals, a low noise amplifier (3) for amplifying and filtering the signals picked up by the antenna, a local oscillator (6) with a quartz resonator (7) for supplying high frequency, in-phase signals (SI), and high frequency, in-quadrature signals (SQ), first and second mixers (4, 5) for mixing the high frequency, in-phase and in-quadrature signals with the filtered and amplified incoming signals, in order to generate intermediate signals (Im, Qm), and a filtering unit (12) for filtering the intermediate signals. The receiver can be configured to receive modulated data or control signals at low rate.

Abstract: The present invention discloses a method and apparatus for wide dynamic range phase conversion. In one embodiment, inphase and quadrature signal components of a complex input signal are collapsed into a single quadrant to produce a first signal representation. A scaling operation is subsequently performed on the first signal representation to produce a second signal representation. Lastly, the second signal representation is converted into the phase domain.

Abstract: A symbol error detector can be configured to detect symbol errors of GFSK modulated portions of a Bluetooth packet without relying solely on a CRC error detection mechanism. The symbol error detector can operate on frequency error signals that are a difference between a frequency associated with a current symbol and predetermined frequency outputs from a bank of filters matched to a frequency response of the Bluetooth receiver for predefined combinations of three consecutive symbols (i.e., an estimated previously decoded symbol, an estimated current symbol, and an estimated subsequent symbol). The frequency error signals can be compared against a threshold and against each other to determine a potential unreliability in decoding the current symbol and to determine whether to generate a symbol error notification. The frequency error signals being within a threshold of each other can indicate potential unreliability in decoding the current symbol.

Abstract: A signal demodulation method is disclosed, which includes: obtaining a complete transmission code word; calculating estimated values of three non-differential phases of the transmission code based on a majority logic; identifying a most unreliable phase among three non-differential phases and determining the other two reliable phases to obtain their determination values; calculating determination values of the rest two phases based on the two determined phases; and looking up in tables based on determination values of the four phases to obtain incoming bits. The demodulation method of the present invention is capable of sufficiently reducing the effect of noise on signal and effectively improving the signal demodulation performance.

Abstract: A mobile terminal and an operation control method thereof in which a delay time of the screen lock execution is controlled according to the type of application, are discussed. The mobile terminal according to an embodiment of the present disclosure may include an input unit configured to receive a user input; an execution controller configured to execute screen lock if the user input is not received for a first delay time; and a change controller configured to extend the first delay time to a second delay time based on the user's gaze information.

Abstract: A handover control method in a mobile communication system that performs handover control by switching base stations that communicate with a mobile terminal as the mobile terminal moves. In this handover control method, a mobile control device selects one or more handover base station candidates based on the communication state, and based on the communication capabilities of the handover base station candidates, decides a transmission rate for multicasting communication data, and transmits communication data to each of the handover base station candidates at the decided transmission rate, and a handover base station candidate that is decided as a handover base station sends the saved multicast communication data to the mobile terminal.

Abstract: A method (500) of demodulation, the method comprising the steps of receiving (510) a radio frequency signal, converting (520) the received radio frequency signal to a baseband signal, performing (530) symbol timing recovery on the baseband signal, and demodulating (540) the baseband signal. The baseband signal comprises alternating symbols spaced therebetween at an alternating first interval length and a second interval length, where the first interval length and second interval length are dissimilar. Communication units and a method of modulation are also described.

Abstract: A symbol error detector can be configured to detect symbol errors of a Bluetooth enhanced data rate (EDR) packet without relying solely on a CRC error detection mechanism. After a phase of a current symbol is demodulated to determine a demodulated current symbol, the phase of the demodulated current symbol can be subtracted from the phase of the current symbol prior to demodulation to yield a phase error. The phase error can be compared against a phase error threshold to determine a potential unreliability of the demodulated current symbol. The phase error being greater than the phase error threshold can indicate that the demodulated current symbol may be unreliable. Accordingly, a symbol error notification can be generated to indicate that the demodulated current symbol may be unreliable.

Abstract: A symbol error detector can be configured to detect symbol errors of GFSK modulated portions of a Bluetooth packet without relying solely on a CRC error detection mechanism. The symbol error detector can operate on frequency error signals that are a difference between a frequency associated with a current symbol and predetermined frequency outputs from a bank of filters matched to a frequency response of the Bluetooth receiver for predefined combinations of three consecutive symbols (i.e., an estimated previously decoded symbol, an estimated current symbol, and an estimated subsequent symbol). The frequency error signals can be compared against a threshold and against each other to determine a potential unreliability in decoding the current symbol and to determine whether to generate a symbol error notification. The frequency error signals being within a threshold of each other can indicate potential unreliability in decoding the current symbol.

Abstract: In a receiving apparatus (100), a noise power estimation unit (107) estimates the noise power included in a received signal in the frequency domain. A channel characteristics calculation unit (105) estimates the channel characteristics in accordance with a reference signal included in the received signal. A tap coefficient calculation unit (108) calculates the tap coefficients for a filtering unit (109) in accordance with noise power included in the received signal and with an autocorrelation value for the channel characteristics. The filtering unit (109) calculates an estimated value for the channel characteristics via filtering processing on the channel characteristics in accordance with the tap coefficients.

Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: Methods and apparatus are provided for receiving an input signal. In an embodiment of the invention a current candidate QAM constellation can be selected. A mean squared error of a signal responsive to the input signal can be computed based on the current candidate QAM constellation. The computed mean squared error can be compared to a threshold error value. The invention advantageously allows for relatively efficient and relatively reliable equalization of signals transmitted with an unknown QAM constellation, and allows for relatively efficient and reliable recovery of the unknown QAM constellation.

Abstract: A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, ?) rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.

Abstract: A method of generating a phase value representative of a phase of a complex signal that includes an in-phase component and a quadrature-phase component includes determining a first sign for a first value and a second sign for a second value based on a quadrant occupied by the complex signal. The in-phase component is multiplied by the first value with the first sign, thereby generating a first multiplication result. The quadrature-phase component is multiplied by the second value with the second sign, thereby generating a second multiplication result. The first multiplication result, the second multiplication result, and a bias value are added, thereby generating the phase value for the complex signal.

Abstract: A sampling offset estimation apparatus including a pilot sub-carrier refiner, an information sub-carrier refiner, a data sub-carrier refiner, and a sampling offset estimator. The pilot sub-carrier refiner to refine a pilot sub-carrier extracted from a differential demodulated signal, and to generate a reference pilot sub-carrier. The information sub-carrier refiner to refine an information sub-carrier extracted from the differential demodulated signal, and to generate a reference information sub-carrier. The data sub-carrier refiner to refine a data sub-carrier extracted from the differential demodulated signal, and to generate a reference data sub-carrier. The sampling offset estimator to estimate a sampling offset included in the differential demodulated signal, on a basis of the reference pilot sub-carrier, the reference information sub-carrier, and the reference data sub-carrier.

Abstract: A receiver includes a signal input for receiving a differentially-encoded quadrature phase-shift keyed (DEQPSK) communication signal. A demodulator performs bit decisions on a received coherent symbol and bit decisions on a received differential symbol. A processor is operative with the demodulator and scales a soft decision by a factor from 0 to 1 when the results of the bit decisions on the received coherent branch and differential branch are different.

Abstract: A mixer circuit accumulates I signal (digital signal of first channel) having its band limited by low-pass filter and first carrier signal to perform two-phase shift keying modulation thereon. An adder adds fundamental-wave component of bit clock signal BCK into Q signal (digital signal of second channel) having its band limited by the another low-pass filter to obtain a resultant added-up signal. Another mixer circuit accumulates the added-up signal and second carrier signal to perform two-phase shift keying modulation thereon. Output signals of the mixer circuits are input to another adder so that they may be added up to obtain a QPSK signal as a modulated quadrature signal. The QPSK signal contains frequency signals whose frequencies are a sum of bit clock frequency and carrier frequency and a difference between them. When demodulating, the carrier signal and the bit clock signal are reproduced using the frequency signals.

Abstract: The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . .

Abstract: A receiving/processing unit receives signals parallelized by a parallelizing unit, and executes a frame process including frame synchronization process on the signals. A phase comparing circuit and a phase judging circuit judge whether a bit delay is present based on a phase difference between a phase of a clock signal at a clock/data recovering unit and a phase of a clock signal at the parallelizing unit. The receiving/processing unit includes a logic processing circuit that executes a bit delay process based on a result of judgment by the phase comparing circuit and the phase judging circuit.

Abstract: An apparatus and method for improving a symbol error rate of an M-ary phase shift keying (M-PSK) system having a quadrature error are provided. The apparatus includes: a conversion parameter detector that detects a conversion parameter and converts a symbol decision region using the quadrature error and at least one pair of first received symbols; and a converter & determiner converting a pair of second received symbols using the detected conversion parameter, and determining a transmission symbol according to a symbol of the converted pair of second received symbols. An increase in a symbol error rate due to the quadrature error can be prevented and the quadrature error can be easily estimated.

Abstract: A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Abstract: Methods and apparatus are provided for receiving an input signal. In an embodiment of the invention a current candidate QAM constellation can be selected. A mean squared error of a signal responsive to the input signal can be computed based on the current candidate QAM constellation. The computed mean squared error can be compared to a threshold error value. The invention advantageously allows for relatively efficient and relatively reliable equalization of signals transmitted with an unknown QAM constellation, and allows for relatively efficient and reliable recovery of the unknown QAM constellation.

Abstract: A method is disclosed for correcting carrier frequency offset (CFO) in a received data packet that includes one or more M data streams. The data packet has a payload portion preceded by a preamble portion, the payload portion having a plurality of data symbols (L) each of which include a plurality of data tones (K). The method comprises, making a per-stream preamble CFO estimate for each data stream by correlating repeated preamble portions that precede the data packet. The per-stream preamble CFO estimates are weighted and averaged to obtain a single preamble CFO estimate. Any CFO in each received data stream is then corrected according to the preamble CFO estimate. Additionally, for an lth data symbol in a data packet, a per-tone CFO estimate is derived and successively averaged over frequency (tones), time (symbols) and space (data steams) to derive data CFO estimate pdata. Any CFO in each received data stream may be corrected according to the data CFO estimate, and/or the preamble CFO estimate.

Abstract: The invention relates to an orthogonal frequency division multiplexing system with PN-sequence. In the synchronization of the invention, both timing offset and frequency offset are estimated and compensated by utilizing a time and frequency synchronization device. In addition, the PN-sequence with the cyclic prefix is added to the OFDM symbol before transmitting. The time and frequency synchronization device of the invention comprises two synchronization circuits from the cyclic prefix and PN-sequence when calculating the timing offset and frequency offset of receiving signal. As a result, the OFDM system of the invention not only has better performance in fading channel, but also has the better bandwidth utilization without extra bandwidth for transmitting the PN-sequence.

Abstract: An RF receiving apparatus and method which can remove a leakage component in a received signal are provided. In the RF receiving apparatus, a noise removing unit estimates a signal corresponding to a noise component introduced into a received RF signal RXIN by controlling a gain and a phase of a local signal LOI and removes the estimated noise signal from the received RF signal RXIN. An RF signal in which the noise is removed is frequency-down converted in a receiving unit. Also, the noise removing unit utilizes a Q signal of the local signal LOI, LOQ, to control the phase of the local signal LOI.

Abstract: The present invention relates to a multiple differential demodulator using a weighting value. The multiple differential demodulator according to the present invention includes a weighting value generator for integrating a real part and an imaginary part of a value acquired by multiplying one of a plurality of differentiated reception signals by a conjugated value of a differentiated PN code signal corresponding to a preset symbol, and determining the greater of the integrated real and integrated imaginary parts to apply a predetermined weighting value to the greater value, where the PN code signal is differentiated in the same fashion as the differentiated reception signals.

Abstract: The present invention relates to a method of estimating symbol synchronization for an Offset Quadrature Phase Shift Keying (OQPSK) demodulator applicable to a Zigbee receiver. More particularly, the invention relates to a method of recovering symbol synchronization of an OQPSK demodulator in which a reference correlation value is reset using a correlation value of a reception signal when detecting symbol synchronization in the OQPSK demodulator, preventing errors in detecting symbol synchronization due to noise, thereby increasing the accuracy in symbol synchronization.

Abstract: A common signal generating sub-system (CSGS) for a radio frequency (RF) receiver. The CSGS includes a down converter section and a digitizer section. The down converter section receives intermediate frequency (IF) signals and injection frequency signals from an RF/IF processing section of an RF receiver and translates the IF signals to analog intermediate frequency (IF) signals preserving the spectra thereof. The analog IF signals comprise analog in-phase IF signals and analog quadrature IF signals. The digitizer section utilizes a locally generated sampling rate signal (LGSRS) and converts the analog in-phase IF signals and the analog quadrature IF signals to a common digital in-phase IF signal and a common digital quadrature IF signal. The common digital IF signals can be subsequently processed by a digital processing section of the RF receiver.

Abstract: A method and system of improving sensitivity in the demodulation of a received signal over an arbitrary measurement time epoch, the method comprising the steps of: correlating the received signal in a coherent fashion (80); and utilizing a Viterbi phase state keying trellis demodulation with a variable resolution of phase states over 360° to demodulate the radio frequency phase trajectory of the signal throughout the measurement time epoch (70); and the system comprising a receiver for receiving a direct sequence spread spectrum signal, the receiver comprising: an antenna (10) for receiving the direct sequence spread spectrum signal; a downconverter (40) for downconverting the received signal, producing a downconverted signal; an analog to digital converter (60) to convert the downconverted signal to a digital signal; a despreader (80) for despreading and coherently correlating the digital signal to a known signal, creating a despread signal; and a processor (70) for applying a Viterbi algorithm to the despre

Abstract: A method and apparatus for extending the linear range of a phase detector. In one embodiment, a limited range phase difference is generated between selected edges of first and second input signals, and an excursion of the limited range phase difference beyond a predetermined threshold is detected. In response to detecting the excursion of the limited range phase difference beyond a threshold, an edge of the first or second input signal is prevented from influencing subsequent generation of the limited range phase difference, and a compensated phase difference is generated, derived from the limited range phase difference and including a correction component which compensates for the effect of preventing said edge from influencing subsequent generation of the limited range phase difference.

Abstract: The invention relates generally to the field of wireless communications and more particularly to a method of and device for detecting the presence of a received data packet in a digital receiver. The present invention proposes a simplified method of correlation by removing dependency on the amplitude fluctuations while at the same time maintaining phase relevancy. The key advancement involves mapping the complex quadrature amplitude modulation (QAM) preamble to a quantized phase shift keying (PSK) constellation before application to a matched complex correlator. The proposed process essentially “amplitude normalizes” the input signal without the use or complexity associated with a divider. This simplified normalization scheme makes the packet detection algorithm robust against amplitude variations in the input signal, while still allowing for good correlation output.

Abstract: An AGC processing portion receives a burst signal of each received frame, and measures its received power level to perform gain control of a variable gain amplifier. Unlike a conventional wireless receiving device, a digital signal from an A/D converter is directly supplied to the AGC processing portion, without passing through an FIR filter. Accordingly, the input timing for the AGC processing portion does not include a delay due to the FIR filter, and an amplitude value can be adjusted to be appropriate from the leading part of each frame, suppressing the occurrence of a reception error due to AGC processing.