Abstract: Provided is a direct-conversion frequency mixer for down converting a radio frequency (RF) signal into a baseband signal, in which a single phase RF signal and a quadrature location oscillation (quadrature LO) signal are used to generate the baseband signal, the frequency mixer comprising a first frequency mixing unit that uses quadrature LO signals having respective phases of 0 degrees and 180 degrees to directly down-convert the single phase RF signal into the in-phase baseband signal, and a second frequency mixing unit that uses quadrature LO signals having respective phases of 90 degrees and 270 degrees to directly down-convert the single phase RF signal into the quadrature-phase baseband signal, whereby drains and sources of the transistor for receiving the quadrature LO signal and the transistor for receiving the RF signal are connected in common, thus enabling low power source voltage driving.

Abstract: An apparatus and method for use by a receiver in decoding information sent by phase-shift keying over a carrier frequency is disclosed. The method is well suited for use with power line carrier (PLC) applications as it is adapted to appropriately position the sampling window based on a zero crossing of one of the phases of the power line. The method allows for receipt and processing of information on more than one carrier frequency and from transmitters operating on a phase of the power line that is different than the phase used by the receiver to detect the zero crossings of the alternating current at the power grid frequency on the power line. A number of alternative embodiments are included.

Abstract: A method and an apparatus relating to an OFDM data communications system where the sub-carriers are modulated using differential quadrature phase-shift keying (DQPSK). The multi-carrier transmitted signal is directly generated by means of summation of pre-computed sample points. As part of the multi-carrier signal generation, a signal for the guard interval is established. In an acoustic application of this approach, direct radiation of the sub-carrier approach is facilitated. Symbol synchronization in the receiver is based on signal correlation with the missed sub-carrier. Separation of the sub-carriers in the receiver by means of correlation of the received signal and reference signals that are derived from a table of pre-computed values. Optimal non-coherent processing of the sub-carriers without any phase tracking procedures is achieved.

Abstract: A system for processing a data packet is disclosed and may include at least one processor that enables receiving of a data packet at a station on a network, the data packet having a preamble which includes a destination tag and a training sequence. The at least one processor may enable obtaining a channel model using the training sequence, and encoding each of one or more addresses that the station receives with the channel model to produce a result. The at least one processor may also enable comparing the result with the destination tag. The at least one processor may enable convolving of each of the one or more addresses that the station receives with the channel model to produce the result.

Abstract: Methods and apparatuses employing symmetrical phase-shift keying (SPSK) for data modulation and demodulation. Each symbol in a transmission signal carries n-bit information and is transmitted with one of 2n+1 directions. Half directions among the 2n+1 directions are regarded as default directions and the remaining are regarded as complementary directions. Each default direction has a corresponding complementary direction with a phase difference of ? and representing the same n-bit information as the default direction. The phase difference between any two successive symbols after modulation is less than or equal to ?/2.

Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.

Abstract: A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator (4) is connected with an input to the detector output and an oscillator output is connected to a loop output (12). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device (7;71-74) having a transfer function with at least one zero.

Abstract: A system for demodulation of the Loran Data Channel transmitted over the Enhanced Loran (eLoran) system including a quadrature filter. The quadrature filter calculates the real and quadrature phase components of a received ninth pulse. The resultant components are used to obtain the angle of the ninth pulse. This angle is then compared with a set of pre-tabulated angles/symbols that are calculated using the same quadrature filter on thirty-two different simulated ninth pulses. The closest angle match gives the corresponding symbol. Such twenty-four symbols make up a single Reed Solomon encoded message. This message is then passed through a Reed Solomon decoder and the transmitted message is obtained.

Abstract: A receiving/processing unit receives signals parallelized by a parallelizing unit, and executes a frame process including frame synchronization process on the signals. A phase comparing circuit and a phase judging circuit judge whether a bit delay is present based on a phase difference between a phase of a clock signal at a clock/data recovering unit and a phase of a clock signal at the parallelizing unit. The receiving/processing unit includes a logic processing circuit that executes a bit delay process based on a result of judgment by the phase comparing circuit and the phase judging circuit.

Abstract: A demodulator of a differential detection system for a ?/4 shifted QPSK or DQPSK modulation wave in digital communication. The demodulator includes a differential detector connected to receive orthogonal components of the modulation wave, a corrector connected to receive an output of the differential detector for correcting a deviated distribution of signal points on a constellation, and a slicer/decoder connected to receive an output of the corrector. The slicer/decoder decodes a received bit from the signal points after the deviated distribution is corrected. The corrector has average calculators connected to receive respective outputs of the differential detector, and subtractors connected to receive the associated outputs of the differential detector and also to receive associated outputs of the average calculators for subtracting an average value of the outputs of the differential detector from the outputs of the differential detector.

Abstract: An apparatus and method for performing digital timing recovery includes a rotating demultiplexor receiving a four times oversampled baseband signal and providing four downsampled phases at respective outputs. Each output is processed by a correlation detector which computes a peak sum signal for each downsampled phase. The peak sum signals are processed to produce a best phase select output signal. The best phase select output signal is used to select the optimum sampling phase. Symbol timing is then determined based on the relative peak offset in the best downsampled phase.

Abstract: A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinations are formed from the first digital signal. A decision is made whether the bit combination is an erroneous bit combination, and a probability check is performed to obtain probability values that decide which parts of the erroneous bit combination are true and which are false. A corrected bit combination is generated from the obtained probability values, and a second digital signal is generated whose data states are formed from the valid bit combination and, in the presence of an erroneous bit combination, from the corrected bit combination.

Abstract: A system for estimating the modulation index and frequency offset of a CPM signal. An estimator filters the received signal and utilizes a training sequence to determine the modulation index and frequency offset of the CPM signal. The estimator can also include a post-processing step to eliminate all or part of a bias that might be created by the estimator.

Abstract: A method is described for correcting sampling frequency offset (SFO) of a data packet in a communications system where carrier frequency (fc) and sampling frequency (fs) are driven by a common clock source. The method comprises, for each lth symbol in the data packet, estimating carrier frequency offset (CFO) in a received data packet. From the CFO estimate, an SFO estimate is derived, wherein the SFO is approximately equal to fs multiplied by said CFO estimate, and divided by fc. An SFO phase correction is generated according to the SFO estimate for each kth tone in a data stream. The SFO phase correction is then applied to each received data stream.

Abstract: A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.

Abstract: A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1, St2; Stp) are determined, and a decision is made as to whether the respective bit combination (St1, St2; Stp) is a valid combination (Sg1, Sg2; Sgp) or an erroneous one (Sf1, Sf2; Sfp). Probability values (Sw1, Sw2; Swp) are determined that decide which parts of the erroneous bit combination (Sf1, Sf2; Sfp) are probably true and/or which are probably false. Next, a corrected bit combination (Sk1, Sk2; Skp) is formed from the existing information. Finally, a second digital signal (d2) is generated as an output signal, whose data states are formed either from the valid bit combination (Sg1, Sg2; Sgp) or from the corrected bit combination (Sk1, Sk2; Skp).

Abstract: A polyphase receiver comprises an RF front end (10 to 28) for receiving a wanted data signal modulated on a carrier signal and for producing quadrature related low IF signals, an image rejection filter formed by a polyphase filter (30) for filtering the quadrature related low IF signals, soft limiting means (36,38) for compressing the dynamic range of the filtered quadrature related IF signals and a signal demodulator (41) for recovering the data signal. The soft limiting means (36,38) has a characteristic which is substantially linear at signal levels 10 dB below a predetermined minimum wanted signal level, moves into compression for higher signal levels and hard limits at substantially 10 dB above the desired receiver sensitivity which avoids degrading the sensitivity of the receiver.

Abstract: An 8-ary PSK demodulation apparatus for receiving an input signal Rk(Xk, Yk) comprised of a kth quadrature-phase component Yk and a kth in-phase component Xk, and for generating soft decision values ?(sk,0), ?(sk,1), and ?(sk,2) for the input signal Rk(Xk, Yk) by a soft decision means. A calculator calculates Zk by subtracting a level |Yk| of the quadrature-phase signal component Yk from a level |Xk| of the in-phase signal component Xk, and outputs the Zk as a first soft decision value. A first selector selects the Zk or reverse ?Zk, according to an MSB of the quadrature-phase signal component Yk. A second selector selects the Zk or the reverse ?Zk according to an MSB of the in-phase signal component Xk. A third selector selects an output of the second selector or a value “0” according to an MSB of the Zk. A first adder adds ?{square root over (2)}Yk to an output of the third selector, and outputs the result value as a third soft decision value.

Abstract: A differential detector produces, for each symbol, a phase difference between received phase information and one-symbol-delayed phase information, and delivers the phase difference to a differential circuit and a phase corrector. Another differential detector produces, for each symbol, a phase difference between the one-symbol-delayed phase information and two-symbol-delayed phase information of the received phase information. The differential circuit produces, for each symbol, phase-difference difference information from a difference between both the phase differences. A phase error detector obtains a phase error caused by a difference in the carrier frequency between a sending and a receiving digital radio apparatus, based on the phase-difference difference information and either of both phase differences. A phase corrector subtracts the phase error from the phase difference.

Abstract: The invention proposes the separate processing of the phase and amplitude of multi-amplitude digital modulation techniques, such as a QAM. The phases are differentially modulated and the amplitudes coherently processed. Also proposed is a method to correct the amplitude distortion of the symbols on each subcarrier, either from the QAM signal itself or from any PSK signal, if available. The invention shows that differential modulation/demodulation of multi-amplitude signals with no equidistant phases such as QAM is possible. Complex equalizer means to perform a channel estimation is no more needed as for coherent systems. Further, no pilot sucarriers are needed, thus the bandwidth efficiency is much higher. Furthermore, the frequency snychronization of differential demodulated signals is less complex. An implementation proposal of the new modulation/demodulation technique is described.

Abstract: The present invention relates to a method for receiving CDMA signals with synchronization being obtained through double delayed multiplication, and an associated receiver. According to the invention, the correlation signal undergoes double delayed multiplication. Synchronization is established on the signal thus generated. Applied to digital communications, in particular with mobile phones.

Abstract: A tangent angle computation device and associated DQPSK decoder. The computation device uses an eight-bit divider and a four-quadrant technique for finding a quantized angular value from an incoming signal. The quantized angular value is subsequently used to decode the incoming signal.

Abstract: A baseband detector includes a complex differential detector, a constellation point computer, and a phase shift keying (PSK) decoder. The complex differential detector outputs complex values in response to digitized samples derived from a received baseband signal. The PSK decoder generates decoded bits representing information symbols by determining in minimum distance between the complex values and plural constellation points provided by the constellation point computer. The constellation point computer can adaptively generate the constellation points based on a training sequence of information symbols and their corresponding complex valued outputs from the complex differential detector. The baseband detector can be used for frequency shifting keying (FSK) and differential phase shift keying (DPSK) demodulation in direct conversion receivers (DCRs).

Abstract: A demodulator of a differential detection system for a &pgr;/4 shifted QPSK or DQPSK modulation wave in digital communication. The demodulator includes a differential detector connected to receive orthogonal components of the modulation wave, a corrector connected to receive an output of the differential detector for correcting a deviated distribution of signal points on a constellation, and a slicer/decoder connected to receive an output of the corrector. The slicer/decoder decodes a received bit from the signal points after the deviated distribution is corrected. The corrector has average calculators connected to receive respective outputs of the differential detector, and subtractors connected to receive the associated outputs of the differential detector and also to receive associated outputs of the average calculators for subtracting an average value of the outputs of the differential detector from the outputs of the differential detector.

Abstract: A method and apparatus for controlling communications between a mobile cellular telephone and a cell of a cellular telephone network. The apparatus comprises a serving transceiver for transmitting and receiving communications between the cell and the mobile cellular telephone, a scanner, coupled to an antenna, for selectably scanning the communication channels to measure a characteristic of the signal transmitted from the mobile telephone, and a controller, coupled to the scanner and the serving transceiver, for commanding the antenna based on the measured signal characteristic.

Abstract: A received signal phase detecting circuit in provided in which the circuit scale is small. The circuit functions so as to capture a frame synchronizing signal from a demodulated baseband signal, extract a symbol stream during the period of frame synchronizing signal from the demodulated baseband signal through delay circuits (41, 42) at a timing matching the bit stream of the captured synchronizing signal, rotating the phase of a corresponding symbol extracted from the symbol stream when the big in the bit in the bit stream is logic “0” by 80°, outputting the symbol after the phase rotation and a corresponding symbol extracted from the symbol stream when the bit in the bit stream is logic “1” from a 0°/180° phase rotating circuit (43), operating the cumulative average of the output from the 0°/180° phase rotating circuit (43) for a specific period through cumulative averaging circuits (45, 46), rotating the phase of the outputs therefrom through a 22.

Abstract: When reception of a multiplexed wave to be PSK-modulated of BPSK, QPSK, and 8PSK is started, a selector (16A) of a demodulating circuit (1A) reads high-order three bits &Dgr;&phgr;(3) of phase error data corresponding to I and Q symbol streams out of one phase error table (15-1) for BPSK among phase error tables provided for each modulation system and each phase rotation angle. A received-signal-phase rotation angle detecting circuit (8A) detects phase rotation angles of portions corresponding to bits (1) and (0) of a frame-synchronizing signal of a received symbol stream from the &Dgr;&phgr;(3) and the MSB of I symbol stream and outputs the phase rotation angles to a remapper (7) to make the remapper perform absolute phasing.

Abstract: A multipath processor processes a plurality of groups of spread-spectrum signals. Each group has a plurality of spread-spectrum signals. A first plurality of spread-spectrum signals is despread within a first group to generate a first plurality of despread signals. The first plurality of despread signals are combined as a first combined-despread signal. A second plurality of spread-spectrum signals is despread within a second group to generate a second plurality of despread signals. The second plurality of despread signals are combined as a second combined-despread signal. The first and second combined-despread signal are combined as an output-despread signal.

Abstract: A modulator produces a modulated signal including a carrier and data signals representing data bits. The data signals include at least two in-phase modulating pulses which have different shapes and which are interfering in time and frequency; the data signals further include at least two quadrature modulating pulses which have different shapes and which are interfering in time and frequency. The modulator includes a filter for producing each shape of pulse, and combining circuits for combining the pulses with each other and with a carrier. The demodulator (or receiver) receives the combined signal and separates the pulses from the carrier. The demodulator further includes filters for separating the pulses, and a circuit for processing the pulses to reproduce the data bits. The processing circuit preferably includes one or more maximum likelihood sequence estimation equalizers.

Abstract: A simplified method for frequency offset estimation in a TDMA cellular PCS environment using &pgr;/4-shifted DQPSK comprises the steps of multiplying a complex conjugate of a received complex-valued symbol and a succeeding symbol to produce a comparison vector having an angle equal to the phase angle between the received complex-valued symbol and the succeeding symbol, rotating the comparison vector so that the angle thereof is between 0° and 90°, and estimating the frequency offset by determining a constant deviation of the phase angle from an ideal phase angle value of 45° by calculating an average phase angle for a plurality of successive comparison vectors or correlating the rotated comparision vector against a bank of unit vectors to determine a maximum correlation.

Abstract: A simplified method for sampling timing adjustment and frequency offset estimation in a TDMA cellular PCS environment using &pgr;/4 - shifted DQPSK comprises the steps of oversampling a received signal resulting from transmission of sequences of complex-valued symbols at a rate N times the symbol rate thereof so as to produce N sets of samples, comparing for each set of samples the differential phase angle between successively received complex-valued symbols, and determining which set of the N sets of samples has differential phase angles closest to ideal values to thereby obtain an optimal sampling timing. The differential phase angles are measured by multiplying a complex conjugate of a received complex-valued symbol and a succeeding symbol to produce a comparison vector having an angle equal to the differential phase angle between the received complex-valued symbol and the succeeding symbol. The differential phase angles are optionally rotated so that the angle thereof is between 0° and 90°.

Abstract: The present invention concerns a receiver (110) including: an antenna (2) able to receive a frequency shift keying modulated signal (S), conversion means (3) able to receive this signal and to provide two first analog signals (I, Q); and demodulation means (112) able to receive said first signals and to provide a signal (X32+Y32) representative of the modulated signal. This receiver is characterised in that the demodulation means comprise: a complex filter (116) able to receive the first analog signals and to provide two second analog signals (X3, Y3), so that the gain of the transfer function (H3) can be equal to two different values (G1, G2); two normalisation means (118, 120) able to receive the second signals, and to provide in response two third analog signals (X32, Y32), representing a standard of the second signals; and an adder (122) able to receive said third signals and to provide the sum thereof.

Abstract: A differential FM detection of signals uses in-phase and quadrature phase signal components of a received signal in the detection process, wherein the in-phase and quadrature phase signal components are at a low intermediate frequency (IF). The in-phase and quadrature phase signal components are each amplitude limited, sampled at a prescribed sampling rate and filtered in a prescribed manner. Delayed versions of the filtered in-phase and quadrature phase signal components are generated and, then, signal products are generated of the delayed in-phase signal component and quadrature phase signal component, and the delayed quadrature phase signal component and in-phase signal component. The algebraic difference of the generated signal products is obtained to yield the desired data signal, e.g., symbols.

Abstract: Methods and systems for iterative demodulation of a message are provided. A first copy of the message is received to provide a first set of symbols associated with the message. A second copy of the message is received to provide a second set of symbols. The first copy is associated with a first interleaving pattern and the second copy is associated with a second interleaving pattern different from the first interleaving pattern. The first set of symbols and the second set of symbols are iteratively demodulated using extrinsic information associated with the first set of symbols for demodulation of the second set of symbols and extrinsic information associated with the second set of symbols for demodulation of the first set of symbols to provide a set of symbol estimates for the message. Transmit methods and systems for selective interleaving to generate the copies of the message in a retransmission based communication system are also provided.

Abstract: A differential phase detection device receives first through fourth detection signals from a photodetector and detects a differential phase signal therefrom, the differential phase detection device includes a slicer slicing and digitizing each of the detection signals with respect to a reference level. A synthesizer synthesizes the digitized detection signals and generates therefrom synthesis signals. A phase difference detector compares phases of the synthesis signals and outputs a first phase difference signal and a second phase difference signal. A matrix circuit processes the first and second phase difference signals to output the differential phase signal.

Abstract: A differential detector produces, for each symbol, a phase difference from a difference between phase information received from a phase detector and one-symbol-delayed phase information of the received phase information to deliver the phase difference to a differential circuit and a phase corrector. The one-symbol-delayed phase information is supplied to another differential detector, which produces, for each symbol, a phase difference from a difference between the one-symbol-delayed phase information and two-symbol-delayed phase information of the received phase information. The phase difference is fed to the differential circuit, which produces, for each symbol, phase-difference difference information from a difference between both of the received phase differences.

Abstract: On a transmitter side, a known bit inserting section 101 inserts a known bit having a predetermined length at a predetermined position of transmitting data, and a tail bit inserting section 102 inserts a tail bit thereto so as to generate frame data. Then, a frame length detecting section 103 detects a length of frame data, a convolutional coding section 104 convolutional codes the frame data, and a dummy bit inserting section 105 inserts a dummy bit to the frame data so as to obtain a transmitting signal. On a receiver side, a decoding section 205 divides a receiving signal into a convolutional coded portion, including a head portion to a tail of a known bit, and a subsequent portion so as to perform decoding on a receiver side. Then, an unnecessary bit removing section 206 removes the known bit, the tail bit, and the dummy bit from the decoded data.

Abstract: A multiple phase shift keying (MPSK) spread spectrum communications receiver uses weighted correlation techniques for carrier recovery and tracking. The receiver includes three subsystems: a synchronization system, a carrier tracking system, and a data demodulation system. To demodulate the received signal, the receiver requires a carrier frequency that matches the frequency of an associated transmitter as well as the sampling (or chip) and symbol clocks that are synchronized with those of the transmitter. In the disclosed receiver, the carrier tracking subsystem continually tracks the carrier frequency of the received signal using a tracking scheme that uses weighted correlation techniques. The weighted correlation technique combines signals from two correlator modules, an R-correlator module and a W-correlator module, to generate the correlation output. The R-correlator is similar to conventional correlators. The W-correlator, however, is unlike conventional correlators.

Abstract: Apparatus and methods for adaptively, reliably, and accurately measuring the frequency of an alerting or other signaling tone. A tone detector measures the frequency of a tone (continuous or pulsed) with a high degree of accuracy (e.g., to within 1 part in 10,000). Two lower order or smaller DFTs measure the energy level in two separate but intersecting frequency ranges. A simple ratio is determined from the relative energy measured from discrete Fourier transforms relating to each of the two separate frequency ranges, and an actual measured frequency is determined.

Abstract: The present invention relates to the use of complex non-linear elements in improvements to the recovery of a carrier phase reference from a modulated input signal where the modulation is in accordance with the M-PSK modulation format and where M has a value greater than 4 and the signal-to-noise ratio in the channel is low. A voltage-controlled oscillator is employed to generate first and second oscillations in phase quadrature with respect to each other. The modulated input signal is mixed with the first of the oscillations to detect the (I) signal component and the modulated input signal is mixed with the second of the oscillations to detect the (Q) signal component. A control signal is derived from the (I) and (Q) signal components as an estimate of the phase difference between the input signal carrier and the voltage-controlled oscillator.

Abstract: A phase shift keyed carrier recovery and demodulator circuit which includes a phase detector and subsequent feedback control loop circuitry which maintains an initial phase relationship. By comparing an incoming phase modulated carrier with the multiple phase outputs of a local oscillator, the circuit is able to generate a correcting signal which allows coherent phase tracking of the incoming phase modulated carrier. The phase detector produces a correction signal which allows the circuit to phase lock any two sequential phases of the locally generated phase outputs to phase positions on either side of the phase of the incoming phase modulated carrier. Once the circuit has obtained carrier phase lock, the multiple phases produced by the local oscillator will remain fixed (without phase change) relative to the initial detected phase of the incoming phase modulated carrier.

Abstract: A method for increasing data rates within a modulated signal is disclosed. Initially, a first and second bit streams are interleaved together to form an interleaved output bit stream. The interleaved output bit stream is modulated in a manner such that upon demodulation of the interleaved output bit stream according to an FSK modulation scheme only the first bit stream is recovered, and upon demodulation of the interleaved output bit stream according to a second modulation scheme, both the first and second bit streams are recovered.

Abstract: A DQPSK mapping circuit is disclosed which comprises: a parallel decoding circuit having inputs for decoding first to 2Nth bits of input data and one symbol period prior I and Q data which are prior by one symbol period from the present decoding cycle thereof through the inputs and outputting serial first to Nth I and Q data of the present decoding period in parallel, N is a natural number; and a FF circuit for supplying the Nth I and Q data to the inputs as the one symbol period prior I and Q data in the succeeding decoding cycle of the parallel decoding circuit. The parallel decoding circuit may comprise first to Nth decoders, an Mth decoder out of the first to Nth decoders decoding 2Mth bit and (2M-1)th bits of the input data and outputs of (M-1)th decoder, M being a natural number and M.ltoreq.N, wherein the first decoder decodes the one symbol period prior I and Q data and the first and second bits of the input data.

Abstract: In a radio communication system (100), enhanced communication capability is provided while maintaining standard channel modulation compatibility. At a transmitter (110, 200, 600), a first information signal is generated from data according to a predefined standard modulation scheme (212, 613). A second information signal is generated from data that provides supplemental information to the standard modulated data (213, 616). For transmission, the first and second information signals are combined into a composite signal (214, 619) that represents the first information signal when interpreted according to the predefined standard modulation scheme.

Abstract: A block phase estimator include a phase averaging circuit. A first embodiment of the phase averaging circuit includes a phase differencing circuit coupled to an averager input, a first modulo circuit coupled to the phase differencing circuit, a filter coupled to the first modulo circuit, and a summation circuit having an positive input and a negative input, the positive input being coupled to the averager input, the negative input being coupled to the filter. The phase averaging circuit further includes a second modulo circuit coupled to the summation circuit. An alternative embodiment of the phase averaging circuit includes a delay line having a plurality of taps coupled to an averager input and a plurality of first subtractor circuits, a first input of each first subtractor circuit being coupled to the averager input, a second input of each first subtractor circuit being coupled to a corresponding tap of the plurality of taps.

Abstract: An input quadrature modulation signal which is converted into a digital signal is converted into a complex baseband signal in a converter 7. A rough estimation of parameters of the signal is made in a rough signal correction unit 51. Using the estimates, the complex baseband signal is corrected. Utilizing a data detection of the corrected signal, a reference signal which corresponds to a transmitted signal is formed from the detected data in a generator 52. The reference signal and the corrected signal are used to estimate parameters in a fine parameter estimation unit 23.

Abstract: The along and perpendicular rails of a received signal (e.g., modulated using multi-phase shift keying) are rotated to compensate for frequency offsets between the carrier frequency of the received signal and the reference frequency of the local oscillator. The rotation angles are updated, based on the rotated along rail, during dotting sequences in the received signal. In one implementation, the dotting sequences are detected based on the rotated perpendicular rail. The beginnings of dotting sequences are detected by thresholding the average on the perpendicular rail, and the ends of dotting sequences are detected by analyzing the encoded data for non-dotting-sequence values. In a cordless phone application, different dotting sequences may be used to distinguish base-to-handset transmissions from handset-to-base transmissions.

Abstract: A direct conversion receiver for a radio system has an antenna and blocking filter connected to an amplifier. The input signal is split and mixed with an in-phase signal and a quadrature phase signal generated by an oscillator in a mixer circuit. An output from each mixer circuit is applied to a low pass filter and to an input of a limiting circuit. The output from each low pass filter is applied to respective circuits, a first of which is arranged to sum the in-phase and quadrature phase signals, and the second of which is arranged to subtract the in-phase and quadrature phase signals to generate a respective output signal having an axis intermediate the in-phase and quadrature phase signal axes. These signals, together with the in-phase and quadrature phase signals are passed through a limiting circuit respectively, to a decoder circuit for recovering the data. The output of the limiting circuits represent signals quantized to eight possible phase states separated by 45.degree..

Abstract: An apparatus for automatic gain control (AGC) of a digital QPSK demodulator is disclosed. The apparatus for automatic gain control of a QPSK demodulator comprising a variable gain amplifier for controlling an amplification gain of a QPSK-demodulated signal by a predetermined gain control signal comprises a signal magnitude estimator for estimating the magnitude of I and Q-channel signals in the QPSK demodulator by using the equation S.sub.mag =MAX.vertline.I.vertline.,.vertline.Q.vertline.)+1/2MIN(.vertline.I.vertli ne.,.vertline.Q.vertline.), and a control signal generator for generating a gain control signal according to the magnitude of the input signal outputted from the signal magnitude estimator, and outputting the gain control signal to a variable gain amplifier.

Abstract: Improved carrier recovery methods and apparatus suitable for use with QAM, QPSK and a wide variety of other modulation formats is described. In accordance with the invention, the phase error between received symbols, representing a frequency error, is determined using one of a plurality of techniques. The estimated frequency error is used to adjust the phase and/or frequency of a received carrier signal to achieve a frequency lock. The methods and apparatus of the present invention can be easily integrated into existing carrier recovery designs to supplement known frequency In accordance with a first embodiment of the present invention, the receipt of pairs of consecutive outer symbols is detected, a frequency error associated with each pair of consecutive symbols is generated, and the frequency error is compared to a selected threshold value to determine if it is a non-ambiguous estimate of the frequency error.