Abstract: An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: An integrated circuit device includes functional circuitry, and serializer/deserializer circuitry for serial communication with the functional circuitry. The serializer/deserializer circuitry includes phase interpolator circuitry for interpolating phases of a clock signal of the integrated circuit device. The phase interpolator circuitry includes a phase shift register having storage locations configured to represent the phases of the clock signal, and phase rotation control circuitry configured to decode a phase code signal to determine a shifting direction for phase selections in storage locations of the phase shift register. The phase rotation control circuitry may be configured to determine the shifting direction based on only the most significant bit and the second most significant bit of the phase code signal.

Abstract: This application provides a current measurement circuit including: an amplification unit, configured to amplify an electrical signal from the sensor unit; a comparison unit, configured to obtain an initial pulse signal based on a voltage signal output by the amplification unit and a preset voltage; a delay unit, electrically connected to the comparison unit and configured to delay an output of the initial pulse signal to obtain a target pulse signal; a resistance unit, wherein two terminals of the resistance unit are electrically connected to an input terminal of the amplification unit and an output terminal of the delay unit respectively, and the resistance unit is configured to charge and discharge the amplification unit based on the target pulse signal; and a calculation unit, electrically connected to the delay unit and configured to calculate a target current based on the target pulse signal output by the delay unit.

Abstract: Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.

Abstract: A reception device that communicates with a transmission device is provided. The reception device includes a reception circuit configured to receive a clock signal, a first data signal, and a second data signal from the transmission device, a signal synchronization circuit configured to adjust the phases of the first data signal and the second data signal, and generate a first synchronization data signal and a second synchronization data signal, a signal distribution circuit configured to adjust the phase of the clock signal and generate a first distributed clock signal and a second distributed clock signal, and adjust the phases of the first synchronization data signal and the second synchronization data signal and generate a first distributed data signal and a second distributed data signal, and an output circuit configured to process the first distributed data signal and the second distributed data signal.

Abstract: A synchronization method, suitable between a first electronic device and a second electronic device, includes following operations. A first pulse of a wireless signal sent from the first electronic device is received by the second electronic device. A first status of the second electronic device is determined. A second pulse of the wireless signal is received after the first pulse. A receiving time gap between the first pulse being received and the second pulse being received by the second electronic device is measured. A new status of the second electronic device is determined according to the receiving time gap and the first status of the second electronic device. Whether to synchronize a system clock on the second electronic device with the second pulse of the wireless signal is determined according to the new status.

Abstract: To obtain a position detection device capable of detecting highly accurate and robust position by suppressing affect of error detection of an edge, provided is a configuration for performing a validity determination of edges detected by binarizing an image signal (21) converted by a light-receiving element (3) for receiving light irradiated from a light source (1) toward a scale (2) having a code pattern, and performing position detection after removing the edges determined to be invalid as edges that have been affected by foreign matter and the like among the edges on which the validity determination has been performed.

Abstract: Technologies are described herein for compressing or decompressing data using polar codes. Some example technologies may receive a data string comprising a first set of symbols. The technologies may transform the data string into a generalized message comprising a second set of symbols by mapping the data string to the generalized message via an inverse of a transformation function. The technologies may identify, based on a polar code, fixed symbols of the generalized message. The technologies may generate a compressed data string by extracting the fixed symbols from the generalized message and concatenating the fixed symbols into the compressed data string. As a result, the generalized message may be transformed into the compressed data string.

Abstract: A wireless charging in-band communication system includes a transmitter module that formats a message using CRC calculation and attaches the results of the CRC calculation to the message for message error detection. The transmitter includes channel encoding for message error correction. A modulation module performs biphase modulation for DC balanced signals and impedance switching to change reflected impedance seen by the source. A synchronization module prepending the message with a synchronization sequence having Golay complementary codes. Moreover, the in-band communication includes a receiver module that receives the message from the transmitter module. The receiver module includes an impedance sensing circuit to detect changes in the reflected impedance of the transmitter module. The receiver module includes a front end filter used for pulse shaping and noise rejection.

Abstract: A method implemented in a device is disclosed for networking through signals transmitted across a shared medium network. The method starts with monitoring for a first signal on a shared medium of the shared medium network. The first signal is processed after it is received and while the first signal is being processed, a set of one or more signals is received on the shared medium. Then a set of one or more amplitude increases is determined, where each amplitude increase is from an earlier received signal to a later received signal. The set of one or more amplitude increases is compared to a threshold value and at least partially in response to the comparison, the device discards one or more signals from the first signal and the set of one or more signals.

Abstract: A method implemented in a device is disclosed for networking through signals transmitted across a shared medium network. The method starts with monitoring for a first signal on a shared medium of the shared medium network. The first signal is processed after it is received and while the first signal is being processed, a set of one or more signals is received on the shared medium. Then a set of one or more amplitude increases is determined, where each amplitude increase is from an earlier received signal to a later received signal. The set of one or more amplitude increases is compared to a threshold value and at least partially in response to the comparison, the device discards one or more signals from the first signal and the set of one or more signals.

Abstract: A Manchester code receiving circuit includes an analog circuit configured to convert an analog signal received through a communication transmission path, to a digital signal based on a Manchester code, and a characteristic compensating unit configured to compensate at least one of rise delay characteristics in which a rising time of the digital signal is longer than a falling time, and fall delay characteristics in which the falling time of the digital signal is longer than the rising time.

Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.

Abstract: One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.

Abstract: An RFID system using an M pulse amplitude modulation (M-PAM) or M quadrature amplitude modulation (M-QAM) scheme using a plurality of load-modulators, a plurality of antennas, and a communication method thereof are provided. The RFID system includes: an RFID tag; and a reader device communicating with the RFID device, wherein the RFID tag includes: N load-modulators an N antennas communicating with the reader device in any one scheme of M-pulse amplitude modulation (M-PAM) and M-quadrature amplitude modulation (M-QAM) in which modulation of an M level is performed and operated corresponding to the M level.

Abstract: A method for impulsive noise mitigation using an adaptive blanker based on BPSK modulation system includes estimating narrowband Middleton parameters of impulsive noise from signals received for a fixed time period; calculating a threshold using the estimated narrowband Middleton parameters; operating the first blanker to suppress impulsive noise from the signal received at a given point of time through the comparison of the SNR value of the received signal and the threshold. Further, the method includes operating the second blanker to suppress impulsive noise from the received signal through the comparison of the summation of the threshold and the SNR value with an absolute value of the received signal, when the SNR value is above the threshold.

Abstract: Systems and methods for detecting unused channels in a cognitive radio system are described. In one method, data is communicated on a particular channel for a secondary receiver. In addition, a set of channels is iteratively scanned by collecting samples for each channel and for each iteration of the scanning. Here, iterations of the scanning progressively removes channels from the set of channels based on the collected samples and updates states of the channels in the set based on the collected samples to obtain a set of candidate channels. In response to detecting a pre-determined condition, communications on the particular channel are precluded and at least one of the candidate channels is evaluated by collecting additional samples on each of the channels. Further, at least one of the candidate channels is selected based on the evaluation for utilization by the one or more secondary receivers for data communication.

Abstract: In a control unit for passenger protection and a method for triggering passenger protection devices, a Manchester-coded signal is supplied by an interface and the Manchester-coded signal is decoded by a coding unit, so that an analyzer unit performs the triggering of passenger protection devices as a function of the decoded signal. The decoding unit uses a shift register structure for decoding and oversampling for the Manchester-coded signal.

Abstract: There is provided an information processing apparatus, including a signal receiver that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value, wherein the first bit value is represented by first amplitude values, the second value is represented by a second amplitude value, and polarity of the encoded signal amplitude value is reversed in each period, a conversion processor performs conversion to add a delayed signal that is delayed by delaying a signal received by the signal receiver by one period of the received signal, an inversion processor that performs inverse processing of the conversion on the signal output from the conversion processor, and an input data decoder that decodes an input data by determining the first and second values based on the amplitude value of the signal output from the inversion processor.

Abstract: A method (500) of demodulation, the method comprising the steps of receiving (510) a radio frequency signal, converting (520) the received radio frequency signal to a baseband signal, performing (530) symbol timing recovery on the baseband signal, and demodulating (540) the baseband signal. The baseband signal comprises alternating symbols spaced therebetween at an alternating first interval length and a second interval length, where the first interval length and second interval length are dissimilar. Communication units and a method of modulation are also described.

Abstract: A communication receiver and a receiving method are disclosed. An analog front-end device samples a receiving signal and generates a sampled signal. A signal detector detects presence of the receiving signal according to the sampled signal. A symbol timing recovery (STR) unit determines an optimal symbol sampling point according to a zero-crossing point of the sampled signal when the receiving signal is present, and then generates a recovered symbol based on an optimally chosen sampled value according to the optimal symbol sampling point.

Abstract: One embodiment of the present invention includes a decoder system that decodes a bi-phase modulated signal to generate an output code. The system includes a first filter associated with a first logic state configured to generate a first dot product of a plurality of consecutive digital samples of the bi-phase modulated signal and a respective plurality of tap weights of the first filter. The system also includes a second filter associated with a second logic state configured to generate a second dot product of the plurality of consecutive digital samples of the bi-phase modulated signal with a respective plurality of tap weights of the second filter. The system further includes a comparator configured to compare the first and second dot products and to provide the output code as a bit having one of the first logic state and the second logic state based on the comparison.

Abstract: A method and modem are provided for obtaining an optimized efficiency of an Orthogonal Frequency Division Multiplex (OFDM) data transmission, such as for power line communication, for example. The length or duration of a guard interval or cyclic prefix in an OFDM symbol is newly selected at each start-up of a modem while initializing or preparing the OFDM data transmission. The length of the guard interval can be given by the number of samples in a time-discrete representation, and the value of such number of samples that is retained for the subsequent data transmission can be selected from a plurality of pre-determined possibilities based on an evaluation of a channel quality of a communication channel including a physical line to which the modem is connected. Hence, the selected value depends on actual transmission conditions, and the optimization potential offered by a more flexible handling of system parameters is exploited to meet changing conditions on the physical line.

Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.

Abstract: A method includes receiving a first wireless signal and demodulating data in the first wireless signal using a first demodulation technique. The method also includes receiving multiple second wireless signals simultaneously (where the second wireless signals interfere to produce an interfered signal) and demodulating data in the interfered signal using a second demodulation technique. The method could also include (i) determining that a single transmitter transmitted the first wireless signal and selecting the first demodulation technique in response and (ii) determining that multiple transmitters transmitted the second wireless signals and selecting the second demodulation technique in response. Determining that the single transmitter transmitted the first wireless signal could include determining that a fundamental frequency of the first wireless signal is below a threshold.

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: A method for interference reduction is described. A sampling frequency is selected for a digital-to-analog converter (DAC) so that images within a DAC output signal do not interfere with one or more receivers. A sample rate is adjusted of an input signal that is provided to the DAC to match the sampling frequency for the DAC.

Abstract: An automatic zero-crossing signal demodulation and classification device for rapidly identifying an unknown modulation in a signal identifies an unknown modulation in a signal, demodulates differential phase shift keying signals and automatically recognizes certain phase shift keying signals. This is accomplished by eliminating the unknown term fc in differential phase estimation, introducing a symbol rate tracking mechanism, applying hysteresis nonlinearity to eliminate the phase shaping effect and using a weighted average to estimate the phase difference. Better estimates are accomplished by using the hysteretic nonlinear function to detect the zero-crossing points in eliminating the false detecting of the zero-crossing points caused by the additive noise, and calculating differential phase without directly using the center frequency to simplify the estimation process.

Abstract: Digital data encoding and decoding method and system is provided. The data encoding includes encoding a frame signal into a bit stream, including detecting a specific bit pattern in the bit stream when the frame signal is present, generating a control signal in respect to the specific bit pattern, and encoding the bit stream into one or more marks and one or more spaces so that encoded data include a unique encoding pattern for the frame signal. The data decoding includes detecting at least one of mark and space from encoded data, recovering a bit stream from the encoded data when the at least one of mark and space is present, detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present, and recovering the frame signal from the encoded data.

Abstract: A galvanic isolator having a transmitting section and a receiving section is disclosed. The transmitting section includes a frame input circuit, a data encoder, and a data transmitter. The frame input circuit receives an input data frame that includes a plurality of input binary bits. The data encoder encodes the input binary bits to generate an encoded data frame that includes a sequence of encoded binary bits in which two successive encoded binary bits represent each input binary bit. The successive encoded binary bits representing a 1 are 01 or 10, and the successive encoded binary bits representing a 0 are 00 or 11. The sequences are chosen to maximize the number of transitions in the encoded data frame. A data receiver recovers the encoded data frame by examining successive pairs of encoded data bits using a clock that is reset on the edges in the encoded data frame.

Abstract: A method is provided that contemplates including filtered decode values in an RDS/RBDS output signal. The filtered decode values are generated from reliable values. The reliable values are generated from corresponding received values from each of at least two groups of RDS/RBDS data in an RDS/RBDS input signal. The method also comprises preventing an error correction code (ECC) unit from modifying the filtered decode values in the RDS/RBDS output signal.

Abstract: A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, ?) rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.

Abstract: A communication system comprising one or more transceiver units of a first type and one or more transceiver units of a second type capable of communicating with the transceiver units of the first type; each transceiver unit of the first type comprising: a frequency comparison unit for comparing the frequency of a signal received from a transceiver unit of the second type with a reference frequency; a feedback signal generator for generating a feedback signal dependent on the result of that comparison; and a transmitter for transmitting that signal to the transceiver unit of the second type; and each transceiver unit of the second type comprising: a local frequency reference unit on which the frequency of signals transmitted by it are dependent; and a frequency adjustment unit for receiving the feedback signal and adjusting the local frequency reference unit in dependence on the feedback signal.

Abstract: An ASK modulator for reducing the difference in the On/Off ratio due to the difference in the envelope frequency components without deteriorating an adjacent wave leakage power is disclosed. The ASK modulator includes a Manchester encoder that generates Manchester-encoded signals by applying Manchester encoding to an input signal sequence, a waveform shaping unit that generates band-limited encoded signals from the Manchester-encoded signals, and detects and limits minimum values of waveforms of the band-limited encoded signals to generates shaped signals, and a modulating unit that modulates carrier waves based on the shaped signals.

Abstract: A network device includes a first demodulation path to recover a header portion of a data packet. A second demodulation path recovers a payload portion of the data packet. The second demodulation path includes a down sampler to down sample a payload portion of the data packet. An equalizer equalizes an output of the down sampler. A correlator receives an output of the equalizer. A demodulation controller selects the output of the equalizer or an output of the correlator based on the header portion.

Abstract: A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.

Abstract: A mixer circuit accumulates I signal (digital signal of first channel) having its band limited by low-pass filter and first carrier signal to perform two-phase shift keying modulation thereon. An adder adds fundamental-wave component of bit clock signal BCK into Q signal (digital signal of second channel) having its band limited by the another low-pass filter to obtain a resultant added-up signal. Another mixer circuit accumulates the added-up signal and second carrier signal to perform two-phase shift keying modulation thereon. Output signals of the mixer circuits are input to another adder so that they may be added up to obtain a QPSK signal as a modulated quadrature signal. The QPSK signal contains frequency signals whose frequencies are a sum of bit clock frequency and carrier frequency and a difference between them. When demodulating, the carrier signal and the bit clock signal are reproduced using the frequency signals.

Abstract: Data message sync patterns for use in a network that utilizes Manchester (Bi-Phase) signal encoding with an embedded sync pattern. The sync pattern of the invention differs from conventional sync patterns for Manchester (Bi-Phase) type signal encoding, allowing greater deviation of the local oscillators in the communication network without increase in the communication network bandwidth.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: An apparatus and method for improving a symbol error rate of an M-ary phase shift keying (M-PSK) system having a quadrature error are provided. The apparatus includes: a conversion parameter detector that detects a conversion parameter and converts a symbol decision region using the quadrature error and at least one pair of first received symbols; and a converter & determiner converting a pair of second received symbols using the detected conversion parameter, and determining a transmission symbol according to a symbol of the converted pair of second received symbols. An increase in a symbol error rate due to the quadrature error can be prevented and the quadrature error can be easily estimated.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: A signaling method reduces bandwidth requirements and signaling delays normally associated with sending text-based signaling messages over a wireless links. An application at a transmitting endpoint generates and sends a binary-encoded signaling message, along with a binary interpreter that enables the receiving endpoint or SIP server to construct a text-based message from the binary encoded message. The binary-encoded signaling message may include references to a saved state, or to a dictionary to enable compression of the message. The signaling method can be used with any text-based signaling protocol, such as the Session Initiation Protocol, the Session Description Protocol, and the Real Time Streaming Protocol.

Abstract: A receiver supports a single carrier (SC) form of modulation and a multi-carrier form of modulation such as orthogonal frequency division multiplexing (OFDM). Upon receiving a signal, the receiver determines a maximum fluctuation range (MFR) as a function of at least a fourth-order cumulant of a received signal; and classifies a modulation type of the received signal as a function of the determined maximum fluctuation range. After determining the modulation type of the received signal, the receiver switches to that modulation mode to recover data from the received signal.

Abstract: A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state responsive to the recovered clock signal. A switch pulse signal asserts when the decision time signal is active and the stored phase and current phase of the data signal have the same logic value, which is stored and cleared responsive to the recovered clock signal. A data output is decoded from a decision pair of phases responsive to the recovered clock, preamble found and decision time signals. The stored and current phases of the data input signal are selected to be the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and, otherwise, the stored phase and inverted stored phase are selected.

Abstract: A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also includes a clock generator for generating a replacement clock signal, first and second latches controlled by the replacement clock signal to store the data taken, respectively, from the decoded data signal and from a signal that represents the sign of the signal at the output of the decoder, and a selection circuit for capturing, at each pulse edge of a clock signal that is offset with respect to the replacement clock signal, either the stored data originating in the sign signal in the case of loss of the previous data capture clock pulse edge at the output of the clock comparator, or the stored data originating in the data signal.

Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.

Abstract: A method of decoding, in one particular embodiment, an IEC 60958 biphase coded data stream comprising determining the maximum period in the data stream without a transition; determining a first threshold corresponding to a period of time less than the maximum period and greater than the data bit period; determining whether a considered transition corresponds to a data bit or a preamble based on the time between the considered transition and a preceding transition compared with said first threshold; and if the considered transition corresponds to a data bit, determining the data bit based on the considered transition and the preceding considered transition.

Abstract: A delay section delays a detected signal by less than one bit time in the NRZ data. A subtraction section performs subtraction between a delayed signal and the detected signal, and outputs a resultant signal. A clock extraction section extracts, from crossing points of a subtracted signal, crossing points whose time interval is more than or equal to (Tb??) and less than or equal to (Tb+?) (wherein 0<??Tb/8, 0<??Tb: Tb is one bit time in the NRZ data), and outputs a synchronous signal synchronized with the extracted crossing point. A clock recovery section synchronizes a clock signal with the phase of the synchronous signal, and outputs a data clock signal. A determination section determines the polarity of the subtracted signal outputted from the subtraction section in accordance with the data clock signal, and outputs the determination result as the NRZ data.