Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.

Abstract: A bit synchronizer (16) that includes a tapped delay line (38) connected to a plurality of timing hypothesis circuits. A control and adjudication circuit (50) is connected to the timing hypothesis circuits, and compares outputs of the timing hypothesis circuits and selects one. Each of the timing hypothesis circuits includes a sum-and-dump summer (112) that is connected to outputs of the tapped delay line (38). The timing hypothesis circuits further include an absolute value circuit (46) and an averaging circuit (48). A select switch (60) is connected to the summers (112) and receives a switch control signal from the control and adjudication circuit (50). A threshold test circuit (62) compares the selected output signal to a threshold value and outputs a mark or space symbol.

Abstract: A comparator compares the voltage of an envelope signal by applying envelope detection to a signal amplitude-modulated by a digital signal encoded by a Manchester code with the terminal voltage of a capacitor constituting a filter for converting the output current of a charge pump into a voltage. The charge pump charges/discharges the capacitor by discharging or charging current, according to the result of the comparison.

Abstract: A hard disk drive (HDD) holds data using a biphase scheme. A plurality of matched filters are used to detect binary data represented by the biphase pattern without the need for synchronous sampling or equalization.

Abstract: A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1, St2; Stp) are determined, and a decision is made as to whether the respective bit combination (St1, St2; Stp) is a valid combination (Sg1, Sg2; Sgp) or an erroneous one (Sf1, Sf2; Sfp). Probability values (Sw1, Sw2; Swp) are determined that decide which parts of the erroneous bit combination (Sf1, Sf2; Sfp) are probably true and/or which are probably false. Next, a corrected bit combination (Sk1, Sk2; Skp) is formed from the existing information. Finally, a second digital signal (d2) is generated as an output signal, whose data states are formed either from the valid bit combination (Sg1, Sg2; Sgp) or from the corrected bit combination (Sk1, Sk2; Skp).

Abstract: An apparatus and method for providing control signals, comprising a processor coupled to a memory, for generating a signal sequence. The processor encodes the signal sequence into a plurality of symbols using a 5 pulse position modulated (5 PPM) scheme. Advantageously, the last position of each symbol encoded under the 5 PPM scheme is set to a low bit. The symbol sequence represents a signaling protocol having a payload portion and a header portion, wherein the header portion comprises a plurality of fields for defining the payload portion. The payload portion indicates keyboard characters or coordinates for a pointing device.

Abstract: A method for decoding Manchester data is provided that includes receiving input data comprising at least two transition types. Each transition of a specified transition type in the input data is detected. For each pair of consecutive transitions of the specified transition type, a length between the consecutive transitions is determined. Output data is generated based on the length.

Abstract: A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determined using the decoded clock signal.

Abstract: A biphase code detector and method for implementing the same. In accordance with one embodiment, the biphase code detector includes a receiver input for receiving a biphase encoded signal. The biphase encoded signal is a stream of unit bit cells each having a logic value encoded as a mid-bit transition between a first half-symbol signal component and a second half-symbol signal component. A demodulator demodulates the first and the second half-symbol components of a received unit bit cell. The biphase code detector further includes a delta detector that generates a difference signal corresponding to the difference between the demodulated values of the first and second half-symbol components to determine the logic value of the received unit bit cell. In a preferred embodiment, the biphase code detector incorporates the delta detection function within an optimum receiver that integrates demodulation and detection functionality.

Abstract: A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approximating a number of least common multiples in the corresponding sample size. A preamble is detected from the sample lengths of a sequence of the samples and decoded to determine an expected logic level of the clock following a transition at an expected clock edge. The expected level of the clock is gated with the biphase encoded data to generate a control signal in advance of the opening of the time window. The control signal is then gated with the biphase encoded data to extract the clock edge after the time window has opened.

Abstract: A method and system for decoding a biphase-mark input stream is disclosed. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream to generate decoded data and storing the decoded data in a data buffer; reading, by an audio out module, the decoded data from the data buffer at a rate determined by a programmable clock; using the timing information from the receiver module to calculate a sampling frequency of the input stream; and adjusting a frequency of the programmable clock to substantially match the sampling frequency so that the audio out module reads the decoded from the buffer at substantially the same rate that the receiver module inputs the decoded data into the data buffer.

Abstract: In a digital audio interface signal demodulating apparatus (DDAp) that adds a preamble (PA) and additional information (V, U, C, P) to a digital audio signal (Sda) and demodulates into a digital audio interface signal (Sdai) after subjected to bi-phase modulation for transmission, based on both of positive and negative edges of a reference clock (Src) having a frequency higher than twice a minimum inverse frequency (1/T) of said digital audio interface signal (Sdai) and not necessarily synchronizing with said digital audio interface signal (Sdai), a modulation period (nT) of the digital audio interface signal (Sdai) is decided, and a decision signal (Sj) is generated. Furthermore, based on the decision signal (Sj), the: preamble (PA) is detected, and based on the detected preamble (PA), an audio signal (Sda) is obtained from said decision signal (Sj) through demodulation.

Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.

Abstract: A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of a respective digital control signal. This is done by way of a shift register including a number of latches equal to the number of the cells of the delay line. An output tap of each latch of the shift register controls a respective delay cell of the delay line. A digital state machine in the control loop prevents any undesired oscillations.

Abstract: The invention relates to a system for transmitting packets from interactive terminals to a head station. The terminals intended for consumers are provided with local oscillators which are not very accurate and use carriers having frequency errors which are relatively large with respect to the theoretical reference value (Fp). The invention provides an improvement of the reception of signals having such a frequency shift at the receiver end. To this end, the invention provides a method of estimating the frequency error &Dgr;{circumflex over (f)}, which consists of rapidly obtaining the maximum value of a discrete error function denoted Z(&Dgr;{circumflex over (f)}) for a given accuracy (Acc) by computing the function Z(&Dgr;{circumflex over (f)}) for a minimal number of points.

Abstract: Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal having the frame synchronization signal incorporated into the bi-phase mark signal as a phase-shift. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.

Abstract: A digital television transmitting system is presented having a recovery circuit for recovering non-return to zero (NRZ) data pulses and transport clock pulses from a biphase-mark serial data pulse stream and wherein the recovered NRZ data pulses and the recovered transport clock pulses are applied to modulation and amplifying circuits for broadcasting by an antenna. The recovery circuit includes a first circuit for receiving the biphase-mark serial pulse stream and providing therefrom a train of first clock pulses wherein the rising edge of each the biphase-mark pulse corresponds with a rising edge of one of the first clock pulses. A second circuit receives the biphase-mark serial data pulses and the first clock pulses for providing therefrom a train of de-serialized data pulses each having a rising edge corresponding with a rising edge of one of the first clock pulses.

Abstract: The radio transmission circuit comprises 16 antenna elements in a broadside array. A carrier wave is routed to the 16 elements and the phase to each element is adjusted to direct the transmitted wavefront toward a selected receive point. Prior to transmission, however, the carrier to each element is independently modulated by a two-state (0/&pgr;) phase shifter. Each of the 16 carriers is modulated with the first 16 orthogonal Walsh waveforms (a digital counterpart of the Fourier Transform). The output power levels at all antennas are equal, only the phase of the RF carriers change. Depending upon the sign conditions (inverted or noninverted) for the various 16 modulation waveforms, a pulse position modulation (PPM) signal is transmitted in which the pulse can occupy one of 16 time positions.

Abstract: Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal that is defined by a specific modulation protocol and the frame synchronization signal is incorporated into the bi-phase mark signal as a protocal violation. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.

Abstract: Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

Abstract: Before digital data impulses are transmitted from a transmitter to a receiver that includes a data acquisition signal generator, at least one synchronizing impulse (syn1, . . . ) is transmitted for synchronizing the transmitter with the receiver with regard to a sync frequency that is repeatedly updated to provide a current accepted sync frequency. The at least one synchronizing impulse and the data impulses are Manchester encoded which combines timing (synchronizing) and data signals. An impulse flank change occurring centrally in an impulse width is used as a synchronization point of time. Stepping pulses occurring between two consecutive synchronization points of time are counted and the resulting count is used to determine the sync frequency in response to the occurrence of a synchronizing impulse and at a synchronization point of time. A time shift or delay occurs between data impulses and synchronization points of time.

Abstract: A low jitter method for extracting clock or data from a serial digital bitstream generates from a digital decoder a window signal from the serial digital bitstream by sampling the serial digital bitstream with a sample clock signal. The window signal envelops a specified transition of the serial digital bitstream, and is used as a gate input to an AND circuit to extract the clock signal or desired data from the bitstream without introducing jitter. The clock signal may then be used to clock out data previously extracted by the digital decoder.

Abstract: An improved digital decision directed phase locked loop (DD-PLL) for use with short block codes using phase shifting keying (PSK) modulation. The improvement involves a conventional digital phase lock loop which is modified to base its loop corrections on the results obtained by decoding the short block code rather than on a symbol by symbol basis as is customary in conventional DD-PLLs. The improved method of loop corrections involves retaining the symbol data pending the decoder's decision, derotating the retained data in accordance with the decoded result, and integrating the derotated data to form a composite estimator upon which to base the loop correction. In its preferred embodiment, the invention uses an (8, 4) biorthogonal code with quatenary PSK.

Abstract: A circuit for demodulating a signal having a temporal mixture of different modulation schemes applied thereto includes a synchronization-word-detection unit which detects synchronization words included in the signal, and generates first and second position signals, based on the detected synchronization words, indicative of respective predetermined positions in the signal, a first selection unit which selects the first position signals during a first period, and selects the first position signals and the second position signals during a second period, and a carrier-reproduction unit which carries out frequency capturing during the first period by using the first position signals selected by the first selection unit, and carries out phase capturing during the second period by using the first position signals and the second position signals selected by the first selection unit, thereby reproducing a carrier.

Abstract: An apparatus for receiving broadcasting signals, which includes a tuner for receiving a digital audio broadcasting signal, a channel decoder for obtaining audio information data, service information data and control information based on the digital audio broadcasting signal received by the tuner, a source decoder for causing the audio information data to be subjected to a decoding processing to produce a digital audio signal, a digital audio signal transmission processor for obtaining a first digital transmission signal based on the digital audio signal, a service data producing portion for obtaining service data based on the control information and the service information data, a service data transmission processor for obtaining a second digital transmission signal based on the service data, a switch for deriving selectively the first and second digital transmission signals, and a digital output transmitter for forwarding a digital transmission output obtained based on one of the first and second digital tra

Abstract: The method and associated apparatus of the present invention decodes digital signals by appropriately weighting the respective noise portions of the two phase segments generated by the detector, such as an APD in an optical communications system, such that the digital signal can be reliably decoded despite the presence of multiplicative noise induced by the detector. The detector detects a digitally encoded communications carrier signal having a waveform defining first and second portions. The detector then generates an electrical signal in response to the digitally encoded communications carrier signal. The electrical signal has two phase segments, namely, one phase segment corresponding to the first portion of the digitally encoded communications carrier signal and another phase segment corresponding to the second portion of the digitally encoded communications carrier signal. Each phase segment also includes a respective noise portion.

Abstract: A delay-locked loop which phase-locks the reference clock of crystal oscillation by certain identical delay units for generating certain precise time-sharing phase signals. These time-sharing phase signals can be utilized to recover the clock/data. The advantages of the invention, when comparing with the typical phase-locked loop, are: (1) it can be easily stabilized; (2) the phase error does not accumulate; (3) the loop filter requires only one capacitor, which reduces the area of chip; (4) no additional loop filter is need in multiport application, which further reduces the area of chip.

Abstract: A horizontal period counter 3 determines one bit period of bi-phase codes by measuring the period of a horizontal scan line immediately preceding one containing bi-phase codes to be decoded. An edge pulse generator 6 generates edge pulses at rising and falling edges of inputted bi-phase codes. A compensating pulse generator 7 is triggered by the edge pulse and generates a compensating pulse in a predetermined period, which is shorter than one bit period of the bi-phase codes and longer than one half bit period, according to one bit period that has been determined. A rise judging circuit 11 generates sampling pulses by superimposing compensating pulses on the edge pulses. The bi-phase codes are decoded according to the sampling pulses.

Abstract: A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.

Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.

Abstract: A circuit for decoding an input signal includes a measurement circuit having an input to receive a timing clock signal that is asynchronous with clocking of the input signal, to measure duration of a plurality of pulses received on the input signal in relation to frequency of the timing clock signal and a decode circuit to decode the input signal into digital data. In one embodiment, the circuit may include a servo mechanism for generating the timing clock signal to have a frequency that varies in response to variations in frequency of clocking of data on the input signal. The servo mechanism may include a digitally controlled oscillator and a feedback circuit, to control the digital frequency of the digitally controlled oscillator in response to variation of clocking of data on the input signal. The invention permits use of all digital components for decoding digital audio data encoding using biphase-mark encoded data according to the SPDIF or AES/EBU standards.

Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: A bi-phase signal is output from BPSK demodulator; by a pair determining circuit and a clock reproducing circuit, a clock signal corresponding to a former half bit of two half bits constituting a data pair of the bi-phase signal is reproduced; a carrier pulse immediately following the clock signal is generated by a carrier extracting circuit; using the carrier pulse and a carrier pulse obtained by delaying the pulse signal by a half bit period as a sampling clock, the bi-phase signal is subjected to AD conversion by AD converting circuit; two AD converted data values different in time are input to a subtraction circuit, and a result of subtraction between data pairs of bi-phase signals is obtained; thus sign of a bi-phase signal is determined.

Abstract: A method and apparatus for recovering clock and data signals from a Manchester code is provided. The present invention uses a phase lock loop with a digital delay line wherein an adjustable delay is introduced into the Manchester coded signal for synchronizing the coded signal with the local clock of the decoding apparatus. This delaying technique enables the present invention to successfully receive Manchester coded signals having substantial jitter. The present invention also conserves energy by reducing power consumption when no signals are present.

Abstract: The method and associated apparatus of the present invention decodes optical signals by appropriately weighting the respective noise portions of the two phase segments generated by the photodetector, such as an APD, such that the optical signal can be reliably decoded. The photodetector detects an optical signal having a light portion and a dark portion. The photodetector then generates an electrical pulse in response to the optical signal. The electrical pulse has two phase segments, namely, one phase segment corresponding to the light portion of the optical signal and another phase segment corresponding to the dark portion of the optical signal. Each phase segment also includes a respective noise portion. The optical decoding method and apparatus determines a weighting factor based upon the respective noise portions of the two phase segments. Thereafter, at least one phase segment is weighted by the weighting factor. For example, the noisier phase segment can be attenuated by the weighting factor.

Abstract: The Manchester coder/decoder of the invention includes the following modules. A synchronization signal generation module (11), gives the clocks' start signal. A module (12) for the synchronization and generation of clocks generates the transmission/coding and decoding clocks and a low frequency clock. A decoding module (13) includes a flip-flop driven by the decoding clock. The decoding is a simple sampling of the input signal of the Manchester coded data which is to be decoded during the reception phase. A coding module (14) carries out an "OR EXCLUSIVE" function between the input signal to be coded in Manchester code and the transmission clock.

Abstract: The present invention provides a system and method for using a single digzed component of an analog signal to be converted into a pair of digital signals used to re-establish the analog signal. A low level serial transceiver transforms a first analog signal into a first digital signal representing the complement of the first analog signal. The first digital signal is propagated through an electronic interface circuit such as a matrix switch or through some electronic circuit used to detect characteristics of the analog signal. In response to receiving the first digital signal, a logic circuit generates a second digital signal representing the analog signal, and also outputs the first digital signal. In response to receiving the first and second digital signals, a retimer generates a third digital signal comprising a series of pulses.

Abstract: A digital audio signal demodulator which demodulates an input digital audio interface format signal inputted with asynchronous serial bits to a non-return to zero (NRZ) signal, corrects error per frame, and provides the error-corrected NRZ signal, being synchronized with a digital-to-analog conversion control signal. According to the demodulator, data in the digital audio interface format signal except a header region is demodulated in a demodulating section and the demodulated NRZ data is converted into parallel NRZ data by a serial-parallel conversion section. The even parity error of the parallel NRZ data is corrected in accordance with error check pulses from an error detecting and latch section, and the error-corrected parallel NRZ data is converted into serial data by a parallel-serial conversion section to be provided to a following digital-to-analog converter.

Abstract: A phase-locked loop circuit recovering original clock information and original stream of binary data both from Manchester-coded data is disclosed. The phase-locked loop circuit comprises first, second, and third exclusive-OR circuits each with two inputs and an output. The phase-locked loop circuit further comprises a controlled oscillator that generates two local clock signals that are phase shifted from each other, preferably by an amount of 90.degree., with the first being at 0.degree. phase shift. The 0.degree. clock signal is applied to one input of the first exclusive-OR circuit having Manchester-coded data at its other input. The 90.degree. phase shifted clock is applied to one input of the second exclusive-OR circuit having Manchester-coded data at its other input. The output of each of the first and second exclusive-OR circuits, after passing through associated circuitry, is applied to the third exclusive-OR circuit.

Abstract: In a circuit for a demodulator of a radio data signal in a radio receiver, the multiplex signal in digital form is mixed into the baseband, in two phase positions shifted 90.degree. with respect to each other, after band-pass filtering, together with a reference carrier generated at a sampling clock rate produced in the radio receiver, thus producing a first and a second mix signal. A first and a second auxiliary signal with, respectively, a sine waveform and a cosine waveform are produced. The first mix signal is multiplied by the first auxiliary signal, and the second mix signal by the second auxiliary signal. The results of these multiplications are added together, producing a first output signal. The first mix signal is multiplied by the second auxiliary signal, and the second mix signal by the first auxiliary signal, and the results subtracted from each other, thus producing a second output signal.

Abstract: A Manchester decoder and clock recovery circuit for recovering Manchester encoded data and a clock synchronized with the incoming data. The circuit uses an oversampling rate of eight times the data rate, and a reduction in circuit elements to reduce the circuit power consumption requirements. The circuit operates in a search mode and in a tracking mode. A clock phase generator produces eight phase clocks, used by a sampling and majority vote circuit to determine the decoded data value. During the tracking mode, the phase of the synchronized clock can be adjusted during data reception.

Abstract: Binary signals that are transmitted by Manchester coding and frequency modulation are demodulated based on the behavior of the phase or complex vector value of the received signal. The polarities of the information bits may be determined by measuring the phase excursions in the middles of the Manchester symbols. A phase reference is established from a plurality of candidate phase references as a basis for comparison of the mid-symbol phase. The phase can be measured at the start-points and end-points of the symbols and averaged, or measured a plurality of times during each symbol period to generate a reference phase.

Abstract: A digital decoder for a biphase-mark encoded serial digital signal detects edges in the encoded serial digital signal by sampling with a sample clock to produce a blivet signal. The blivet signal is filtered by a one-bit digital lowpass filter to recover a decoded clock signal and to generate a transition window signal. The blivet and window signals are used to detect whether there is a transition within each bit interval defined by the decoded clock signal. A decoded serial digital signal has a logical one for each bit interval in which a transition occurs, and a logical zero otherwise.

Abstract: For a demodulator for radio data signals, where transmission of these signals is carried out through phase shifting of a suppressed subcarrier, where a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, the amplitude-limited signal having a subcarrier frequency is transformed into digital sampling values, if necessary by additional filtering, and the sampling values are supplied to at least one phase control loop for deriving a bit clock signal.

Abstract: A one-bit differential detector for a GMSK signal operates independently of an offset frequency. In particular, a decision signal used by a decision circuit to distinguish between logic "0" and logic "1" is always equal to sin[.DELTA..phi.(T)]. The inventive detector has an improved bit error rate performance in comparison to the prior art.

Abstract: An optical code recognition unit (OCRU) for recognising a predetermined n-bit optical code sequence coded using the Manchester code format, has an n-way splitter (7) having an input and n parallel outputs (7a). A plurality of gates (9a, 9b, 9c, 9d) are associated with the splitter outputs (7a), respective pairs of splitter outputs leading to each of the gates ( 9a, 9b, 9c) via a respective optical combiner (8a, 8b, 8c), and any remaining single splitter output leading directly to its gate (9d). Each of the splitter outputs (7a) is subject to a different delay of m half bit periods, where m=0 to 2(n-1), the values of m being chosen such that, if a predetermined optical code sequence is applied to the splitter input, the `1`s in the outputs of each of the pairs of splitter outputs (7a) reach the associated AND gates (9a, 9b, 9c) and the `1` in any remaining single splitter output (7a) reaches its AND gate (9d) at predetermined times such that all the gates are turned on.

Abstract: A device for demodulating a signal modulated on two axes in phase quadrature using a .pi./4-QPSK type digital modulation technique employing alternately two phase-shifted constellations. The device includes: a voltage-controlled oscillator (28) supplying a local signal substantially at the carrier frequency; a demodulator means using the local signal and supplying, after filtering (30, 31), the phase component P and quadrature component Q of the demodulated received signal; a phase controller (32) producing a control signal (39) for controlling the oscillator (28) and including a phase estimator (33) producing a phase estimation signal E (35) involved in control of the oscillator (28), the phase estimation signal being derived from the phase component P and quadrature component Q of the demodulated received signal.

Abstract: In a demodulator for radio data signals the transmission of which is made by phase-keying of a suppressed subcarrier the occurence of transient times is avoided in that the received signal of subcarrier frequency is transformed into a first square wave signal (A) and that a second square wave signal of subcarrier of frequency is formed which is brought into such a time relationship to the first square wave signal that by means of a comparison of both square wave signals a phase information for the first square wave signal (A) is obtained. Demodulator can be implemented by means of only digital components.

Abstract: In a demodulator for use in the Radio Data System (RDS) as defined by the European Broadcasting Union, transmission of these signals is carried out through phase shift modulation of a suppressed subcarrier, a multiplex signal, which contains a signal with the frequency of the subcarrier passes through a band-pass filter and an amplitude limiter, and the amplitude-limited signal, having a carrier frequency, is sampled at a sampling frequency that is a multiple of the frequency of the subcarrier. The sampling values are summed over a preset portion of one period of the subcarrier. The summed sampling values are supplied to a digital signal processing circuit.

Abstract: An improved apparatus and method for determining the carrier frequency in a biphase coded signal such as the course acquisition code signal in a global position sensing system. The described system may also be used for other purposes. The described system is based on use of the conventional data signal squaring or frequency doubling step to remove biphase coding but performs a series of frequency reducing steps prior to applying the Fourier transformation sequence. The frequency reducing steps include heterodyne mixing and signal averaging. These frequency-reducing steps diminish the speed and capacity requirements imposed on the Fourier transformation sequence and thereby decrease the cost and complexity of the overall system.