Abstract: An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.

Abstract: A phase interpolator includes a sampling circuit configured to capture samples of an output of the phase interpolator, a delay circuit configured to delay sampling by the sampling circuit, a comparator configured to provide a comparison signal that indicates whether voltage of the samples exceed a reference voltage, and a counter responsive to the comparison signal and configured to provide an output that controls an operating point of the phase interpolator. The phase interpolator my further include a pair of driver circuits configured to concurrently drive the output of the phase interpolator.

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

Abstract: A test device includes a comparison circuit configured to receive a plurality of input signals and generate a plurality of comparison signals based on the plurality of input signals; and a field programmable gate array (FPGA) configured to recover clock data, based on the plurality of comparison signals, wherein the FPGA includes a sampling circuit configured to generate a plurality of sample data signals by sampling the plurality of comparison signals; an edge extraction circuit configured to generate a plurality of edge data signals, based on logic values of bits in the plurality of sample data signals; an edge combining circuit configured to generate combined edge data by performing a logic operation on the plurality of edge data signals; and a filter circuit configured to recover the clock data by filtering the combined edge data.

Abstract: A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

Abstract: The present disclosure proposes an adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver and a method for operating the same. An adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver according to the present disclosure comprises a Continuous-Time Linear Equalizer (CTLE) to boost high-frequency components of an input signal, a Track and Hold (T&H) circuit to track and hold an output of the CTLE, and a sampler, wherein the sampler includes a Decision Feedback Equalization (DFE) sampler to equalize an output of the T&H circuit and sample an output of the T&H circuit in a DFE sampling clock phase; and a DATA sampler to sample a signal equalized by the DFE sampler in a DATA sampling clock phase, wherein the DFE sampling clock phase differs from the DATA sampling clock phase.

Abstract: A fraud prevention server and method. The fraud prevention server includes an electronic processor and a memory. The memory includes an online application origination (OAO) service. The electronic processor is configured to perform feature encoding on one or more categorical variables in a first matrix to generate one or more feature encoded categorical variables, generate a second matrix including the one or more feature encoded categorical variables, generate a feature encoded OAO model by training an OAO model with the second matrix, receive information regarding a submission of an online application on a device, determine a fraud score of the online application based on the information that is received and the feature encoded OAO model, the feature encoded OAO model being more precise than the OAO model, and control the client server to approve, hold, or deny the online application based on the fraud score that is determined.

Abstract: The present disclosure provides for calibrating clock signals in an unmatched data input system. In various embodiments, an unmatched data input system uses multi-delay circuits to calibrate a clock signal distributed to various input/outputs in the unmatched data input system. These multi-delay circuits can include coarse delay circuits and fine delay circuits that provide a broad range as well as accurate delay capabilities. Through the use of these multi-delay circuits, the unmatched data input system can optimally align a clock signal with its associated data signal across multiple input/outputs.

Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.

Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.

Abstract: A time-to-digital converter (TDC) provided according to an aspect of the present disclosure identifies existence of jitter in either one of two periodic signals received as inputs. In an embodiment, jitter is detected by examining a first sequence of counts and a second sequence of counts respectively for a first periodic signal and a second periodic signal received as input signals, with the first sequence of counts representing respective time instances on a time scale at which a first sequence of edges with a first direction of the first periodic signal occur, and the second sequence of counts representing respective time instances on the time scale at which a second sequence of edges with the first direction of the second periodic signal occur.

Abstract: A memory system includes a memory device configured to monitor a first oscillator count value for a write data strobe signal for sampling a data signal at a first temperature and a second oscillator count value for the write data strobe signal for sampling the data signal at a second temperature, and a memory controller configured to determine a weight based on the first oscillator count value and the second oscillator count value, wherein the memory device is configured to sample the data signal by adjusting a delay on a transfer path of the write data strobe signal according to a change in temperature of the memory device based on the weight.

Abstract: Methods, systems, and apparatuses related to configured dual register clock driver (RCD) devices on a single memory subsystem using different configuration information are described. In some examples, configuration of the two RCD devices with different configuration information may include use of a serial data bus to receive and store first RCD configuration data, which is provided to both of the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices may receive second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

Abstract: A receiver convolutes each of a real component and an imaginary component of each polarization of a polarization-multiplexed reception signal with an impulse response for compensating for frequency characteristics of the receiver and a complex impulse response for wavelength dispersion compensation, and generates, as input signals, the convoluted real component and imaginary component of each polarization and phase conjugations thereof, for each polarization.

Abstract: A test and measurement device includes an input for receiving a test waveform from a Device Under Test (DUT), where the test waveform has a plurality of input level transitions, a selector structured to respectively and individually extract only those portions of the test waveform that match two or more predefined patterns of input level transitions of the test waveform, a noise compensator structured to individually determine and remove, for each of the extracted portions of the waveform, a component of a jitter measurement caused by random noise of the test and measurement device receiving the test waveform, a summer structured to produce a composite distribution of timing measurements with removed noise components from the extracted portions of the test waveform, and a jitter processor structured to determine a first noise-compensated jitter measurement of the DUT from the composite distribution. Methods of determining noise-compensated jitter measurements are also disclosed.

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

Abstract: A time-to-digital converter (TDC) includes a count logic and a digital core. The count logic generates a first sequence of counts representing a first sequence of edges of a first periodic signal, and a second sequence of counts representing a second sequence of edges of a second periodic signal. The digital core generates a sequence of outputs representing the phase differences between the first periodic signal and the second periodic signal from the first sequence of counts and the second sequence of counts. Each output is generated from a pair of successive edges of the first direction of one of the periodic signals and an individual one of the other periodic signal occurring between the pair, and the output is set equal to the minimum of difference of the individual one with the first value of the pair and the individual one with the second value of the pair.

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

Abstract: A clock data calibration circuit including a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators and a data selector is provided. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generate a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data signal groups according to selected clocks to generate a plurality of second sampled data signal groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.

Abstract: A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device receives data bits for storage. Based on the data bits, the memory device generates a codeword that includes the data bits, parity bits, and placeholder bits. The memory device balances the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device stores at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device is able to re-invert the appropriate packets to recover the original data bits.

Abstract: Disclosed is a secure and adaptive waveforms multiplexing system in advanced-level wireless communication systems (such as 5G and beyond systems).

Abstract: A method for operating a memory system includes: performing a first training operation for alignment between a clock and a data strobe signal; performing a second training operation for alignment between the data strobe signal and the data; detecting an error of the second training operation; and adjusting a delay value of the data strobe signal in response to the detection of the error.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: Disclosed are a device and method for realizing data synchronization. The device may include a synchronization circuit for a plurality of radio frequency (RF) chips, configured to realize work clock synchronization among the plurality of RF chips; and/or, a synchronization circuit for a plurality of channels in a single chip, configured to realize data synchronization among the plurality of channels in the single chip.

Abstract: Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device receives data bits for storage. Based on the data bits, the memory device generates a codeword that includes the data bits, parity bits, and placeholder bits. The memory device balances the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device stores at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device is able to re-invert the appropriate packets to recover the original data bits.

Abstract: Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.

Abstract: An input device comprises a plurality of sensor electrodes and a processing system coupled to the plurality of sensor electrodes. The processing system comprises a sensor driver. The sensor driver comprises clock synchronization circuitry, a blocking pulse generator, and a sensor module. The clock synchronization circuitry is configured to receive an external clock signal, and synchronize an internal clock signal with the external clock signal. The blocking pulse generator is configured to generate a first blocking pulse based on the internal clock signal. The sensor module comprises sensing circuitry and is configured to pause acquisition of a resulting signal from a sensor electrode based on the first blocking pulse.

Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

Abstract: Embodiments of the application can provide a method, a device, and a terminal for controlling a jitter in network communication, belonging to the technical field of communication. The method includes: generating trigger information, where the trigger information is for triggering switching of a jitter control strategy for the network communication, the jitter control strategy includes a first control strategy based on a first cached data amount and a second control strategy based on a second cached data amount, and the first cached data amount is smaller than the second cached data amount; switching the jitter control strategy to a target control strategy in response to the trigger information; and controlling the jitter in the network communication by using the target control strategy, where the target control strategy is the first control strategy or the second control strategy corresponding to the trigger information.

Abstract: Systems, devices, and methods related to selecting a sample phase of a signal are disclosed. A method includes sampling a signal including a plurality of symbols with a plurality of different sample phases to obtain sample values of each of the plurality of symbols at each of the plurality of different sample phases. The signal is received from a shared transmission medium. The method also includes determining an edge sample phase of the plurality of different sample phases that corresponds to edges of the symbols based on the sample values. The method further includes determining a center sample phase of the plurality of different sample phases based on the determined edge sample phase, and using the determined center sample phase to determine values of the symbols.

Abstract: According to certain embodiments, a method in a wireless device includes generating a signal comprising repeating segments for transmission in a subslot duration transmission time interval (TTI) to a network node. The signal comprising the repeating segments is transmitted to the network node in the subslot duration TTI.

Abstract: A method for synchronizing baseband clocks in an OFDMA wireless microphone system is disclosed. An example method includes receiving a plurality of pilot subcarriers from an audio transmitter. The method also includes determining a timing offset estimate based on the pilot subcarriers. The method further includes determining a tuning value by passing the timing offset estimate through a proportional-integral controller. The method still further includes determining a modified reference signal by modifying a reference oscillator based on the tuning value. And the method yet further includes controlling (i) an audio sample clock and (ii) an antenna data clock based on the modified reference signal.

Abstract: A method for operating a memory system includes: performing a first training operation for alignment between a clock and a data strobe signal; performing a second training operation for alignment between the data strobe signal and the data; detecting an error of the second training operation; and adjusting a delay value of the data strobe signal in response to the detection of the error.

Abstract: A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.

Abstract: The present disclosure generally relates to reducing time for interface transmitter training based upon an assumed identify of the training partner. It is unlikely for a drive PHY to link up with multiple PHYs per power cycle. Therefore, it is a fair assumption that when there is no power loss, the drive PHY is connected to the same host device. The drive can therefore change its behavior based on the assumed identity of the host from previously exchanged identify frames, if the previously used training algorithm was sufficient for interface transmitter training for the particular host. The drive will go directly to the correct training algorithm without the need to do a PHY reset using a training algorithm that is tailored to the host and thus reduce interface transmitter training time.

Abstract: A technique for managing data storage begins at a predetermined offset relative to a chunk of data received for writing, and identifies a span of contiguous regions of the chunk that contain identical data. The technique replaces the span of contiguous regions of the chunk with a single instance of a region of the contiguous regions. The technique persistently stores a shortened version of the chunk with the single instance replacing the span of contiguous regions.

Abstract: A jitter determination method for determining at least one jitter component of an input signal is described, wherein the input signal is generated by a signal source. The method comprises: receiving the input signal; determining a step response based on the decoded input signal, the step response being associated with at least the signal source; and determining a data dependent jitter signal based on the determined step response and based on the decoded input signal. Further, a measurement instrument is described.

Abstract: Embodiments of methods and systems for operating a communications device that communicates via inductive coupling are described. In an embodiment, a method for operating a communications device that communicates via inductive coupling involves detecting a falling signal edge corresponding to a received signal at the communications device based on a falling signal edge threshold, detecting a rising signal edge corresponding to the received signal based on a rising signal edge threshold, where the rising signal edge threshold is independent from the falling signal edge threshold, and decoding the received signal based on the detected falling signal edge and the detected rising signal edge. Other embodiments are also described.

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract: The disclosed embodiments provide a system that detects unwanted electronic components in a target asset. During operation, the system generates a sinusoidal load for the target asset. Next, the system obtains target electromagnetic interference (EMI) signals by monitoring EMI signals generated by the target asset while the target asset is executing the sinusoidal load. The system then generates a target EMI fingerprint from the target EMI signals. Finally, the system compares the target EMI fingerprint against a reference EMI fingerprint for the target asset to determine whether the target asset contains unwanted electronic components.

Abstract: A signal analysis method for determining at least one perturbance component of an input signal is described, wherein the perturbance is associated with at least one of jitter and noise.

Abstract: A jitter determination method for determining at least one jitter component of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving and/or generating probability data containing information on a collective probability density function of a random jitter component of the input signal and a other bounded uncorrelated jitter component of the input signal; determining a standard deviation of the random jitter component based on the probability data; determining a RJ probability density function associated with the random jitter component based on the standard deviation; and determining a OBUJ probability density function associated with the other bounded uncorrelated jitter component, wherein the OBUJ probability density function is determined based on the probability data and based on the probability density function that is associated with the random jitter component. Further, a measurement instrument is described.

Abstract: A temperature sensor using a poly-phase filter may include: a poly-phase filter suitable for receiving a divided clock, and having passive elements coupled to have one or more negative poles and one or more positive zeros; a comparator suitable for generating a reference clock by comparing potentials of first and second filter voltages outputted from the poly-phase filter; a phase frequency detector suitable for outputting an up or down signal by comparing the phase of the reference clock to the phase of a comparison clock; a current supply unit suitable for supplying and integrating a charge current under control of the up or the down signal; an oscillator suitable for outputting an oscillation signal; a divider suitable for generating the divided clock and the comparison clock; and a buffer suitable for inverting and non-inverting the divided clock and outputting the inverted and non-inverted divided clocks.

Abstract: Processes and systems described herein are directed to determining efficient sampling rates for metrics generated by various different metric sources of a distributed computing system. In one aspect, processes and systems retrieve the metrics from metric data storage and determine non-constant metrics of the metrics generated by the various metric sources. Processes and systems separately determine an efficient sampling rate for each non-constant metric by constructing a plurality of corresponding reduced metrics, each reduced metric comprising a different subsequence of the corresponding metric. Information loss is computed for each reduced metric. An efficient sampling rate is determined for each metric based on the information losses created by constructing the reduced metrics. The efficient sampling rates are applied to corresponding streams of run-time metric values and may also be used to resample the corresponding metric already stored in metric data storage, reducing storage space for the metrics.

Abstract: A variable delay interface configured to introduce a controllable, variable delay between a radio equipment controller and a radio equipment is provided. The interface includes a variable rate change filter, VRCF, having a signal input, a signal output and a rate control input. The VRCF is configured to receive a rate control signal at the rate control inputs and sample an input signal received at the signal input at a sampling rate controlled by a rate control signal to produce a VRCF output signal. The sampling rate is one of greater than and less than a sampling rate of the input signal. The VRCF has a first delay. The interface includes a first in first out, FIFO, buffer having an input and an output, the FIFO buffer configured to store samples of the VRCF output signal received at the FIFO buffer.