Synchronizers Patents (Class 375/354)
  • Patent number: 10771104
    Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 8, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peng Wang, Fredrik Berggren
  • Patent number: 10768920
    Abstract: Software updates within one or more regions of a multi-tenant cloud are coordinated. Tenant vs. tenant conflicts, tenant vs. infrastructure provider conflicts, and conflicts between security and another priority are identified and resolved using a shared update coordinator, update priority specifications, and availability specifications. An infrastructure update request may be presented to tenants for approval. Postponed infrastructure updates may be prioritized higher. Preventing exploits of zero-day vulnerabilities may be prioritized over meeting availability targets. Updates may be merged to reduce downtime, even when the updates originate from independently controlled entities. Maximum downtime, minimum fault domains, minimum virtual machines, permitted update start times, and other availability criteria may be specified. Updates may be preempted, or allowed to complete, based on their relative priorities.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 8, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marcus Fontoura, Mark Russinovich, Yunus Mohammed, Pritesh Patwa, Avnish Kumar Chhabra, Ziv Rafalovich
  • Patent number: 10764612
    Abstract: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: September 1, 2020
    Assignee: DISGUISE TECHNOLOGIES LIMITED
    Inventor: Ashraf Nehru
  • Patent number: 10735006
    Abstract: A functional clock generator, including: an oscillator configured to generate an oscillator clock having an oscillator clock frequency; a control value generator configured to generate control values to ramp the oscillator clock frequency between a first frequency and a second, higher frequency; a Phase-Locked Loop (PLL) configured to generate a PLL clock having the second frequency; and a selector configured to switch between selecting the oscillator clock and the PLL clock as a functional clock when the oscillator clock frequency and the PLL clock frequency are substantially equal.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rex Kho, Udo Elsholz
  • Patent number: 10727966
    Abstract: In various implementations, provided are techniques for distributing network time across a network using multiple grand masters (e.g., master time keepers). These techniques include having multiple grand masters simultaneously providing time to the network. Simultaneous means that all the grand masters are active at the same time, and none are designated as backups. In various implementations, the nodes in the network can simultaneously synchronize to network times provided by more than grand masters so that the nodes can obtain more than one network time. Using these multiple network times, nodes configured as clients can determine one network time. The client devices can then use the single network time in applications that require a time.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Erez Izenberg, Nafea Bshara
  • Patent number: 10720958
    Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peng Wang, Fredrik Berggren
  • Patent number: 10708107
    Abstract: Phase noise (PN) is suppressed in an OFDM signal. In an initial iteration, an estimation of the PN samples in an OFDM signal vector is produced and the OFDM signal is demodulated using the initial estimation of the PN to generate constellation symbols for the initial iteration. In an additional iteration, an Inverse Fast Fourier Transform of constellation symbols generated in a preceding iteration is calculated to reconstruct preceding samples of the transmitted signal vector. A PN effect on the reconstructed samples is estimated. A next estimation of the PN in a next signal vector is produced based on the estimated PN effect on the reconstructed samples. The next signal vector is demodulated using the next estimation of the PN to generate constellation symbols for the additional iteration. A predetermined maximum number of additional iterations may be used.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 7, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peyman Neshaastegaran, Ming Jian
  • Patent number: 10708751
    Abstract: An apparatus, such as a user equipment or a vehicle, may receive a signal associated with vehicle-to-everything (V2X) communication. The apparatus may determine a total energy that corresponds to the received signal, such as by measuring the energy on one or more resources. The apparatus may determine a fractional energy associated with a first technology of the total energy, such as by detecting a sequence associated with a first technology included in the received signal and determining the energy with which the detected sequence is received. The apparatus may determine presence of a second technology based on the determined fractional energy.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shailesh Patil, Kapil Gulati, Gaurav Gupta
  • Patent number: 10694228
    Abstract: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 23, 2020
    Assignee: DISGUISE TECHNOLOGIES LIMITED
    Inventor: Ashraf Nehru
  • Patent number: 10685691
    Abstract: A storage device includes a first memory chip including a first input pad configured to receive a first input signal, a first initializing circuit configured to generate a first initializing signal, a first input delay circuit configured to delay the first input signal by a first time to generate a first output signal, a first output pad configured to receive the first output signal and output the first output signal, a first clock delay circuit configured to delay the first initializing signal by a second time to generate a first clock signal, a second clock delay circuit configured to delay the first clock signal by a third time to generate a second clock signal, a first latch configured to store the first input signal based on the first clock signal, and a second latch configured to store the first input signal based on the second clock signal.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong Kil Jung
  • Patent number: 10677648
    Abstract: Whether an optical delay on a space optical path is within a light emission cycle is accurately determined without narrowing a range of a measurable distance in the light emission cycle. A DFF 1 that divides an output pulse of a first DLL (121) by two to provide a first time offset and a DFF 2 that divides an output pulse of a second DLL (122) by two to provide a second time offset are included, and at least following mathematical formulas (1) and (2) are satisfied: O1=m·T½??(1) 0<O1<(N?1)·T1??(2) (where, m?1), when a time corresponding to a difference between the first time offset and the second time offset is O1 and the first cycle is T1.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 9, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Ikuta, Takuma Hiramatsu, Takayuki Shimizu, Hideki Sato
  • Patent number: 10659099
    Abstract: A page scanning device configured to generate a sequence mask for an expected frequency hopping sequence, select a first tone among a plurality of detected tones, first determine whether the first tone is included within an expected hop sequence, generate a first tone template in response to determining that the first tone is included within the expected hop sequence, align the first tone template with the plurality of detected tones based on the first tone, second determine whether the first tone template matches the plurality of detected tones, and detect a valid frequency hopping sequence in response to determining that the first tone template matches the plurality of detected tones.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ian Appleton, Donald Guy, Michael Cowell, Fei Tong
  • Patent number: 10642570
    Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 5, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Patent number: 10630275
    Abstract: Embodiments of a constant-on-time pulse generator circuit for a DC-DC converter, a pulse width calibration circuit for a DC-DC converter, and a method for operating a constant-on-time pulse generator circuit for a DC-DC converter are disclosed. In an embodiment, a constant-on-time pulse generator circuit for a DC-DC converter includes serially connected digital buffers and a latch circuit having a set terminal, a reset terminal, and an output terminal. The set terminal and the reset terminal are coupled to the serially connected digital buffers. The latch circuit is configured to output a pulse signal with a constant pulse width through the output terminal.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP B.V.
    Inventor: Shufan Chan
  • Patent number: 10579578
    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James Brian Johnson, Brent Keeth
  • Patent number: 10574344
    Abstract: A data transmission system in a communication network comprising a data modulator comprises: a first part at the level of the collection point part comprising: an NCR module taking account of an external absolute time reference to reconstitute a network clock, a transmitter module receiving the value of a time reference to be inserted into the data packet to be transmitted and transmitting to the NCR module an information item on an instant of synchronization for the receiver, a second part at the level of the radiofrequency part of a gateway comprising; a receiver module, a module for reconstructing a clock locally, a module for inserting a time reference into a data packet received by the receiver before transmission of the data via the satellite, the first part and the second part exchange encapsulated data.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 25, 2020
    Assignee: THALES
    Inventors: Mathieu Arnaud, Jean-Luc Almeida, David Arnaud, Cédric Baudoin, Jacques Decroix, Erwan Corbel
  • Patent number: 10528517
    Abstract: Systems and methods for power conservation in a SOUNDWIRE audio bus provide a pulse density modulated (PDM) audio stream at an audio source to an encoder. The encoder has a plurality of encoding states corresponding to bit patterns. The encoder compares bits of the audio stream to available bit patterns and selects an encoding state. The audio source sends the encoding state to an audio sink and then sends data to the audio sink based on encoding using the selected encoding state. The data is sent over a non-return to zero inverted (NRZI) audio bus. As the audio stream changes bit patterns, the encoder may select different more efficient encoding states and provide updates to the audio sink of changes in the encoding state.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sandeep Kumar, Suman Kumar, Lior Amarilio
  • Patent number: 10484165
    Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Rupesh Singh, Ankur Bal
  • Patent number: 10484046
    Abstract: The systems and methods for a twisted pair transceiver with correlation detection includes a transceiver system operating on a cable. The transceiver system includes a receiver to obtain one or more data samples related to one or more encoded data symbols. The transceiver system further includes a first correlation filter to generate a first correlation output based on the one or more data samples, and a second correlation filter to generate a second correlation output based on the one or more data samples. The transceiver system further includes a detector. The detector compares the first correlation output with the second correlation output, generates an output data bit based on a comparison result, and sends the output data bit for data decoding.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: November 19, 2019
    Assignee: Marvell International Ltd.
    Inventors: Brett McClellan, Kuoruey Han
  • Patent number: 10476448
    Abstract: Digital pre-distortion may be provided. First, a characterization for input matching circuitry may be determined. Next, a characterization for non-linearity of an amplifier connected to the input matching circuitry may be determined. Then, a distortion correcting signal may be generated from an input signal based on the determined characterization for the input matching circuitry and the determined characterization for the non-linearity of the amplifier. The generated distortion correcting signal may then be provided to the input matching circuitry.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 12, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Hang Jin, John T. Chapman
  • Patent number: 10469886
    Abstract: A system controller, preferably implemented as a cloud service, enables the synchronization of display devices located at geographically remote locations relative to one another. A display and control devices are provided at each of a plurality of sites, with one or both of the devices being capable displaying the transmitted show. The control device enables the system controller to determine local relative delays in the show and to control the temporal reproduction of said transmitted show by said display device so as to achieve a substantially synchronized reproduction of the show at each of the sites.
    Type: Grant
    Filed: April 6, 2013
    Date of Patent: November 5, 2019
    Assignee: Minerva Networks, Inc.
    Inventor: Fabrizio Capobianco
  • Patent number: 10448156
    Abstract: A content delivery apparatus includes an external input portion, a content reception portion and a delivery portion. To the external input portion, first content having at least a fundamental component is inputted. The content reception portion receives second content having a fundamental component and an extended component. When delivering the first content, the delivery portion delivers the fundamental component of the first content to a client apparatus more than once.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 15, 2019
    Assignee: Yamaha Corporation
    Inventor: Osamu Kohara
  • Patent number: 10425895
    Abstract: A preamble detector for a Bluetooth Long Range includes a receiver for forming baseband samples from Bluetooth packets and a preamble detect controller for enabling and disabling power to the receiver. Where the preamble duration is Tcyc, the preamble detector turns on for a preamble detect time T1 and turns off for a duration T2, where T2=Tcyc?2*T1. A series of hierarchical decisions is made on sequentially increasing intervals of time based on an accumulated correlation result of correlating the baseband samples against a SYNC sequence to power the receiver back down before the end of the T1 period when the accumulated correlation result is below a threshold and continues to a subsequent correlation interval when the accumulated correlation result is above a threshold, where the threshold is established to have at least a 20% false alarm rate for preamble detection.
    Type: Grant
    Filed: December 16, 2018
    Date of Patent: September 24, 2019
    Assignee: Redpine Signals, Inc.
    Inventors: Partha Sarathy Murali, SuryaNarayana Varma Nallajaraju
  • Patent number: 10404317
    Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The Cell ID can be determined from the first cyclic shift and the second cyclic shift.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 3, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peng Wang, Fredrik Berggren
  • Patent number: 10383056
    Abstract: Low power consumption networking method for 802.15.4e wireless device “WD” taking 4-20 mA loop power, including: a “WD” taking loop power; constructing a WD oriented to ultra-low power consumption; the WD implementing unidirectional time synchronization based on preceding wireless network; on basis of preceding time synchronization, completing neighbor discovery; the WD interacting with the wireless network; and pausing a preceding procedure according to a power monitoring result of an energy storage monitoring module.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: August 13, 2019
    Assignees: SHENYANG INSTITUTE OF AUTOMATION OF THE CHINESE ACADEMY OF SCIENCES, SHENYANG INSTITUTE OF AUTOMATION, GUANGZHOU, CHINESE ACADEMY OF SCIENCE
    Inventors: Haibin Yu, Peng Zeng, Jinchao Xiao, Chuanzhi Zang, Zhongwen Li
  • Patent number: 10367660
    Abstract: A rate determination apparatus 1 includes a reception unit 2 configured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unit 3 configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unit 4 configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unit 5 configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kichung Kim, Hiroyuki Okada, Naohiro Matsui, Tomoaki Hirota
  • Patent number: 10361686
    Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 23, 2019
    Assignee: MEDIATEK INC.
    Inventors: Min-Hang Hsieh, Wei-Min Hsu, Jen-Hang Yang
  • Patent number: 10348416
    Abstract: Embodiments disclosed herein provide systems and methods for acoustically transferring information between systems. In a particular embodiment, a method provides identifying information for acoustic transfer and determining an amount of time corresponding to the information. The method further provides acoustically transmitting a signal at a first time and, upon the amount of time elapsing since the first time, acoustically transmitting the signal at a second time.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 9, 2019
    Assignee: Avaya Inc.
    Inventors: Azaria Cohen, Ori Modai
  • Patent number: 10341969
    Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Ganesh Dabak, Eko Nugroho Onggosanusi, Badri Varadarajan
  • Patent number: 10324879
    Abstract: An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: David D. Cadigan, Samuel R. Connor, Michael A. Cracraft, William V. Huott, Adam J. McPadden, Anuwat Saetow, Gary A. Tressler
  • Patent number: 10318447
    Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
  • Patent number: 10320593
    Abstract: A receiver for data communication may include: an input buffer suitable for generating plural comparison signals by differentially comparing plural input signals; a de-serializer suitable for generating plural groups of de-serialized signals by de-serializing the plural comparison signals at a preset de-serialization ratio; a D flip-flop suitable for generating plural delayed signals by delaying last de-serialized signals of the respective plural groups of de-serialized signals by a preset time; a symbol decoder suitable for comparing current and previous states of the plural comparison signals and for generating plural symbol signals based on a preset state diagram defining a correspondence relationship between the plural symbol signals and changes between current and previous states of the plural comparison signals.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 11, 2019
    Assignees: SK hynix Inc., KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Chul Woo Kim, Sung Jun Moon, Sang Su Lee
  • Patent number: 10305493
    Abstract: A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 28, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shingo Seto, Satoshi Suda
  • Patent number: 10297046
    Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventor: Bimal Poddar
  • Patent number: 10236946
    Abstract: A beamforming device is provided. The beamforming device comprises: a beam deriving unit for deriving, among multiple reception beams, a first reception beam receiving, from a terminal, the first largest reception signal and a second reception beam receiving, from the terminal, the second largest reception signal; and a control unit for estimating the direction of the terminal on the basis of a ratio value between the size of the reception signal received through the first reception beam and the size of the reception signal received through the second reception beam.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 19, 2019
    Assignee: SK TELECOM CO., LTD.
    Inventors: Haesung Park, Changsoon Choi
  • Patent number: 10212016
    Abstract: Embodiments of the disclosure disclose a synchronization method and apparatus on the basis of a field broadband bus architecture of an industrial Internet, where the bus architecture includes a bus controller, at least one bus terminal, and a two-wire bus, and the bus controller and the bus terminal are connected over the two-wire bus to constitute a bus system, the bus system communicating using OFDM technology; and in the method, all the bus terminals refer to the bus controller, and when receiving a signal, and transmitting a signal, they adjust a clock for a received signal, and a signal to be transmitted, adaptively according to the downlink pilot signal so as to synchronize their clocks and symbols with the bus controller, and adjust a transmission time for the signal to be transmitted so that all the devices in the bus system are synchronized.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 19, 2019
    Assignee: KYLAND TECHNOLOGY CO., LTD
    Inventors: Zhihui Shao, Jing Shi, Hui Zhong, Yi Huang
  • Patent number: 10211972
    Abstract: A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: February 19, 2019
    Assignee: Rambus Inc.
    Inventors: Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang-Wook Paul Park, Marcus Van Ierssel
  • Patent number: 10193723
    Abstract: The present invention relates to a method of transmitting and a method of receiving signals, and corresponding apparatus. One aspect of the present invention relates to a method of obtaining a field for indicating a time de-interleaving depth from a layer 1 (L1) header of preamble symbols.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 29, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Woo Suk Ko, Sang Chul Moon
  • Patent number: 10156843
    Abstract: Disclosed is a technology for detecting an erroneous operation of a task scheduler of a battery management system. An apparatus for detecting an erroneous operation according to an exemplary embodiment includes: a first scheduler module configured to control a first task to be executed for every first period; a second scheduler module configured to control a second task to be executed for every second period; a task counting unit configured to increase the first counting value for the first scheduler module in accordance with the first period whenever the first task is executed, and increase the second counting value for the second scheduler module in accordance with the second period whenever the second task is executed; and an erroneous operation detecting unit configured to detect erroneous operations of the first scheduler module and the second scheduler module based on the first counting value and the second counting value.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 18, 2018
    Assignee: LG CHEM, LTD.
    Inventor: Hyunchul Lee
  • Patent number: 10114407
    Abstract: A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: October 30, 2018
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Markus Bakka Hjerto, Arne Wanvik Venas
  • Patent number: 10116433
    Abstract: A circuit arrangement for clock and data recovery comprises a control unit, a phase-locked loop circuit and a sampling unit. The control unit is configured to derive a first reference signal and a second reference signal from an input signal. Furthermore, the control unit is configured to derive a common reference signal from one of the first reference signal and the second reference signal, selected depending on a mode of operation of the circuit arrangement. The phase-locked loop circuit is configured to generate an oscillator signal based on the common reference signal. The sampling unit is configured to extract a recovered data signal from the input signal.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 30, 2018
    Assignee: ams AG
    Inventor: Tibor Kerekes
  • Patent number: 10117244
    Abstract: Uplink carrier selection is performed for reduced bandwidth machine type communication devices by reserving a portion of a wideband carrier for machine type communication traffic to provide a plurality of narrowband uplink carriers in the wideband carrier, and by selecting a narrowband uplink carrier of the plurality of narrowband uplink carriers for use by a machine type communication device.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 30, 2018
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Rapeepat Ratasuk, Jun Tan
  • Patent number: 10108563
    Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changho Yun, Sung-Joon Kim
  • Patent number: 10091270
    Abstract: A method and system to enable interoperability between Internet enabled devices and online applications without traditionally agreeable on device standard formats between the manufacturer and applications ahead time. The application is able to connect, control, and actuate newly added devices at runtime.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 2, 2018
    Assignee: Safenet International LLC
    Inventor: Joseph Y. Fang
  • Patent number: 10083137
    Abstract: A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: September 25, 2018
    Assignee: Atmel Corporation
    Inventors: Frédéric Schumacher, Guillaume Pean, Renaud Tiennot
  • Patent number: 10069513
    Abstract: Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data converter configured to convert a serial data packet into N parallel data packets and outputting the N parallel data packets; a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detecting a data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of N bits set in advance; and an error compensation unit configured to detect and compensate for a skew between parallel clock and data.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 4, 2018
    Assignee: Hanwha Techwin Co., Ltd.
    Inventor: Young Su Lee
  • Patent number: 10045316
    Abstract: A method and device for sending a synchronization signal and a method and device for synchronization between base stations, include: determining, by a synchronization source base station according to a synchronization level of the synchronization source base station, a resource for sending an NLRS for clock synchronization between base stations, and according to the determined resource. In this way, one NLRS for clock synchronization between base stations is configured on each synchronization source base station, and the NLRS is sent on a resource determined according to a synchronization level, so that a synchronization base station that acquires the NLRS can determine the synchronization level of the synchronization source base station according to a resource for sending the NLRS.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 7, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuan Xia, Juan Zheng, Xiaoan Fan, Sha Ma, Qiang Li
  • Patent number: 10044376
    Abstract: Disclosed is a transmitting apparatus that includes an uplink transmitting unit that generates at least two carrier transmission signals carrier and generates transmission control data corresponding to the carrier transmission signals, a Radio Frequency Front End (RFFE) that transmits the at least two carrier transmission signals, and a transmission controller including a storage unit and decoders. The transmission controller activates a decoder corresponding to transmission control data output from the uplink transmitting unit, and the activated decoder accesses information of the storage unit to control wireless transmission of the RFFE.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Changjoon Park, Il-Soo Kim, Youngil Son, Dong Woo Lee
  • Patent number: 10038545
    Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 31, 2018
    Assignee: XILINX, INC.
    Inventors: Zhaoyin D. Wu, Winson Lin, Yu Xu, Geoffrey Zhang
  • Patent number: 10014041
    Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nikunj Khare, Rajeev Suvarna, Gregory A. North, Maneesh Soni