Synchronizers Patents (Class 375/354)
  • Patent number: 11151392
    Abstract: Embodiments of the present disclosure provide a method and an apparatus for camera calibration processing, a device for vehicle control and a storage medium. In the method according to the embodiments of the present disclosure, at least one pair of images collected by a camera and a vehicle position at a collection time of each of the images are acquired during a process of a vehicle travelling along a straight line, where each pair of images includes images taken by the camera at two different positions, and two images in each pair of images include a common static feature point. A current installation angle of the camera is calculated according to the at least one pair of images and the vehicle position at the collection time of each of the images.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 19, 2021
    Assignee: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Tong Wu, Gaifan Li, Xun Zhou, Shirui Li
  • Patent number: 11140097
    Abstract: Some embodiments provide a network device that may receive alignment information at each physical connection of a network interface of the network device. Each alignment information includes a unique value for identifying a unique logical lane associated with the corresponding physical connection. The network device may determine the order of the unique logical lanes associated with the several physical connections based on the received alignment information. The network device may configure a cross point switch of the network device to reorder the physical connections so that the unique logical lanes associated with the physical connections are ordered according to a defined order.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 5, 2021
    Assignee: Arista Networks, Inc.
    Inventors: Andrew Bruce Bridger, Marc Durrenberger
  • Patent number: 11140239
    Abstract: In aspects of shareable devices, a shareable device implements a device sharing module that can maintain an interactive session of a user on the shareable device. The shareable device can detect that the user has moved away from the shareable device during the interactive session, and obscure personalized content associated with the user who has moved away from the shareable device. The device sharing module is implemented to detect, without user input, a user condition indicative of an intent to end or share the interactive session. The device sharing module can determine a status of an executing application associated with the interactive session of the user. The device sharing module can then end or share the interactive session based on the detected user condition and the determined status of the application.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 5, 2021
    Assignee: Motorola Mobility LLC
    Inventors: John J. Gorsica, IV, Rachid M. Alameh, Robert S. Witte
  • Patent number: 11134459
    Abstract: In a base station, a signal synchronization unit detects a received timing of a signal from a mobile station. A correlation position protection unit corrects the received timing on the basis of time from a transmitting timing at which a signal transmitting operation to the mobile station is started to the received timing. A transmitting timing generation unit generates, on the basis of the received timing after the correction, a transmitting timing at which a subsequent signal transmitting operation to the mobile station is started. Further, an FB frame generation unit generates frame period information that indicates a correction value by the correlation position protection unit, and a transmitting processing unit transmits, to the mobile station, a signal including the frame cycle information in response to the generation of the transmitting timing.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 28, 2021
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Daiki Hoshi, Hiroki Kato, Tatsuhiro Nakada
  • Patent number: 11108681
    Abstract: Disclosed herein is a system (10) for transmitting a data stream (12). The system (10) is configured to receive the data stream (12). The data stream (12) carries a plurality of orders that are destined for a market (24) configured for electronic trading. The system (10) is configured to transmit the data stream (12) carrying the plurality of orders. The system (10) is configured to process at least the plurality of orders (12) to determine trading risk information (14) indicative of trading risk. The system (10) is configured to determine if the trading risk indicated by the trading risk information (14) satisfies a trading risk condition (16). The system (10) is configured to cease transmitting the data stream (12) carrying the plurality of orders if the trading risk condition is determined to be satisfied and commenced transmitting another data stream (18) destined for the electronic market. Also disclosed herein is a method for transmitting a data stream (12).
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: August 31, 2021
    Assignee: Arista Networks, Inc.
    Inventor: David Snowdon
  • Patent number: 11102735
    Abstract: Disclosed is a 5G or pre-5G communication system for supporting a data transmission rate higher than that of a 4G communication system such as LTE. According to one embodiment of the present invention, a method of a base station in a wireless communication system can comprise the steps of: generating a first synchronization signal; confirming symbol index information on a plurality of symbols transmitted through beams in directions different from each other; and transmitting the first synchronization signal and the symbol index information in each of the plurality of symbols.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: August 24, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyunyong Lee
  • Patent number: 11088819
    Abstract: A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 10, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Vivek Sarda
  • Patent number: 11088816
    Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 10, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Vivek Sarda
  • Patent number: 11088682
    Abstract: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Ee Wah Lim, Lay Leng Lim
  • Patent number: 11025252
    Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 1, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Shishir Kumar, Tanuj Kumar, Deepak Kumar Bihani
  • Patent number: 11018844
    Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 25, 2021
    Assignee: NXP USA, INC.
    Inventors: Andres Barrilado Gonzalez, Olivier Vincent Doaré, Didier Salle
  • Patent number: 11013062
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for fast role switching between master and slave roles among wireless nodes. In one aspect, wireless nodes, such as wireless earbuds, coupled to a wireless source, may dynamically and intelligently swap master and slave roles to optimize battery life in the wireless nodes.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 18, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Dishant Srivastava, Mayank Batra
  • Patent number: 10986612
    Abstract: [Object] To adaptively adjust a symbol interval in accordance with a communication environment. [Solution] An apparatus including: a communication unit configured to perform radio communication; and a control unit configured to perform control such that control information for adjusting a symbol interval in a complex symbol sequence into which a bit sequence is converted is transmitted from the communication unit to a terminal, the control information being set on a basis of a predetermined condition.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 20, 2021
    Assignee: SONY CORPORATION
    Inventors: Ryota Kimura, Ryo Sawai
  • Patent number: 10965290
    Abstract: Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 30, 2021
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 10958410
    Abstract: There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period consider
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: March 23, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Christian Rohde, Carmen Wagner, Stefan Lipp
  • Patent number: 10951264
    Abstract: Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Such UWB systems through their receivers may operate in the presence of interfering signals and should provide for robust communications. Accordingly, an accurate and sharp filter that operates at low power is required and beneficially one that does not require a highly accurate power heavy clock. Further, many UWB applications require location and/or range finding of other elements and it would therefore be beneficial to provide a UWB based range finding and/or location capability removing the requirement to add additional device complexity and, typically significant, power consumption.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: March 16, 2021
    Assignee: Transfert Plus, Societe en Commandite
    Inventors: Frederic Nabki, Dominic Deslandes, Mohammad Taherzadeh-Sani, Michiel Soer, Rabia Rassil
  • Patent number: 10931486
    Abstract: Highly efficient digital domain sub-band based receivers and transmitters.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: February 23, 2021
    Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD.
    Inventors: Moshe Nazarathy, Alex Tolmachev
  • Patent number: 10928882
    Abstract: A processing system includes multiple processors in which first processor operates at a first clock frequency and first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and first supply voltage resulting in the first and second processors providing symmetrical multi-processing (SMP) or at a second clock frequency and a second supply voltage resulting in the first and second processors providing asymmetrical multi-processing (ASMP). A third processor may be included that also operates at the first clock frequency and the first supply voltage at all times. Various criteria can be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. A controller enables control and fast-switching between the two modes for the switchable processor.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 23, 2021
    Assignee: Futurewei Technologies, Inc.
    Inventors: Wei Chen, Konggang Wei, Tongzeng Yang
  • Patent number: 10911161
    Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: February 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandeep Oswal, Visvesvaraya Pentakota, Jagannathan Venkataraman, Jaiganesh Balakrishnan, Francesco Dantoni
  • Patent number: 10911930
    Abstract: A communication system as an example of an exemplary embodiment includes two mobile terminals and two BLE terminals. The mobile terminals establish connections with the BLE terminals. Specifically, one of the mobile terminals and one of the BLE terminals are connected together such that the mobile terminal is a central and the BLE terminal is a peripheral. In the state of being connected to the mobile terminal, the BLE terminal communicates with the other BLE terminal in the state of being connected to the other mobile terminal. The BLE terminals may establish a connection with each other and communicate with each other, or may communicate with each other without establishing a connection with each other.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 2, 2021
    Assignee: NINTENDO CO., LTD.
    Inventors: Hiroyuki Takeuchi, Yoshitaka Imura
  • Patent number: 10892852
    Abstract: A master includes a transmission and receiving unit that transmits and receives signals to and from a slave, and the transmission and receiving unit receives read data read out from the slave, and typically drives the second bit of a preamble transmitted/received subsequent to the read data. The master can notify the slave that communication is or is not interrupted at some midpoint, on the basis of the second bit of the preamble. The present technology can be applied to a bus IF that communicates pursuant to, for example, the specification of I3C.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 12, 2021
    Assignee: Sony Corporation
    Inventors: Hiroo Takahashi, Takashi Yokokawa, Sonfun Lee, Naohiro Koshisaka
  • Patent number: 10884451
    Abstract: A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes in response to the transmitted source clock, from the first processing node to the last processing node. The last processing node provides the transmitted source clock as an end clock signal, and provides the transmitted data as end data values. The end data values are written into a FIFO memory in response to the end clock signal. The end data values are subsequently read from the FIFO memory using the source clock signal, and are provided to the first processing node. A synchronizing circuit ensures that a plurality of end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 5, 2021
    Assignee: DeGirum Corporation
    Inventor: Winston Lee
  • Patent number: 10871796
    Abstract: In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 22, 2020
    Assignee: XILINX, INC.
    Inventors: Brian C. Gaide, Chiao K. Hwang, Guoqing Ning, Richard W. Swanson, Wayne E. Wennekamp
  • Patent number: 10861515
    Abstract: An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Kang-Sub Kwak, Sang-Sic Yoon, Young-Jun Yoon
  • Patent number: 10862666
    Abstract: An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi
  • Patent number: 10824187
    Abstract: A signal processing circuit includes: a clock input terminal configured to receive a master clock from outside: a signal processing part configured to perform a signal processing based on the master clock; an interface circuit configured to communicate with an external circuit; and a clock detection circuit configured to determine, using a serial clock received by the interface circuit, whether the master clock is input.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Mitsuteru Sakai
  • Patent number: 10819499
    Abstract: Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 27, 2020
    Assignee: KANDOU LABS, S.A.
    Inventor: Ali Hormati
  • Patent number: 10819633
    Abstract: A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.
    Type: Grant
    Filed: February 4, 2018
    Date of Patent: October 27, 2020
    Assignee: Barefoot Networks, Inc.
    Inventors: Changhoon Kim, Steven Licking, Anirudh Sivaraman Kaushalram, Chaitanya Kodeboyina
  • Patent number: 10797851
    Abstract: A method for synchronization of an input signal includes providing the input signal to a first signal path associated with a first clock and to a second signal path associated with a second clock, detecting an edge of the input signal by detecting values of the input signal along the first signal path at a first rising edge of the first clock and at a second rising edge of the first clock, detecting a value of the input signal along the second signal path at an edge of the second clock, and selecting the input signal from the first signal path or from the second signal path according to the detected value of the input signal along the second path when an edge of the input signal along the first path is detected.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 6, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Jay M. Towne, Steven E. Snyder, Steven Ricco, Matthew Nealon
  • Patent number: 10768920
    Abstract: Software updates within one or more regions of a multi-tenant cloud are coordinated. Tenant vs. tenant conflicts, tenant vs. infrastructure provider conflicts, and conflicts between security and another priority are identified and resolved using a shared update coordinator, update priority specifications, and availability specifications. An infrastructure update request may be presented to tenants for approval. Postponed infrastructure updates may be prioritized higher. Preventing exploits of zero-day vulnerabilities may be prioritized over meeting availability targets. Updates may be merged to reduce downtime, even when the updates originate from independently controlled entities. Maximum downtime, minimum fault domains, minimum virtual machines, permitted update start times, and other availability criteria may be specified. Updates may be preempted, or allowed to complete, based on their relative priorities.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 8, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marcus Fontoura, Mark Russinovich, Yunus Mohammed, Pritesh Patwa, Avnish Kumar Chhabra, Ziv Rafalovich
  • Patent number: 10771104
    Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 8, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peng Wang, Fredrik Berggren
  • Patent number: 10764612
    Abstract: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: September 1, 2020
    Assignee: DISGUISE TECHNOLOGIES LIMITED
    Inventor: Ashraf Nehru
  • Patent number: 10735006
    Abstract: A functional clock generator, including: an oscillator configured to generate an oscillator clock having an oscillator clock frequency; a control value generator configured to generate control values to ramp the oscillator clock frequency between a first frequency and a second, higher frequency; a Phase-Locked Loop (PLL) configured to generate a PLL clock having the second frequency; and a selector configured to switch between selecting the oscillator clock and the PLL clock as a functional clock when the oscillator clock frequency and the PLL clock frequency are substantially equal.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rex Kho, Udo Elsholz
  • Patent number: 10727966
    Abstract: In various implementations, provided are techniques for distributing network time across a network using multiple grand masters (e.g., master time keepers). These techniques include having multiple grand masters simultaneously providing time to the network. Simultaneous means that all the grand masters are active at the same time, and none are designated as backups. In various implementations, the nodes in the network can simultaneously synchronize to network times provided by more than grand masters so that the nodes can obtain more than one network time. Using these multiple network times, nodes configured as clients can determine one network time. The client devices can then use the single network time in applications that require a time.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Erez Izenberg, Nafea Bshara
  • Patent number: 10720958
    Abstract: This disclosure relates to techniques for synchronization signals. The synchronization signal comprise a primary synchronization signal (PSS) generated based on a PSS sequence and a secondary synchronization signal (SSS) generated based on an SSS sequence. The SSS sequence may be generated based on a first sequence corresponding to a first cyclic shift and a second sequence corresponding to a second cyclic shift. The first cyclic shift and the second cyclic shift are associated with Cell ID. The PSS sequence may be generated based on one of the first and the second sequences.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peng Wang, Fredrik Berggren
  • Patent number: 10708107
    Abstract: Phase noise (PN) is suppressed in an OFDM signal. In an initial iteration, an estimation of the PN samples in an OFDM signal vector is produced and the OFDM signal is demodulated using the initial estimation of the PN to generate constellation symbols for the initial iteration. In an additional iteration, an Inverse Fast Fourier Transform of constellation symbols generated in a preceding iteration is calculated to reconstruct preceding samples of the transmitted signal vector. A PN effect on the reconstructed samples is estimated. A next estimation of the PN in a next signal vector is produced based on the estimated PN effect on the reconstructed samples. The next signal vector is demodulated using the next estimation of the PN to generate constellation symbols for the additional iteration. A predetermined maximum number of additional iterations may be used.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 7, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peyman Neshaastegaran, Ming Jian
  • Patent number: 10708751
    Abstract: An apparatus, such as a user equipment or a vehicle, may receive a signal associated with vehicle-to-everything (V2X) communication. The apparatus may determine a total energy that corresponds to the received signal, such as by measuring the energy on one or more resources. The apparatus may determine a fractional energy associated with a first technology of the total energy, such as by detecting a sequence associated with a first technology included in the received signal and determining the energy with which the detected sequence is received. The apparatus may determine presence of a second technology based on the determined fractional energy.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shailesh Patil, Kapil Gulati, Gaurav Gupta
  • Patent number: 10694228
    Abstract: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 23, 2020
    Assignee: DISGUISE TECHNOLOGIES LIMITED
    Inventor: Ashraf Nehru
  • Patent number: 10685691
    Abstract: A storage device includes a first memory chip including a first input pad configured to receive a first input signal, a first initializing circuit configured to generate a first initializing signal, a first input delay circuit configured to delay the first input signal by a first time to generate a first output signal, a first output pad configured to receive the first output signal and output the first output signal, a first clock delay circuit configured to delay the first initializing signal by a second time to generate a first clock signal, a second clock delay circuit configured to delay the first clock signal by a third time to generate a second clock signal, a first latch configured to store the first input signal based on the first clock signal, and a second latch configured to store the first input signal based on the second clock signal.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong Kil Jung
  • Patent number: 10677648
    Abstract: Whether an optical delay on a space optical path is within a light emission cycle is accurately determined without narrowing a range of a measurable distance in the light emission cycle. A DFF 1 that divides an output pulse of a first DLL (121) by two to provide a first time offset and a DFF 2 that divides an output pulse of a second DLL (122) by two to provide a second time offset are included, and at least following mathematical formulas (1) and (2) are satisfied: O1=m·T½??(1) 0<O1<(N?1)·T1??(2) (where, m?1), when a time corresponding to a difference between the first time offset and the second time offset is O1 and the first cycle is T1.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 9, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiki Ikuta, Takuma Hiramatsu, Takayuki Shimizu, Hideki Sato
  • Patent number: 10659099
    Abstract: A page scanning device configured to generate a sequence mask for an expected frequency hopping sequence, select a first tone among a plurality of detected tones, first determine whether the first tone is included within an expected hop sequence, generate a first tone template in response to determining that the first tone is included within the expected hop sequence, align the first tone template with the plurality of detected tones based on the first tone, second determine whether the first tone template matches the plurality of detected tones, and detect a valid frequency hopping sequence in response to determining that the first tone template matches the plurality of detected tones.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ian Appleton, Donald Guy, Michael Cowell, Fei Tong
  • Patent number: 10642570
    Abstract: A method of compensating for a round-trip transmission delay in an audio system comprising: a portable communications device; an audio accessory; and a cable, suitable for connecting the portable communications device and the audio accessory, having at least one wire and being detachable from at least one of the portable communications device and the audio accessory. At first times, a first synchronisation data pattern is transmitted on the at least one wire from said device to said accessory, wherein said first synchronisation data pattern comprises first signal level transitions on the at least one wire, synchronised to a master transmission clock. At second times, a second synchronisation data pattern is transmitted on the at least one wire from said accessory to said device, wherein said second synchronisation data pattern comprises second signal level transitions at timings that are set based on a delay value stored in said accessory.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 5, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: Willem Zwart
  • Patent number: 10630275
    Abstract: Embodiments of a constant-on-time pulse generator circuit for a DC-DC converter, a pulse width calibration circuit for a DC-DC converter, and a method for operating a constant-on-time pulse generator circuit for a DC-DC converter are disclosed. In an embodiment, a constant-on-time pulse generator circuit for a DC-DC converter includes serially connected digital buffers and a latch circuit having a set terminal, a reset terminal, and an output terminal. The set terminal and the reset terminal are coupled to the serially connected digital buffers. The latch circuit is configured to output a pulse signal with a constant pulse width through the output terminal.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP B.V.
    Inventor: Shufan Chan
  • Patent number: 10579578
    Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James Brian Johnson, Brent Keeth
  • Patent number: 10574344
    Abstract: A data transmission system in a communication network comprising a data modulator comprises: a first part at the level of the collection point part comprising: an NCR module taking account of an external absolute time reference to reconstitute a network clock, a transmitter module receiving the value of a time reference to be inserted into the data packet to be transmitted and transmitting to the NCR module an information item on an instant of synchronization for the receiver, a second part at the level of the radiofrequency part of a gateway comprising; a receiver module, a module for reconstructing a clock locally, a module for inserting a time reference into a data packet received by the receiver before transmission of the data via the satellite, the first part and the second part exchange encapsulated data.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 25, 2020
    Assignee: THALES
    Inventors: Mathieu Arnaud, Jean-Luc Almeida, David Arnaud, Cédric Baudoin, Jacques Decroix, Erwan Corbel
  • Patent number: 10528517
    Abstract: Systems and methods for power conservation in a SOUNDWIRE audio bus provide a pulse density modulated (PDM) audio stream at an audio source to an encoder. The encoder has a plurality of encoding states corresponding to bit patterns. The encoder compares bits of the audio stream to available bit patterns and selects an encoding state. The audio source sends the encoding state to an audio sink and then sends data to the audio sink based on encoding using the selected encoding state. The data is sent over a non-return to zero inverted (NRZI) audio bus. As the audio stream changes bit patterns, the encoder may select different more efficient encoding states and provide updates to the audio sink of changes in the encoding state.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sandeep Kumar, Suman Kumar, Lior Amarilio
  • Patent number: 10484046
    Abstract: The systems and methods for a twisted pair transceiver with correlation detection includes a transceiver system operating on a cable. The transceiver system includes a receiver to obtain one or more data samples related to one or more encoded data symbols. The transceiver system further includes a first correlation filter to generate a first correlation output based on the one or more data samples, and a second correlation filter to generate a second correlation output based on the one or more data samples. The transceiver system further includes a detector. The detector compares the first correlation output with the second correlation output, generates an output data bit based on a comparison result, and sends the output data bit for data decoding.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: November 19, 2019
    Assignee: Marvell International Ltd.
    Inventors: Brett McClellan, Kuoruey Han
  • Patent number: 10484165
    Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Rupesh Singh, Ankur Bal
  • Patent number: 10476448
    Abstract: Digital pre-distortion may be provided. First, a characterization for input matching circuitry may be determined. Next, a characterization for non-linearity of an amplifier connected to the input matching circuitry may be determined. Then, a distortion correcting signal may be generated from an input signal based on the determined characterization for the input matching circuitry and the determined characterization for the non-linearity of the amplifier. The generated distortion correcting signal may then be provided to the input matching circuitry.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 12, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Hang Jin, John T. Chapman
  • Patent number: 10469886
    Abstract: A system controller, preferably implemented as a cloud service, enables the synchronization of display devices located at geographically remote locations relative to one another. A display and control devices are provided at each of a plurality of sites, with one or both of the devices being capable displaying the transmitted show. The control device enables the system controller to determine local relative delays in the show and to control the temporal reproduction of said transmitted show by said display device so as to achieve a substantially synchronized reproduction of the show at each of the sites.
    Type: Grant
    Filed: April 6, 2013
    Date of Patent: November 5, 2019
    Assignee: Minerva Networks, Inc.
    Inventor: Fabrizio Capobianco