Abstract: The master device includes a first pad connected to a slave device through a first wire; a second pad connected to the slave device through a second wire; and a communication interface to transmit a communication control signal to the slave device through the first pad, and, through the second pad, to transmit a first data signal synchronized with the communication control signal to the slave device and to receive a second data signal synchronized with the communication control signal from the slave device. The first data signal is transmitted to the slave device by the master device in a write mode and the second data signal is transmitted to the master device by the slave device in a read mode. The communication interface is configured to start the read mode by transiting the communication control signal from a first voltage level to a second voltage level while the second pad has a predetermined voltage level.

Abstract: Various aspects pertaining to apparatuses, methods, and computer-readable medium are described herein. Some aspects pertain to wireless communication between various apparatuses, such as an access point (AP) and a station (STA). The AP may have a radio, and the STA may have a first radio and a second radio. The radios may have various power states. Some aspects pertain to negotiation of various communication parameters. Some aspects pertain to communication of a packet and execution of various related operations. Some aspects pertain to certain uplink (UL) and/or downlink (DL) communications. Some aspects pertain to termination or teardown of the negotiated parameters. The written description and appended drawings provide detailed descriptions regarding these and many other aspects.

Abstract: This application provides a synchronization signal transmission method and a communications apparatus. The synchronization signal transmission method and the communications apparatus are applied to the communications field. In the synchronization signal transmission method, a synchronization signal generated and sent by a network device may include a first sequence and a second sequence. The first sequence is a first complex sequence or a sequence obtained based on the first complex sequence. The second sequence is a sequence obtained based on the first complex sequence, and the second sequence is different from the first sequence. Because a correlation processing result between the first sequence and the second sequence is still a complex sequence, there is a good correlation property, so that a terminal device can obtain a relatively sharp correlation peak when synchronizing with the network device based on the synchronization signal, thereby effectively shortening duration required for synchronization.

Abstract: A synchronization method includes: a first step of transmitting a query command a plurality of times to a communication device configured to perform time synchronization with a base station device connected to a mobile communication network, the query command requesting time information expressed in a first unit, the first unit being lower in accuracy than accuracy of the time synchronization established by the communication device; a second step of determining timing at which the time information obtained in response to the query command is updated; a third step of determining timing to transmit a next query command, based on the timing at which the time information is updated; and a fourth step of acquiring time information with higher accuracy than the first unit, based on time information obtained in response to the query command transmitted at the third step.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: The present technology relates a television apparatus that comprises circuitry configured to receive a digital broadcast signal, extract a packet including content included in the digital broadcast signal, extract time information included in a preamble of a physical layer frame, and send the time information and the packet including the content to other circuitry in the television apparatus. The television apparatus includes a transmission interface configured to interconnect the circuitry and the other circuitry. The television apparatus is further configured to process signaling that includes the time information that is comprised in the preamble of the physical layer frame in the digital broadcast signal.

Abstract: The present application relates to a clock quartz oscillator synchronization method, system and apparatus, in which the method includes, when a calculation unit is in network connection, calculating a first deviation between a calculation unit time and a network clock time; updating a fundamental deviation according to the first deviation; updating the calculation unit time and calculating an actual refresh frequency of the calculation unit according to the fundamental deviation; calculating a second deviation between the calculation unit time and a sensor time; and according to the second deviation, updating the sensor time and calculating an actual interruption frequency of the sensor. The present application provides a synchronization method for calculation, estimation, correction, compensation of time deviation caused by the clock quartz oscillator, which has a benefit of time deviation reduction when one or more sensors are in data exchange with one or more calculation units.

Abstract: A device providing temporary pairing for wireless devices may include a memory and at least one processor configured to receive a request to temporarily pair with a wireless device. The at least one processor may be further configured to pair with the wireless device, wherein the pairing comprises generating a link key for connecting to the wireless device. The at least one processor may be further configured to connect to the wireless device using the link key. The at least one processor may be further configured to initiate a timer upon disconnecting from the wireless device. The at least one processor may be further configured to automatically and without user input, delete the link key when the timer reaches a timeout value without having reconnected to the wireless device using the link key.

Abstract: Embodiments of this application provide a method, apparatus, and system for determining a synchronization cycle, and relate to the communications field, to determine a proper synchronizing cycle, so that air interface bandwidth resources are saved during clock synchronization in an industrial factory, energy consumption of UE is reduced, and battery power is saved. The method includes: A network device obtains a crystal oscillator frequency offset f1 of UE; the network device obtains a crystal oscillator frequency offset f2 of an AN; the network device obtains a service synchronization precision requirement t of the UE; and the network device calculates a synchronization cycle of clock synchronization between the UE and the AN based on the obtained f1, f2, and t.

Abstract: Systems, methods, and devices for generating a constant bitrate (CBR) transport stream in manners that facilitate subsequent reconstruction, and for performing such reconstruction are disclosed herein. For example, generating a CBR transport stream may include for each payload packets: sampling a clock source to obtain a clock sample; and inserting an encoding of the clock sample in a stuffing area of a header of the payload packet. For example, reconstructing a CBR transport stream may include receiving a plurality of packets of a variable bitrate (VBR) transport stream; for a pair of adjacent packets in the VBR transport stream: extracting a clock sample from a header of each of the pair adjacent packets; computing a delta between the clock samples; and inserting one or more null packets between the adjacent packets based on the computed delta and a timing metric corresponding to a bitrate of the CBR transport stream.

Abstract: A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.

Abstract: A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.

Abstract: A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.

Abstract: The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.

Abstract: A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.

Abstract: A phased approach to training of an upstream burst mode receiver equalizer is disclosed that proceeds incrementally through modulation schemes requiring increasing levels of equalization in a manner where the equalizer maintains the capability to accurately recover data transmitted during each training phase. The phased approach includes an initial training phase (one or more upstream bursts) using a simple modulation format, one or more intermediate phases of different modulation schemes, and a final training phase using the PON-defined (high) line rate upstream modulation format. Equalizer settings generated during the initial phase are used as a starting point for the equalization process in the next training phase, and so on, until the equalizer training reaches the final phase where the ONU uses the PON-defined upstream data rate and the burst mode equalizer is updated accordingly.

Abstract: Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.

Abstract: An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.

Abstract: An electronic device is provided. The electronic device includes a communication module, a memory, and a processor operatively connected to the communication module and the memory, the processor is configured to transmit a synchronization signal for generating a synchronization marker to a first sensor device and a second sensor device, receive and store first sensor data, receive and store second sensor data, select reference data serving as a reference from among the first sensor data and the second sensor data, detect the synchronization marker, calculate a required time between synchronization markers of the reference data based on stored sampling information of the reference data and positions of the synchronization marker included in the reference data, and correct and store sampling information of the remaining sensor data other than the reference data.

Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.

Abstract: Exemplary method, system, device and computer-accessible medium can be provided for synchronizing a plurality of sensor systems with respect to a respective phase for providing data. For example, each of the sensor systems can periodically provide the data. This can be done by, e.g., (i) generating a phase request from at least one processing unit for each of the plurality of sensor systems, whereas the processing unit(s) can be configured to receive the data from the plurality of sensor systems, (ii) analysing all phase requests to ascertain executeability thereof, (iii) generating target phase requests if the phase requests have been determined and/or confirmed as being executable, and (iv) transmitting the respective target phase requests to the respective sensor systems for synchronizing the phases of the plurality of the different sensor systems.

Abstract: A clock generating circuit includes a control circuit and a phase interpolator. The control circuit converts an input signal to generate an encoded signal having multiple bits and adjusts arrangement of the bits according to a pointer to generate a control signal having multiple control bits. The phase interpolator includes a first driving circuit, a second driving circuit and an output terminal configured to output an interpolated clock signal. The first driving circuit receives a first clock signal and includes multiple first driving units that are turned on or off to drive the first clock signal in response to multiple first control bits in the control bits. The second driving circuit receives a second clock signal and includes multiple second driving units that are turned on or off to drive the second clock signal in response to multiple second control bits in the control bits.

Abstract: An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

Abstract: The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.

Abstract: A test and measurement system has a test and measurement instrument, a test automation platform, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive a waveform created by operation of a device under test, generate one or more tensor arrays, apply machine learning to a first tensor array of the one or more tensor arrays to produce equalizer tap values, apply machine learning to a second tensor array of the one of the one or more tensor arrays to produce predicted tuning parameters for the device under test, use the equalizer tap values to produce a Transmitter and Dispersion Eye Closure Quaternary (TDECQ) value, and provide the TDECQ value and the predicted tuning parameters to the test automation platform.

Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.

Abstract: Systems, methods, and devices estimate timing values for data transmission associated with wireless communications devices. Methods include receiving, at a transceiver of a wireless communications device, at least one symbol included in a data transmission, obtaining a plurality of samples of the at least one symbol, and generating, using one or more processors, a plurality of correlation values for each of the plurality of samples. Methods further include generating, using the one or more processors, a multi-sample interpolation model based on at least some of the plurality of correlation values and determining, using the one or more processors, an estimated maximum correlation value and a temporal offset value based on the multi-sample interpolation model, the temporal offset value being used for a time of arrival computation.

Abstract: Precision digital chronography based on detected changes in state of a processor is described. The changes in state may be detected by another processor and an averaged time interval generated. A signal corresponding to the averaged time interval may be communicated to a distributed database and propagated to remote systems. Devices associated with the remote systems may adjust or set a device clock in accordance with the averaged time interval.

Abstract: A method for operating a redundant automation system for controlling a technical process in which two-out-of-three system with three subsystems are operated, wherein a comparator is cyclically operated in each subsystem and compares the first, second and third output data with one another, and a respective comparator is operated such that, during each comparison in which the result is that all output data are approximately the same, no further action is performed, and during a comparison in which deviations between the output data are determined, that subsystem in which the deviations of its own output data from the other output data are the greatest is identified as faulty via a majority decision.

Abstract: A test and measurement instrument has an input configured to receive a signal from a device under test, a memory, a user interface to allow the user to input settings for the test and measurement instrument, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to: acquire a waveform representing the signal received from the device under test; generate one or more tensor arrays based on the waveform; apply machine learning to the one or more tensor arrays to produce equalizer tap values; and apply equalization to the waveform using the equalizer tap values to produce an equalized waveform; and perform a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test.

Abstract: Sequences to synchronize devices and related methods are disclosed herein including an access address generator to cryptographically generate a first bit sequence, an access address selector to read a first portion of the first bit sequence and read a second portion of the first bit sequence, the second portion different than the first portion, an access address analyzer to identify a first access address from a first section of the first portion based on a first criteria, the first criteria a function of a first autocorrelation function and identify a second access address from a second section of the second portion based on a second criteria, the second criteria a function of a second autocorrelation function.

Abstract: Provided is a zero crossing point signal output method, including: continuously receiving zero crossing point square wave signals, and periodically sampling zero crossing point square wave signals at a predetermined sampling frequency; acquiring sampling numbers of 1st to Mth zero crossing point square wave signals to obtain an average sampling number S, and calculating a first zero crossing point interval T1; setting a zero crossing point signal output interval as the first zero crossing point interval T1; continuously outputting zero crossing point signals with an interval being the zero crossing point signal output interval; obtaining sampling numbers of M+1th to M+Nth zero crossing point square wave signals, calculating a difference value between each of the sampling numbers and S, and obtaining an accumulated difference value ?s through calculation; when ?s is not within a predetermined change range, obtaining a second zero crossing point interval T2 and setting the zero crossing point signal output inte

Abstract: Embodiments of the present disclosure relate to methods and apparatuses of synchronization signal transmission and receiving in a wireless communication system. The method of synchronization signal transmission in a wireless communication system may comprise transmitting a signal set containing one or more synchronization signals, wherein the one or more synchronization signals are transmitted in a predetermined signal transmission pattern within a signal transmission period, and wherein the predetermined signal transmission pattern indicates information on synchronization signal transmission. With embodiments of the present disclosure, it may indicate the information on synchronization signal transmission information by means of the signal transmission mode. Thus, especially for an initial access process, it can provide a common frame for both single beam based deployment and multi-beam based deployment.

Abstract: One embodiment of the present invention sets forth a technique for communicating within a network. The technique includes receiving, from a first node in the network and at a first receive time, a first periodic beacon that includes a first network time associated with the first node. The technique also includes determining a first transmission time of a first unicast message to the first node based on the first network time and a unicast interval between consecutive unicast listening times on the first node. The technique further includes transmitting the first unicast message to the first node at the first transmission time.

Abstract: A test and measurement instrument, such as an oscilloscope, having a Nyquist frequency lower than an analog bandwidth, the test and measurement instrument having an input configured to receive a signal under test having a repeating pattern, a single analog-to-digital converter configured to receive the signal under test and sample the signal under test over a plurality of repeating patterns at a sample rate, and one or more processors configured to determine a frequency of the signal under test and reconstruct the signal under test based on the determined frequency of the signal, the pattern length of the signal under test, and/or the sample rate without a trigger.

Abstract: A method for communication in a network that includes multiple nodes having respective network interfaces and interconnects between the network interfaces, which include at least first and second network interfaces connected by a physical interconnect having a given latency. The method includes defining a target latency, greater than the given latency, for communication between the first and second network interfaces. Data are transmitted between the first and second network interfaces over the physical interconnect while applying, by at least one of the first and second network interfaces, a delay in transmission of the data corresponding to a difference between the target latency and the given latency.

Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

Abstract: Optical transmitters and receivers for improving synchronization of data transmitted over an optical network are described. The receiver can perform non-linear filtering as part of framer index estimation operations to improve the synchronization. The receiver can determine estimated positions of framer indices in data frames received from the transmitter. Next, using a non-linear filter, the receiver can remove estimated positions that are likely erroneous or are greater than a threshold away from the median or mode estimated framer index position. By removing the likely erroneous estimated positions, the receiver can then determine the estimated position of a framer index position for multiple frames with greater confidence.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Abstract: Precision digital chronography based on detected changes in state of a processor is described. The changes in state may be detected by another processor and an averaged time interval generated. A signal corresponding to the averaged time interval may be communicated to a distributed database and propagated to remote systems. Devices associated with the remote systems may adjust or set a device clock in accordance with the averaged time interval.

Abstract: A phase-shifted sampling module for sampling a signal is described. The phase-shifted sampling module includes a primary sampler module, an ADC module, and an equalization module. The primary sampler module includes an analog signal input, a first signal path, and a second signal path. The equalization module includes a primary sampler equalizer sub-module. The primary sampler equalizer sub-module is configured to compensate low-frequency mismatches between the first signal path and the second signal path. Further, a method for determining filter coefficients of an equalization module of a phase-shifted sampling module is described.

Abstract: A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

Abstract: A method for execution by a low voltage drive circuit (LVDC) operably coupled to a bus includes, when activated, setting data reception for a control channel of a plurality of channels on the bus, where the control channel is a sinusoidal signal having a known frequency. The method further includes receiving the control channel and capturing a cycle of the control channel when the control channel is void of a data communication. The method further includes comparing the cycle of the control channel with a cycle of a first receive clock signal of the LVDC and when the cycle of a first receive clock signal compares unfavorably to the cycle of the control channel, adjusting phase and/or frequency of the cycle of the first receive clock signal to substantially match phase and/or frequency of the cycle of the control channel to produce an adjusted first receive clock signal.

Abstract: A transmitter includes output drivers respectively corresponding to data transmission lines, driver control logic configured to control the output drivers in response to data pattern information, and a data pattern detector configured to detect a data pattern in relation to at least two data transmission lines among the data transmission lines over a predetermined period of time, and output the data pattern information corresponding to the data pattern.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: Systems and methods are disclosed herein that relate to Peak-to-Average Power Ratio (PAPR) reduction in a MIMO OFDM transmitter system. In some embodiments, a method of operation of a transmitter system includes, for each carrier of two or more carriers, performing precoding of frequency-domain input signals for the carrier to provide frequency-domain precoded signals for the carrier, the frequency-domain input signals for the carrier being for a plurality of transmit layers for the carrier, respectively. The method further includes processing the two or more pluralities of frequency-domain precoded signals for the two or more carriers, respectively, in accordance with a multi-carrier processing scheme to provide a plurality of multi-carrier time-domain transmit signals for a plurality of antenna branches, respectively, of the MIMO OFDM transmitter system.

Abstract: A multi-level signal receiver includes a data sampler having (M?1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M?1) reference voltages, to thereby generate (M?1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M?1) sense amplifiers by: (i) adjusting at least one of (M?1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M?1) reference voltages during a second training mode, based on equalized values of the (M?1) comparison signals, where each of the (M?1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

Abstract: A method of operating a communicator includes operating a first receiver of a plurality of receivers on a first channel of a series of channels. A second receiver of the plurality of receivers is operated on a second channel of the series of channels. A third receiver of the plurality of receivers is operated on a third channel of the series of channels. The second receiver that operates on the second channel includes a reception overlap period of about 25% to about 75% with the first receiver that operates on the first channel and a reception overlap period of about 25% to about 75% with the third receiver that operates on the third channel.

Abstract: A device for retrieving media includes a memory configured to store media data of a media presentation; and one or more processors implemented in circuitry and configured to: retrieve a manifest file for a media presentation indicating that container parsing of media data of a bitstream can be started at a resync point of a segment of a representation of the media presentation, the resync point being at a position other than a start of the segment and representing a point at which the container parsing of the media data of the bitstream can be started; use the manifest file to form a request to retrieve the media data of the representation starting at the resync point; send the request to initiate retrieval of the media data of the media presentation starting at the resync point; and present the retrieved media data.