Abstract: A method and a communication modem for broadband communication over power transmission lines. The modem includes a coarse level synchronization mapping unit which maintains a regularly updated coarse level clock synchronization map of neighboring communication units with which it is likely to exchange communications; and a second level synchronization unit which utilizes session handshakes and session data capacity to increase the synchronization level with a neighboring communication unit to allow a communication session to be held at a higher modulation level than the coarse level synchronization is able to support.

Abstract: A method and system are provided which combine (i) adaptive multi-rate half-rate transmission and (ii) intelligent frequency hopping wherein frequency hopping and intelligent underlay overlay are used simultaneously. In the latter, frequency hopping is controlled on a frequency group by frequency group basis, and one frequency hopping group is made up of one or more regular transmitters of a cell and another frequency hopping group is made up of one or more super reuse (super layer) transmitters of the cell. A wireless terminal (e.g., handset) is used in determining the carrier to interference (C/I) ratio for a received signal. A determination is then made as to whether the C/I ratio is acceptable for super layer transmission, and, if the ratio is acceptable, a super reuse transmitter operating in the superlayer range at the half-rate transmission rate is used to transmit a call to the terminal.

Abstract: A processor-implemented method of estimating the saturation level of a transmitter from a transmitted communication signal received from the transmitter comprises generating a received data signal from the transmitted communication signal received from the transmitter, generating a transmitted data signal from the received data signal that corresponds to the actual data signal generated at the transmitter, comparing the transmitted data signal to the received data signal, and estimating the saturation level of the transmitter based on the comparison of the transmitted data signal to the received data signal.

Abstract: In order to transmit a large amount of data in series at a time with a MIMO communication scheme while avoiding deterioration of decoding characteristics due to change over time by a channel matrix, a wireless communication system uses an open-loop type and a closed-loop type of MIMO communication modes in combination and switches to the open-loop MIMO communication mode in response to the information that the amount of data to be transmitted at a time has exceeded a predetermined amount of bits or a predetermined transmission time during data transmission under the closed-loop MIMO communication mode. By discontinuing useless closed-loop MIMO communication and switching to the open-loop MIMO communication mode that is better than Zero-forcing, the decoding characteristics are prevented from simply becoming deteriorated.

Abstract: A multi-channel processing module is arranged in series with multiple channels of a communication system. The processing module synchronizes downstream symbols among the channels, and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel. The synchronization of downstream symbols among the channels and the synchronization of downstream symbols for at least the given channel with upstream symbols for that channel are collectively achieved by adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths in the multi-channel processing module. The channels may comprise respective subscriber lines of a DSL communication system.

Abstract: A system and method provides accurate time generation in a computing device that includes a computing device clock and a microprocessor. The method includes determining a total system latency based on a delay incurred between issuance of a first command by the microprocessor and receipt of a first time-data signal by the microprocessor. The first time-data signal is representative of a master clock output of a master clock device at a first time. The method also includes deriving an accurate time from a second time-data signal. The second time-data signal is representative of the master clock output at a second time known by the microprocessor. The method further includes adjusting the accurate time based on a percentage of the total system latency to form a latency adjusted time, and applying the latency adjusted time to the computing device clock to synchronize the computing device clock to the master clock output.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: Methods and apparatus for aligning the transmitters of two or more bidirectional ports of an integrated circuit (IC), particularly an application-specific IC (ASIC) or field-programmable gate array (FPGA). Misalignment of two or more transmitters is determined by the IC itself without the use of external test equipment. Receivers of the bidirectional ports whose transmitters are to be aligned are used by the IC to detect misalignment. Any misalignment of the receivers is also determined and either eliminated or taken into account when aligning the associated transmitters. Variants for ICs with and without internal loop-back capability and for ICs with and without differential outputs are described.

Abstract: Techniques for correcting time synchronization inaccuracy caused by asymmetric delays on a communication link. Time synchronization according to the present techniques includes determining an asymmetry in a propagation delay on a communication link used by a first device and a second device to exchange timing information and incorporating the asymmetry into a determination of a clock offset between the first and second devices.

Abstract: A method and device may determine the absence of a periodic signal or the absence of an edge of the periodic signal. The periodic signal may be a transmitted clock signal in a forwarded clock architecture. The periodic signal may be delayed by a fixed phase difference to produce a delayed periodic signal. The phase difference between the periodic signal and the delayed periodic signal may be determined. If the determined phase difference is above or below the fixed phase difference by a predetermined amount or more the periodic signal may be missing an edge. If the absence of the periodic signal or the absence of the edge of the periodic signal is detected, an error signal may be asserted. The error signal may be an in-band reset signal.

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network.

Abstract: A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.

Abstract: Methods and systems for calibrating a frequency of a circuit are disclosed herein and may comprise dividing a feedback frequency of an output frequency signal to generate a divided frequency signal. Open loop calibration may be performed based on a binary search of the generated divided frequency signal to generate a coarse calibrated frequency signal. Subsequently, a closed loop calibration may be performed on the coarse calibrated frequency signal to generate a fine calibrated frequency signal. A binary code may be generated utilizing the binary search of the generated divided frequency signal. Capacitance within the circuit may be adjusted based on the generated binary code. A control voltage for the circuit may be measured by closing a phase locked loop (PLL) with the circuit. If the measured control voltage is not within a determined voltage range, a calibration flag signal may be generated.

Abstract: A method of generating beam-forming weights in an orthogonal frequency division multiplexing network is provided. The method includes generating a plurality of sub-bands. Each sub-band comprises a plurality of sub-carriers. A single beam-forming weight is generated for each sub-band.

Abstract: A method of transmitting data can include pre-emphasizing data for transmission by a transmitter over a transmission line based on an error feedback signal provided to the transmitter from a receiver of the pre-emphasized data.

Abstract: Methods and apparatus to determine a relative change relationship between modem and frame clocks are generally described herein. Other embodiments may be described and claimed.

Abstract: For signals to be transmitted through a signal transmission path constituted by a relay device group for relay for each set of a plurality of channels, a timing adjustment unit is provided in both or one of a receiver-side LSI and a transmitter-side LSI for each set of a plurality of channels transmitted through the relay device group for relay so that the signals can be transmitted with accurate timing. In addition, the timing adjustment unit can adjust the timing for signals transmitted through each relay device group, the timing in one receiver-side LSI in signal transmission through a plurality of relay device groups, and the timing in one-to-many signal transmission in which signals are transmitted from one transmitter-side LSI to a plurality of receiver-side LSIs.

Abstract: A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the reception data buffer unit, a variable clock generation unit generating a clock having a variable frequency, a time information output unit outputting second time information counted in accordance with the frequency of the clock generated by the variable clock generation unit, and a first time information comparison unit comparing the first time information added to the packets with the second time information outputted from the time information output unit and controlling the timing of outputting the packet stored in the reception data buffer unit. The reception data amount measuring unit controlling the frequency of the clock generated by the variable clock generation unit in accordance with measured values obtained by the reception data amount measuring unit.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.

Abstract: A slave radio station establishes communization with a master radio station by transmitting a signal intermittently, listening for a response, and saving power by deactivating its transmitter and receiver at other times. When the master radio station responds, the slave station may synchronize periods of receiver activation with a beacon signal transmitted periodically by the master station and may cease transmission of the intermittent signal.

Abstract: Systems and methods for synchronizing a receive clock signal phase with a transmit clock signal phase are presented. A system includes a receiving channel and a transmitting channel, wherein the transmitting channel synchronizes a transmit clock signal phase with a receive clock signal phase based on receive clock signal phase data. A method includes storing a previous receive clock signal phase of a receiving channel and identifying a current receive clock signal phase of the receiving channel. The method further includes determining a phase difference between the previous receive clock signal phase and the current receive clock signal phase, and identifying a direction of the phase difference. The method further includes adjusting a previous transmit clock signal phase of the transmitting channel to a current transmit clock signal phase of the transmitting channel based on the phase difference and direction.

Abstract: To synchronize time between network devices equally capable of accurately maintaining an indication of current time, one of the network devices is deemed to be a reference for time and the other network devices synchronize their indications of current time to the reference. To synchronize copies of data at multiple network devices, each network device maintains a counter representative of the passage of time but not necessarily of current time. The counter at each device is periodically synchronized with the counters of other network devices. When data is changed at a network device, the value of the counter at the time of changing is stored in association with the changed data. Stored counter values are used to determine whether a local copy or a remote copy of the data is likely more recent and therefore preferable. A further test may be applied if a counter value comparison is inconclusive.

Abstract: For signals to be transmitted through a signal transmission path constituted by a relay device group for relay for each set of a plurality of channels, a timing adjustment unit is provided in both or one of a receiver-side LSI and a transmitter-side LSI for each set of a plurality of channels transmitted through the relay device group for relay so that the signals can be transmitted with accurate timing. In addition, the timing adjustment unit can adjust the timing for signals transmitted through each relay device group, the timing in one receiver-side LSI in signal transmission through a plurality of relay device groups, and the timing in one-to-many signal transmission in which signals are transmitted from one transmitter-side LSI to a plurality of receiver-side LSIs.

Abstract: A data transmission method for a data transmission system including a first device and a second device is disclosed. The method comprises the steps of transmitting a clock signal to synchronize the first device and the second device; transmitting a mode signal from the first device to the second device, wherein the mode signal indicates a transmission mode between the first device and the second device; and transmitting a serial data between the first device and the second device based on the clock signal, wherein the length of the serial data is determined based on the transmission mode.

Abstract: According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

Abstract: A communication system, reception apparatus and method, recording medium and program are provided. A technique is provided wherein, even where means for synchronizing a reception clock with a transmission clock is not available, data transmitted can be received accurately with a high transmission capacity assured. The frequency of a transmission clock used by an apparatus of the sender side of data is set equal to that of a reception frequency used by an apparatus on the receiver side. If a sampling timing and a changing point of the value of transmission data do not coincide with each other, then the value of 1 or 0 of a noticed bit is decided from a sample value. However, if they coincide with each other, then the sample value assumes an intermediate value different from 1 and 0, and the value of the noticed bit is decided as a value opposite to the value of the immediately preceding bit.

Abstract: A communications system includes a transmitter that transmits a modulated signal having encoded communications data over a communications channel. The transmitter adjusts one of at least modulation and coding at the transmitter based on the received channel state information of the transmitted signal. A receiver determines received signal metrics from the modulated signal. A noise power estimator estimates the noise power of the received communications signal by collecting N data samples from the communications signals, forming a covariance matrix of the N data samples based on a model order estimate, computing the eigenvalue decomposition of the covariance matrix and ranking resultant eigenvalues from the minimum to the maximum for determining the noise power of the received signal. At least one of modulation and coding are adjusted based on the monitored link quality of the communications channel to enhance use of the available channel capacity.

Abstract: The invention relates to a method for synchronizing a transmitter memory area in a transmitter memory in a transmitter apparatus with a receiver memory area in a receiver memory in a receiver apparatus, and to a receiver apparatus. The transmitter memory area stores transmission data as transmission-data packets and the receiver memory area stores received data as received-data packets with associated error status data which respectively indicate an error status for the received-data packets. Before a reference identification is generated in the receiver apparatus, which, following transmission using a feedback message in the transmitter apparatus, is used for memory area synchronization, the error status data for a plurality of the received-data packets are checked in the receiver apparatus until a first received-data packet is ascertained for which the error status data indicate no error status.

Abstract: The invention relates to a method for synchronizing clock pulse devices. According to this method, an emission unit emits at least one narrow-band distant signal; clock pulse devices of receiving units are pre-synchronized by coupling the same to the source of one such distant signal; the emission unit emits a wide-band measured signal after a defined waiting time, and the receiving units receive said signal; and the receiving units correlate the wide-band measuring signal with a homogeneously modulated comparison signal, the receiving time of the wide-band measuring signal and the deviation in the synchronization of the clock pulse devices being determined and compensated on the basis of the correlation result.

Abstract: A system and method for estimating the range between two devices performs two or more ranging estimates with subsequent estimates performed using a clock that is offset in phase with respect to a prior estimate. The subsequent estimate allows estimate uncertainties due to a finite clock resolution to be reduced and can yield a range estimate with a higher degree of confidence. In one embodiment, these additional ranging estimates are performed at n/N (for n=1, . . . N?1, with N>1 and a positive integer) clock-period offset introduced in the device. The clock-period offset can be implemented using a number of approaches, and the effect of clock drift in the devices due to relative clock-frequency offset can also be determined. To eliminate the bias due to clock-frequency offset, a system and method to estimate the clock-frequency offset is also presented.

Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Abstract: A circuit for optimizing the transmission of data on a communication channel is disclosed. According to one embodiment of the invention, a circuit comprises a transmitter circuit having a programmable output characteristic and being coupled to a transmission media. The transmission media receives serial data from the transmitter circuit and couples the data to a receiver circuit by way of the transmission media. A signal quality monitor associated with the receiver circuit generates received signal quality data. Finally, a feedback path couples the received signal quality data to the transmitter circuit.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: An apparatus and a method for synchronization in a channel card in a mobile communication system are provided. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system includes the DSP modem for sending a reference signal, informing of a start of a transmission, to a Field-Programmable Gate Array (FPGA) modem, and the FPGA modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the DSP modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time.

Abstract: A WLAN (Wireless Local Area Network) transmitter or another data communications apparatus is provided that includes a transmission section that is configured to generate signals to be transmitted, and a control section that is connected to the transmission section to control the transmission section dependent on at least two transmission parameters. The control section comprises a state transition controller that is configured to step through a plurality of predefined control states. The control section is configured to apply different transmission parameter modification mechanisms in different control states. The state transition controller is configured to determine the respective next control states based on transmission success and failure statistics.

Abstract: A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

Abstract: Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a phase difference between an absolute time reference signal and a compensated generated input signal, an IRIG encoder configured to couple a present time value with the generated output signal to form an IRIG waveform, a delay difference indicator configured to provide a time interval value based on a comparison of corresponding pulse edges of the generated output signal and the IRIG waveform, and a numerical delay component configured to delay the generated output signal by the time interval value to form the compensated generated input signal used to time-align the IRIG waveform with the absolute time reference signal to form the accurate IRIG waveform.

Abstract: Disclosed is an apparatus and method for adaptive wireless channel estimation. Once a packet is received, this invention analyzes channel interference index for a moving vehicle, and computes a first recursive parameter, a second recursive parameter and an interpolation number. Based on the first recursive parameter and the interpolation number, partial channel information is calculated for further channel estimation by using an interpolation. The parameter of an equalizer is also immediately updated. Cooperating with a decision feedback scheme and based on the second recursive parameter, channel tracking is performed. In order to achieve the adaptive channel estimation for wireless access on the time-variant vehicle environment, the parameter for the algorithm for performing the channel estimation is adjusted.

Abstract: A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between the voltage mode of operation.

Abstract: A method of synchronizing a smart antenna apparatus with a base station transceiver includes receiving at the smart antenna apparatus control signals being communicated from a base station transceiver to one or more mobile stations via an antenna unit. The control signals are operable to be used to synchronize the mobile stations with the base station transceiver. The method further includes executing one or more algorithms using the control signals received by the smart antenna apparatus as input to synchronize the smart antenna apparatus with the base station transceiver.

Abstract: A method, apparatus and system for opportunistic multicasting are described.

Abstract: In a system for characterizing a satellite clock in a satellite, the satellite has a transmitting device configured to emit a transmission signal at a transmission frequency as a function of a state of the satellite clock. The system includes a receiver clock which has a higher precision than the satellite clock. In addition, a receiving device is configured to receive the transmission signal and to determine a received signal therefrom, as well as a received signal frequency and/or phase, using the receiver clock. Finally, an evaluation device is provided which is configured to determine a frequency offset, drift, and/or an Allan deviation of the transmission frequency from the received signal frequency and/or the received signal phase. The evaluation device determines the stability of the operation of the satellite clock or the validity of the time indication of the satellite clock from the determined frequency offset, frequency drift, and/or the Allan deviation, to thereby characterize the satellite clock.

Abstract: A system and method of wireless communication determines received signal timing deviation which is used to generate a timing advance for adjusting wireless transmit receive unit (WTRU) transmissions. An adaptive threshold for measuring the timing deviation is set based on the energy level of received WTRU signals. WTRU signal samples which exceed the threshold are evaluated to determine timing deviation.

Abstract: A mobile communication system capable of increasing communication efficiency and a method therefor are provided, including a receiver for grouping n MCS levels (where n>0) into continuous m MCS levels (where n>m>0) according to the quality of a data channel for transmitting an information signal, and sending information on an MCS group using a pilot signal, and an ACK or an NACK signal, which indicates whether the information signal is completely received; and a transmitter for storing information on the n MCS levels, extracting the m MCS levels according to the information on the MCS group transmitted from the receiver, determining one of the extracted m MCS levels as an initial MCS level, modulating and coding information data to be transmitted according to the initial MCS level and transmitting the result to the receiver, and changing the current MCS level in response to the ACK or the NACK signal.

Abstract: System (10) comprising at least two units (1, 2) with clock functionality, the units being coupled to a common system clock line (SCLK), a common internal clock line (ICLK), and a logic bus (L-BUS), whereby one sole unit (1, 2) is being dedicated as a mater unit at a time. One source clock signal (CLK10, CLK20) of a unit is output on the internal clock line (ICLK) and all PLL devices of all units generates PLL output signals derived from the internal clock signal, the outputs of the PLL devices (CLKP1, CLKP2) being in phase with one another such that switchover from one PLL output signal to another is seamless.

Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: A clock generator is provided for a transmitter in a transceiver adapted to communicate data over a serial data link. The transceiver includes a clock data recovery circuit recovers a receive clock signal and outputs a reference clock signal. The clock generator includes a local clock, a frequency difference detector, and a fractional-N frequency synthesizer. The local clock outputs a local clock signal. The frequency difference detector outputs a fractional frequency difference signal based on a frequency difference between the local clock signal and the reference clock signal. The fractional-N frequency synthesizer outputs a transmit clock signal having a same frequency as the recovered receive clock signal.

Abstract: A system for providing voltage isolation includes the first and second chips, each containing functional circuitry. The chips are interconnected via at least one RF isolation link that provides voltage isolation between the first chip and the second chip and limits common mode signals therebetween.

Abstract: A network monitor includes means for monitoring downstream traffic from a cable modem termination system (CMTS) to a cable modem (CM), means for monitoring upstream traffic from the CM to the CMTS, and means for identifying a data format used by the CMTS and the CM for bi-directional communication.