Abstract: The present invention provides a control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is configured to: control the SDRAM to switch from a bus data access mode to a dynamic pin (DPIN) operating mode; setting value of the at least one register under the DPIN operating mode; and control the SDRAM according to the value of the at least one register.

Abstract: A method of operating a semiconductor device includes receiving a video stream including a plurality of frames encoded in a hierarchical manner. Each frame is classified as one of a plurality of layers, and the plurality of layers includes a first layer and a second layer. The method further includes decoding the frames classified as the first layer in a chronological order, storing the decoded frames classified as the first layer in a decoded picture buffer (DPB), decoding a latest one of the frames classified as the second layer, storing the decoded latest one of the frames classified as the second layer in the DPB, reading the DPB to display the latest one of the frames classified as the second layer, and decoding and displaying the frames classified as the second layer other than the latest one of the frames classified as the second layer in a reverse chronological order.

Abstract: The phased array antenna system is described. The phased array antenna system formed on one or more layers of a printed circuit board (PCB). The phased array antenna system be may include a beam forming network to convert between one or more element signals and a beam signal. The phased array antenna system may include one or more control circuits, where each control circuit may receive the element signals for corresponding antenna element. Each of the control circuits may further may establish a control signal path and an element signal path between the antenna elements and the beamforming network, where the signal path may carry multiplexed element and control signals. The control circuits may include a signal adjustment circuit that may adjust the corresponding element signal (e.g., in phase or amplitude) based on the control signal.

Abstract: The present disclosure relates to systems and methods to implement efficient high-bandwidth shared memory systems particularly suited for parallelizing and operating large scale machine learning and AI computing systems necessary to efficiently process high volume data sets and streams.

Abstract: Video coding using a constructed reference frame may include generating, by a processor in response to instructions stored on a non-transitory computer readable medium, an encoded video and outputting an output bitstream. Generating the encoded video includes receiving an input video stream, generating a constructed reference frame, generating an encoded constructed reference frame by encoding the constructed reference frame, including the encoded constructed reference frame in an output bitstream such that the constructed reference frame is a non-showable frame, generating an encoded frame by encoding a current frame from the input video stream using the constructed reference frame as a reference frame, and including the encoded frame in the output bitstream.

Abstract: A proxy device may change compression of data for a set of local devices. The proxy device may receive compressed data from a remote device, generate first transformed data based on reduction of compression of the compressed data, and transmit the first transformed data to one or more local devices. The proxy device may receive data from a local device, generate second transformed data based on increase in compression of the data, and transmit the second transformed data to the remote device.

Abstract: A method for video coding includes encoding or decoding a coding block in a current picture with an affine motion model based inter-picture prediction method in a video coding system, storing affine motion information of the coding block in a history-based motion vector prediction (HMVP) buffer that is configured for storing affine motion information candidates each including affine motion information of a processed affine-coded coding block, and constructing a motion candidate list for a current block that includes at least one candidate selected from the affine motion information candidates stored in the HMVP buffer or derived from one of the affine motion information candidates stored in the HMVP buffer.

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

Abstract: A first computing system receives a user request. The user request includes a first set of data. The first computing system determines that one or more resources have exceeded at least one resource utilization threshold. In response to the determining that one or more resources have exceeded the at least one utilization threshold, a first data transfer rate is modified to a second data transfer rate based on transmitting a first subset of the first set of data to one or more host devices, wherein a second subset of the first set of data is not transmitted to the one or more host devices. The one or more host devices validate the user request against one or more security policies in order to complete or terminate the user request.

Abstract: In some aspects, the disclosure is directed to methods and systems for improved bandwidth for DVB-S2X bonded channels. A high bandwidth stream may be split to a plurality of partial streams, including inserted null packets. Modulators may remove the null packets while maintaining a synchronization counter. The counter value may be inserted in headers of transmitted data packets in reduced bandwidth output streams, without requiring explicit identification of removed or deleted null packets. Downstream modulators may recover and remerge the partial streams via the synchronization counters. As explicit deleted null packet identifiers are omitted, header sizes are reduced, further increasing payload/header efficiency ratios.

Abstract: In one example embodiment, a multimedia codec includes a reader configured to read a first frame in an image group according to a field mode indicated by a mode selection signal, and produce a top field and a bottom field for the first frame. The multimedia codec further includes an encoding component configured to encode the top field in an intra mode and encode the bottom field in an inter mode.

Abstract: A method of enabling processing of a video stream is described. The method comprises establishing a slice width for frames of the video stream; receiving the video stream; dividing, for each frame of the video stream, the frame into vertical slices having the slice width; storing a frame of the video stream in a re-ordered slice based format. Computer-readable storage medium and a device for enabling processing of a video stream are also described.

Abstract: Techniques and tools described herein help manage memory efficiently during video decoding, especially when multiple video clips are concurrently decoded. For example, with clip-adaptive memory usage, a decoder determines first memory usage settings expected to be sufficient for decoding of a video clip. The decoder also determines second memory usage settings known to be sufficient for decoding of the clip. During decoding, memory usage is initially set according to the first settings. Memory usage is adaptively increased during decoding, subject to theoretical limits in the second settings. With adaptive early release of side information, the decoder can release side information memory for a picture earlier than the decoder releases image plane memory for the picture. The decoder can also adapt memory usage for decoded transform coefficients depending on whether the coefficients are for intra-coded blocks or inter-coded blocks, and also exploit the relative sparseness of non-zero coefficient values.

Abstract: A RAM_HIME used for integer pixel motion estimation by an IME stores integer pixel luminance data from a SDRAM while satisfying the conditions that improve efficiency in reading an extracted rectangular area. A RAM_HSME used for motion estimation of quarter-pixel accuracy by a SME stores partial quarter-pixel luminance data while satisfying the conditions that improve efficiency in obtaining a rectangular area after calculation by calculation. A RAM_HMEC used for chrominance data generation of quarter-pixel accuracy by a QPG stores integer pixel chrominance data from the SDRAM while satisfying the conditions that improve efficiency in obtaining rectangular areas after calculation by calculation.

Abstract: In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on a format required by the video decoder. The video decoder also includes a second write port to write uncompressed video data to a second buffer in a second format adapted to provide the uncompressed video data for subsequent processing external to the video decoder.

Abstract: A system and method for reproducing original documents includes scanning an original document to generate image data corresponding to the scanned original document, dividing the image data into a plurality of image data blocks, and compressing the plurality of image data blocks into respective compressed image data blocks, such that data of each compressed image data block is independent of data of each other compressed image data block. Each compressed image data block is stored in a first memory with a respective predetermined beginning address. The first compressed image data block, having a first predetermined beginning address, is accessed from the first memory and decompressed into a first decompressed image data block. At least one image processing function is performed on the decompressed first image data block.