Memory Downsizing Methods (epo) Patents (Class 375/E7.095)
  • Patent number: 12008677
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for compatible compression for different types of image views. A graphics processor may select a first common format of a plurality of common formats for at least one image based on at least one of application data or first metadata associated with the at least one image. The graphics processor may encode the at least one image based on the selected first common format for the at least one image. The graphics processor may select a second common format for the at least one image based on second metadata of the at least one image. The second common format may be identical to the first common format. The graphics processor may decode the at least one image based on the selected second common format for the at least one image.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: June 11, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Srihari Babu Alla, Tao Wang, Andrew Evan Gruber, Matthew Netsch, Richard Hammerstone, Thomas Edwin Frisinger
  • Patent number: 9531403
    Abstract: Methods and systems for adaptive compression include compressing input data according to a first compression ratio; pausing compression after a predetermined amount of input data is compressed; estimating which of a set of ranges a compressed output size will fall within using current settings; and performing compression on a remainder of the input data according to a second compression ratio based on the estimated range.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 27, 2016
    Assignee: NEC Corporation
    Inventors: Erik Kruus, Cristian Ungureanu
  • Patent number: 9524209
    Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 20, 2016
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventors: Alessandro Minzoni, Ni Fu
  • Patent number: 7529413
    Abstract: A method for reducing data amount in an image memory system is disclosed. First, it omits one image column from every N image column in left and right portions of the input image, respectively, based on a predetermined percentage, thereby obtaining an image having a reduced data amount. Next, the image having the reduced data amount is sent to an image encoder to encode and accordingly store an encoded image. Then, the encoded image is transmitted to an image decoder through a transmission channel. Then, the encoded image is decoded by the image decoder as received, thereby obtaining a decoding image. Finally, a pixel insertion is performed on reduced image columns of the decoded image.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: May 5, 2009
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Wen-Kuan Chen
  • Patent number: 7415161
    Abstract: Method and apparatus for reducing memory access while de/compressing multimedia files, videos, or image files. An image is divided into blocks, and a frequency data matrix corresponding to a frequency transformed and quantized block is stored in a memory for later de/compression. The method includes registering a bit plane containing a plurality of bits in a register module, wherein each bit represents whether a corresponding element of the data matrix equals zero. While accessing the memory for the data matrix, if a bit of the bit plane shows that its corresponding element of the data array is zero, the element is not accessed from the memory. In checking bits corresponding to elements not yet accessed; if these bits show that elements not accessed are all zero, accessing for the data array can be terminated without accessing them. Thus, memory access can be reduced to occupy less bandwidth of the memory.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: August 19, 2008
    Assignee: Faraday Technology Corp.
    Inventor: Heng-Kuan Lee