Phased Clocking Patents (Class 377/104)
  • Publication number: 20110317802
    Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least clock edges. A comparator determines whether the difference between the master count and the slave count is at least. In a related aspect, a synchronous circuit comprises a clock tree for transmitting a clock signal from a start point to one or more other points, the start point and the other points comprising a first point and second point. A first counter is clocked by the clock signal at the first point and memorizes a first count. A first incrementer advances the first count by one increment. A second counter is clocked by the clock signal at the second point and memorizes a second count. A second incrementer advances the second count by one increment.
    Type: Application
    Filed: January 5, 2009
    Publication date: December 29, 2011
    Inventors: Michael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
  • Publication number: 20090285034
    Abstract: To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that combines outputs of first latch circuits; a second wired-OR circuit that combines outputs of second latch circuits; a gate circuit that combines outputs of the first and second wired-OR circuits; and reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit. According to the present invention, as compared to a case that outputs of all the latch circuits are wired-OR connected, output loads are more reduced. Thus, a high signal quality can be obtained.
    Type: Application
    Filed: May 18, 2009
    Publication date: November 19, 2009
    Applicant: Elpida Memory, Inc.
    Inventor: Hiroki FUJISAWA
  • Publication number: 20090285048
    Abstract: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.
    Type: Application
    Filed: May 18, 2009
    Publication date: November 19, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiroki FUJISAWA
  • Patent number: 6937688
    Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: August 30, 2005
    Assignee: VIA Technologies Inc.
    Inventors: Yung-Huei Chen, Shan-Ting Hong
  • Patent number: 6853698
    Abstract: A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the ripple counter circuit alternates between two states. In the first state, the bits all toggle from their initialization values to new values. In the second state, the circuit operates in the same fashion as the user mode. Therefore, the ripple counter circuit counts by one, returning all of the bits to their initialization values. This capability significantly simplifies the testing process, particularly for long ripple counters. Some embodiments of the invention include various control circuits coupled to provide an internal clock signal and/or an initialization signal.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: February 8, 2005
    Assignee: Xilinx, Inc.
    Inventor: Andy T. Nguyen
  • Patent number: 6795520
    Abstract: A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: September 21, 2004
    Assignee: Zarlink Semiconductor Inc.
    Inventor: Robertus Laurentius Van Der Valk
  • Patent number: 6735270
    Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: May 11, 2004
    Assignee: LSI Logic Corporation
    Inventor: Kwok Wah Yeung
  • Patent number: 5524037
    Abstract: A circuit configuration generates an even-numbered duty factor with an odd-numbered division n of a symmetrical clock signal. A first device generates a first output signal from the symmetrical clock signal. The first output signal begins upon each n.sup.th edge of one type, of a symmetrical clock signal and remains active for a length of N-1/2 periods of the symmetrical clock signal. A second device generates a second output signal from the symmetrical clock signal. The second output signal begins upon each n.sup.th edge of another type, of the symmetrical clock signal and remains active for the length of N-1/2 periods of the symmetrical clock signal. A logic linkage is connected to the first and second devices for linking the two output signals to form one symmetrical output signal.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: June 4, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gunter Donig, Edmund Goetz, Helmut Herrmann
  • Patent number: 5287394
    Abstract: A fast counter includes a clock generator (18), a control circuit (22), and a counting circuit (12). The counting circuit is formed of at least one uniform delay structure (12a, 12b) having a plurality of counter bit cells (58, 60). The uniform delay structure has a regular configuration suitable for very large scale integration. The fast counter is implemented so as to provide minimal propagation delay at relatively low cost.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: February 15, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Pranay Gaglani
  • Patent number: 5175753
    Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.
    Type: Grant
    Filed: April 1, 1991
    Date of Patent: December 29, 1992
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Pranay Gaglani
  • Patent number: 5120988
    Abstract: A clock generator contained in an integrated circuit has an input terminal, a first output terminal, and a second output terminal. When the input terminal of this clock generator receives a basic clock signal supplied by an external integrated circuit, the first output terminal outputs a first clock signal in response to the basic clock signal, and the second output terminal outputs a second clock signal which is an inverted clock signal of the first clock signal in response to the basic clock signal. When the input terminal receives a constant level signal supplied by the external integrated circuit, the first output terminal and the second output terminal output respectively the same constant level signal to thus provide reduced power consumption.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: June 9, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Matsuki
  • Patent number: 5027382
    Abstract: A shift register circuit comprises a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, where a first one of the first clocked gate inverters is adapted to receive an input pulse signal, an output line connected to an output of each of the inverters for outputting an output pulse signal, and a second clocked gate inverter connected to the output of each of the inverters for outputting an output pulse signal. The first clocked gate inverters operate responsive to a first clock signal, and the second clocked gate inverters operate responsive to a second clock signal which is different from the first clock signal.
    Type: Grant
    Filed: December 15, 1989
    Date of Patent: June 25, 1991
    Assignees: Ricoh Company, Ltd., Ricoh Research Institute of General Electronics Co., Ltd.
    Inventors: Akihiko Hiroe, Noriyuki Terao
  • Patent number: 4974241
    Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.
    Type: Grant
    Filed: March 31, 1989
    Date of Patent: November 27, 1990
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: David C. McClure, Mark A. Lysinger
  • Patent number: 4845727
    Abstract: A pulse train divider circuit includes a first flip-flop (1) whose Q output is connected to the D input of a second flip-flop (2) whose Q output is connected to the D input of the first flip-flop (1). A pulse train to be divided is applied via an input (3) directly to the clock input C of the first flip-flop (1) and via a circuit (4) which delays the pulse train applied to the clock input C of the flip-flop (2) to provide a given phase relationship between the pulse trains at the two clock inputs. The circuit divides-by-two, and the resulting divided pulse trains available at the various outputs have phase relationships depending on the phase relationship of the applied pulse trains at the clock inputs.
    Type: Grant
    Filed: November 19, 1987
    Date of Patent: July 4, 1989
    Assignee: U. S. Philips Corporation
    Inventor: Bruce Murray
  • Patent number: 4587664
    Abstract: An 8.5 divider comprises a first and second 1/2 dividers to produce output pulses having phases different from each other by 90.degree., a first logic gate producing output pulses having a repetition frequency of a half of the input pulses, a third and fourth 1/2 dividers connected in series and dividing twice the output pulses of the first logic gate by two, a fifth 1/2 divider receiving the output of the fourth 1/2 divider, a second logic gate detecting the simultaneous presence of the outputs of the second, third and fifth 1/2 dividers to invert the phase of the output pulses of the first 1/2 divider and a third logic gate detecting the simultaneous presence of the outputs of the first and third 1/2 dividers and the inverted output of the fifth 1/2 divider.
    Type: Grant
    Filed: September 21, 1984
    Date of Patent: May 6, 1986
    Assignee: NEC Corporation
    Inventor: Norihiko Iida
  • Patent number: 4509183
    Abstract: A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.
    Type: Grant
    Filed: September 16, 1982
    Date of Patent: April 2, 1985
    Assignee: Helene R. Wright
    Inventor: Fred R. Wright
  • Patent number: 4464773
    Abstract: A first variant using conventional ratio-type two-phase design with nonoverlapping clock signals consists of a first inverter (I1), a complex gate (KG), a first transfer transistor (T1), a second inverter (I2), and a third inverter (I3) connected in series with respect to the signal flow. The complex gate (KG) consists of two NORed AND elements (U1, U2). The output of the second inverter (I2) is the count-up output (VA), and that of the third inverter (I3) is the count-down output (RA). The count-up output (VA) is coupled through a second transfer transistor (T3), controlled by the second clock signal (F2), to the first input of the first AND element (U1), whose second input is connected to the output of the first inverter (I1).
    Type: Grant
    Filed: May 21, 1982
    Date of Patent: August 7, 1984
    Assignee: ITT Industries, Inc.
    Inventors: Reiner Backes, Friedrich Schmidtpott, Mathew Neal
  • Patent number: 4462110
    Abstract: A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.
    Type: Grant
    Filed: April 7, 1981
    Date of Patent: July 24, 1984
    Assignee: Honeywell Information Systems Inc.
    Inventors: David R. Baldwin, Nicholas S. Lemak