Abstract: An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.

Abstract: The invention relates to methods and apparatus for forming images on a display utilizing a control matrix to control the movement of MEMs-based light modulators.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a low-pass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.

Abstract: A frequency measuring apparatus includes: a high-order digit calculation section adapted to measure an input signal and output a high-order digit value of a frequency value of the input signal; a low-order digit calculation section adapted to measure the input signal and output a low-order digit value of the frequency value of the input signal; and an adding section adapted to add the high-order digit value and the low-order digit value to each other to output the frequency value of the input signal.

Abstract: A frequency divider has an inverting unit and a plurality of switch inverters in series. Each switch inverter comprises two inphase switches and is controlled by a clock. The two inphase switches of each switch inverter are respectively supplied by a first voltage and a second voltage, while any two switch inverters in series are respectively controlled by two inverted clocks. The two inphase switches are selectively turned on and off synchronously.

Abstract: A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the ripple counter circuit alternates between two states. In the first state, the bits all toggle from their initialization values to new values. In the second state, the circuit operates in the same fashion as the user mode. Therefore, the ripple counter circuit counts by one, returning all of the bits to their initialization values. This capability significantly simplifies the testing process, particularly for long ripple counters. Some embodiments of the invention include various control circuits coupled to provide an internal clock signal and/or an initialization signal.

Abstract: A clock divider circuit producing 0° and 90° outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a pair of cross-coupled circuits. The clock divider circuit may produce a first output clock signal and a second output clock signal that is phase shifted a positive 90° with respect to the first output clock signal. The operation of the circuit may be responsive only to the input clock signal. In other words, the circuit may not require a reset signal to operate in a deterministic fashion.

Abstract: A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation.

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A third transistor responsive to an output signal of a stage downstream of the given stage applies a control signal to a gate electrode of the pull-down transistor to render the pull-down transistor conductive.

Abstract: A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes an output circuit which switches the output terminal between high and low states. A first node switches the output terminal in response to an input signal and a second node keeps the output terminal low between the input pulse and a clocking pulse.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.

Abstract: An improved dynamic frequency divider circuit is disclosed. A DC voltage generating circuit (10) generates a DC voltage (Vcon) having a level the same as a threshold voltage of an inverter. A voltage application circuit (41) supplies a voltage (Vcon) to one electrode of a capacitor through a high frequency signal component cut-off coil (8), and a high frequency signal component is superimposed on the provided DC voltage. Accordingly, an input signal of an inverter (1a) swings around the threshold voltage level as a center, so that the inverter (1a) can provide a signal having the duty cycle of 50% as an output. As a result, the dynamic frequency divider circuit can be prevented from malfunctioning.

Abstract: The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, the PMOS gates turn on and pass bit values. At the same time the adjacent NMOS gates, which are driven by the same low clock signal, shut off and prevent the passed bit values from traveling any further. The bit values are thus held between adjacent PMOS and NMOS gates. When the clock signal next goes high, the NMOS gates turn on and pass the held bit values while the PMOS gates driven by the same high clock shut off. The gates are connected by circuitry which essentially holds the bit values passed through the first associated gate until they are passed through the second associated gate. The shift register may also include gated or non-gated refresh circuitry, which operates to maintain a passed bit value.

Abstract: A variable width pulse generator includes a plurality of logic stages which are coupled cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the width pulse.

Abstract: An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and size limitation problems associated with known high speed counters.

Abstract: A frequency divider receives a first frequency signal and at least one clock signal of a sub-multiple of the first frequency. The first frequency signal charges a storage terminal once each first frequency cycle and the sub-multiple frequency signal discharges the storage temrinal once each sub-multiple frequency cycle. The discharged storage terminal sets the frequency divider output which is reset by the first frequency signal when the storage terminal is discharged. The sub-multiple frequency clock signal is employed to control the storage terminal instead of a feedback path from the output to increase the operating frequency of the divider.

Abstract: A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).

Abstract: A scanning pulse generating circuit has a multiplicity of stages constitued by first basic circuits and second basic circuits which are connected to appear alternatingly in a cascade manner. The first basic circuit is composed of three or four MOS transistors and a feedback capacitor, and includes at least a bootstrap inverter, so as to produce predetermined output pulses upon receipt of driving synchronizing pulses. The second basic circuit has the same construction as the first basic circuit except that it receives different driving synchronizing pulse from that used in the first basic circuit. The output pulses from the respective basic circuits are free from drop of voltage and fluctuation, by virtue of the bootstrap effect. In addiition, power consumption can be reduced without difficulty.

Abstract: A clock generating circuit having at least one loop of at least two stages. Each stage consists of a pass transistor serially connected to an inverter. An inverter couples the end of the loop to its beginning. The gate electrodes of the transistors in the serially connected stages are controlled alternatively by a true and a complemented clock signal. Preferably, there are two such loops operating in parallel but which include initialization circuitry that initializes the two loops to complementary values.

Abstract: A shift register circuit, including a plurality of stages capable of preserving data bits entered from an external source and shifting the data bits from stage to stage, each of the stages being driven by phase one, phase two and phase three clock signals, each signal alternating between a first and a second logic level. The shift register circuit comprises a first transistor responsive to the phase one clock signal for transferring a new data bit of either first or second logic level, a series combination of second, third, fourth and fifth transistors, and an output node provided between the third and fourth transistors. The second and third transistors are responsive to the new data bit transferred through the first transistor and the phase two clock signal, respectively, to place the phase three clock signal with the logic level corresponding to that of the new data bit at the output node.

Abstract: A multistage counter circuit comprising a plurality of counters connected in cascade, each providing a carry signal and having signal logic levels at an output of each stage inverted by main clock pulses and sub clock pulses, and means including a flip-flop connected at the output of each stage for synchronizing the carry signal of each stage with the main clock pulses to generate a carry signal to a succeeding stage unafffected by delays in the carry signal of a preceding stage.

Abstract: Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.

Abstract: A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS inverter employing a P-intermediate transistor between both the P- and the N-transistor. The gates of the intermediate transistors are interconnected and controlled by the clock signal, whereas the inverter input is constituted by the interconnected gates of the P- and the N-transistor of each inverter. Such an inverter chain can be used, for example, as a digital pulse width discriminator, as a final position counter, as a circuit for compensating signal drop-outs in input pulses, or else for effecting ring oscillator synchronizations.

Abstract: A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.

Abstract: An electronic D-type flipflop includes two storage elements and two transmission gates wherein each gate includes only one MOS transistor. In the first gate the MOS transistor is of a first conductivity type and it is of a second conductivity type in the second gate. The MOS transistors each receive the same clock signal at their gate electrode. Because it is not necessary to form an inverted clock signal, problems due to phase differences between the clock signal and its inverse are precluded. Each of the storage cells includes a pair of inverters which are coupled end-around. The transmission characteristic of the forward inverting circuit is adapted in such a way that it compensates for the voltage drop across the preceding transmission gate. Only a small substrate surface area will be required when the flipflop is used in an integrated circuit.

Abstract: A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state.

Abstract: A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals.

Abstract: A shift register comprising a plurality of memory cells serially coupled together along a signal bus. Each one of the plurality of memory cells comprises a first amplifier, fed by an input logic signal, for amplifying and inverting the logic state of the input logic signal. A first storage section is included for either enabling storage in the first storage section of an electric charge corresponding to the voltage level of the amplified and inverted input logic signal, or disabling storage in the first storage section of the electric charge, selectively in response to a first control signal. The stored electric charge is converted to an intermediate logic signal having a predetermined voltage level. Each memory cell additionally includes a second amplifier, fed by the intermediate logic signal, for amplifying and inverting the logic state of the intermediate logic signal.

Abstract: A driver circuit for generating non-overlapping clocking signals. A single clocking source is divided down into two clock signals which are passed through a plurality of inverter delay chains to insure non-overlapping output signals. Inverters made up of CMOS transistors having long channel lengths are utilized in order to eliminate overlap between the clock signals. Inverter delay chains are also utilized to prevent skewing between a true clock output signal and its complement.

Abstract: In order to reduce the likelihood of incorrect states being transferred from one cross-coupled transistor pair to the next in a frequency divider which comprises at least two such pairs (6a, 7a and 8a, 9a) which are energized alternately by means of a switchable current source arrangement (5) and which are inter-coupled to form a cyclic arrangement by means of data transfer transistors (6b, 7b, 8b and 9b) energized from the same outputs (22, 23) of the current source arrangement, the transistors employed are of the insulated gate field effect type. The channel width-to-length ratios of the pair transistors (6a, 7a, 8a, 9a) may be chosen to be different from the corresponding ratios for the data transfer transistors (6b, 7b, 8b, 9b) in order to improve either the high-frequency or the low frequency performance in accordance with the sign of such difference.

Abstract: A racefree CMOS clocked logic circuit includes a first CMOS clocked gate for selectively transferring an input signal according to a first clock pulse and providing an interstage signal corresponding to the input signal; and a second CMOS clocked gate, which is connected directly to the first CMOS clocked gate, for selectively transferring the interstage signal according to a second clock pulse and providing an output signal corresponding to the interstage signal. The operation of first CMOS clocked gate is synchronized to the first clock pulse, and the operation of second CMOS clocked gate is synchronized to the second clock pulse. The second clock pulse is in-phase with or identical to the first clock pulse so that signal races between the input signal and the output signal are eliminated.

Abstract: A combination of logic circuits perform logical operations on data and include a plurality of shift register latches. Each shift register latch includes a latch means for the storing of data, an isolation means for isolating the latch means from data and clock signals connected logic circuits when the isolation means is at a first state, and for conducting data to the latch means when the isolation means is at a second state. Each shift register latch also includes a power reduction means for reducing the power consumed by the isolation means and the latch means.

Abstract: A dynamic two-phase circuit arrangement includes two dynamic switching circuits, each of which has an input stage, a non-inverting output stage and an inverting output stage. Two-phase control of the two dynamic switching circuits is effected by two drive pulses. The arrangement also includes combinatorial logic which is operated by the drive pulses to feed counter clock pulses to the first dynamic switching circuit. The first dynamic switching circuit performs a divide-by-two operation in response to the clock pulses and drives the second dynamic switching circuit from its Q-output. The second dynamic switching circuit includes an additional switching transistor which is also driven from the Q-output of the first dynamic switching circuit. This transistor is connected to perform an OR-function with the non-inverting output stage of the second dynamic switching circuit. As a result, this output stage produces shift pulses having half the repetition frequency of the clock pulses.

Abstract: A MOS integrated logic circuit is described which comprises a plurality of groups (61, 63, 65, 67, 69) of combinatory logic elements. These groups form a cascade in that a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charging means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.

Abstract: A D-type latch circuit employing only six insulated-gate field-effect transistors and four diodes includes three CMOS inverters, the first and third of which are modified inverters capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. To accomplish this, each of the first and third inverters includes a pair of isolation diodes. Voltage supply nodes of the second inverter are connected to latch voltage supply nodes for continuously enabling the second inverter.

Abstract: A high speed countdown counter (FIG. 7) capable of operation at up to 10 MHz is provided which comprises a number of stages each comprising a flip flop (134, 136; 144, 146; etc.), a preset data input (IN1, IN2, etc.), a carry input (N11, N10, etc.), a data output (N5, N4, etc.), and a carry output.Dynamic Depletion Mode (DDM) transistors (129, 139, etc.) are employed to reduce charging time at inter-stage nodes and thereby improve speed, while minimizing circuit size and power requirements.A look-ahead feature enables early detection of an "all zero minus one" count and enables the presetting of data into the counter simultaneously with the generation of a "carry out" signal from the counter. Various internal counter control signals are delayed by couplers driven by a two-phase non-overlapping clock, in order to allow for signal propagation time through the corresponding circuit elements.

Abstract: A pulse generator circuit for applying a pulse signal to the input source electrode of a charge coupled device (CCD) having a "fill and spill" input operation, includes a voltage reference circuit for generating the "fill" voltage level of the pulse signal and a capacitive element circuit for boosting the voltage level of the pulse signal to a "spill" voltage level which exceeds the operating potential applied to the pulse generating circuit. With this type of pulse generating circuit the operating potential applied to the CCD and its support circuitry (including the pulse generator circuit) can be reduced in order to lower system power consumption while ensuring proper "spill" operation.

Abstract: A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node.

Abstract: There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the carry-in signal propagates through the counter as a "carry-out" signal. Counting by the circuit occurs when the count input and carry-in signals are active.

Abstract: A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and shifts the selectively received signal to the immediately succeeding unit circuit. The selection-delay unit circuit is only formed of three transfer gates and two inverters in order to reduce a chip size and save power consumption.

Abstract: A dynamic divider circuit comprised of insulating gate field effect transistors and capable of operation using minimal current consumption in a reduced space is provided. Master and slave multiple inverters and an intermediate inverter are formed from complementary connected P-channel and N-channel insulated gate field effect transistors, the master and the slave inverter being directly coupled to the master inverter. The coupling of the master, intermediate, and slave inverters providing reduced current consumption and a more simplified circuit by utilizing the parasitic capacitance of said field effect transistors as a memory.