Abstract: A digital clock generator circuit including a series of inverters connected in cascade with the output of the final stage connected to the input of the first stage in a ring counter fashion. Each inverter includes a first circuit to precharge a node, a second circuit to discharge a node upon occurrence of a selected input signal and a third circuit connected to isolate the node from the circuitry output during the precharge interval. The output of the counter is the output of the final stage. The inverter circuits allow for a low power digital counter by allowing a P-MOS or N-MOS fabrication of devices that do not require continuous power.

Abstract: A frequency generator circuit which provides an output signal which is both synchronous with and proportional in frequency to a clock signal of predetermined frequency in response to an input control signal is provided. A frequency divider portion couples a clock signal of divided frequencies to predetermined control electrodes of series-connected switches which selectively couple an output node to a reference voltage node. A decode portion selectively bypasses predetermined switches in response to the input control signal to selectively couple the reference node to the output node. A latch is coupled to the output node to hold the decoded output signal at a predetermined logic level for a predetermined amount of time.

Abstract: A D-type latch circuit employing only six insulated-gate field-effect transistors and four diodes includes three CMOS inverters, the first and third of which are modified inverters capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. To accomplish this, each of the first and third inverters includes a pair of isolation diodes. Voltage supply nodes of the second inverter are connected to latch voltage supply nodes for continuously enabling the second inverter.

Abstract: A prescaler circuit which provides an output signal which is synchronous with and proportional in frequency to a clock signal is provided. A counter portion counts a predetermined number of cycles of the clock signal and provides a plurality of count signals after a predetermined number of clock signal cycles. A decoder portion is coupled to the counter portion and couples a reference voltage node to a decoder output in response to both an input control signal and the count signals. A latch portion is coupled to the decoder portion for holding the decoder output, and a delay portion is utilized to provide the scaled output signal after a predetermined amount of time delay. The prescaler utilizes both odd and even scaling factors.

Abstract: A multibit counter circuit uses a plurality of essentially identical stages which each have a feedback circuit, a flip-flop, and a carry circuit. Each of the stages is connected together in essentially the same way. A counter circuit of any desired bit capacity can be relatively quickly and easily formed with a saving in silicon area compared to standard configurations.

Abstract: A high speed countdown counter (FIG. 7) capable of operation at up to 10 MHz is provided which comprises a number of stages each comprising a flip flop (134, 136; 144, 146; etc.), a preset data input (IN1, IN2, etc.), a carry input (N11, N10, etc.), a data output (N5, N4, etc.), and a carry output.Dynamic Depletion Mode (DDM) transistors (129, 139, etc.) are employed to reduce charging time at inter-stage nodes and thereby improve speed, while minimizing circuit size and power requirements.A look-ahead feature enables early detection of an "all zero minus one" count and enables the presetting of data into the counter simultaneously with the generation of a "carry out" signal from the counter. Various internal counter control signals are delayed by couplers driven by a two-phase non-overlapping clock, in order to allow for signal propagation time through the corresponding circuit elements.

Abstract: This invention concerns counters.More specifically, it relates to a non-volatile counting decade, comprising five flipflops, the outputs of which represent the decimal contents of the decade in the Johnson code. In this code, no flipflop changes its state more than twice in the course of a counting cycle from 0 to 10. The state of the counter is safeguarded on every incrementation, in separate safeguard circuits for each flipflop, formed of MNOS or floating-base transistors. However, any flipflop output state is safeguarded only if its state has changed after incrementation, this being detected by a logic circuit, which selects the safeguard signal for each flipflop.By means of an extremely simple combinative circuit, this invention thereby greatly reduces the number of writing cycles to be performed by the MNOS or floating-base transistors, which cannot withstand an excessive number of writing cycles.

Abstract: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node.

Abstract: The present invention provides a circuit comprising (1) a logic element responsive to data of first and second negative voltage potentials, the logic element having a depletion mode MESFET data input gate, and (2) a depletion mode MESFET transmission gate operatively associated with the data input gate for enabling the selective serial transmission of data therethrough to the logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage of the data input gate being between approximately the first and second negative voltage potentials, the pinch-off threshold voltage of the transmission gate being between approximately the third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more

Abstract: There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the carry-in signal propagates through the counter as a "carry-out" signal. Counting by the circuit occurs when the count input and carry-in signals are active.

Abstract: GaAs digital electronics uses mainly depletion mode MESFET technology. In typical circuits, negative voltage logic input signals are required while the output voltage is positive. To connect gates, level shifters are needed to shift the positive voltage output signals such that they become suitable for the input to the next gate. A capacitor is used which performs the level shifting. As the charge leaks off the capacitor, the voltage level has to be readjusted periodically, leading to a "dynamic" circuit. A method for self-biasing of the capacitor for readjustment of the voltage level is taught.

Abstract: A dynamic divider circuit comprised of insulating gate field effect transistors and capable of operation using minimal current consumption in a reduced space is provided. Master and slave multiple inverters and an intermediate inverter are formed from complementary connected P-channel and N-channel insulated gate field effect transistors, the master and the slave inverter being directly coupled to the master inverter. The coupling of the master, intermediate, and slave inverters providing reduced current consumption and a more simplified circuit by utilizing the parasitic capacitance of said field effect transistors as a memory.

Abstract: A frequency divider for electric timepieces or the like comprising a first block composed of even clock controlled inverters connected in cascade, a second block composed of even clock controlled inverters connected cascade and a clock controlled signal compounding circuit. The final stage output terminal of the first block is connected to a second input terminal of the clock controlled signal compounding circuit.